DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 21, and 27 are amended. Claims 11-20 are cancelled. Claims 1-10 and 21-30 are present for examination.
Response to Arguments
The amendment filed January 23, 2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
“base region” in line 5 of claim 1; ”… wherein the stacks of n-type and p-type nanostructures are disposed above a base region over the substrate …”
“base region” in lines 6-7 of claim 1; “… an isolation structure over the substrate and laterally surrounding the base region …“
“base region” in line 7 of claim 1; wherein the dielectric wall is vertically above the base region and laterally between portions of the isolation structure
Applicant is required to cancel the new matter in the reply to this Office Action.
Applicant’s arguments, see pages 7-11, filed January 23, 2026, with respect to the rejection(s) of claim(s) 21 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Do (US 2022/0189944 A1).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
The term “substantially” in claim 27 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
“… wherein the first and the second gate interconnects have a substantially coplanar top surface and are of different dimensions.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su (US 2021/0134944 A1).
Claim 1, Su discloses a semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7), comprising:
a forksheet structure (structure of semiconductor device is a forksheet as it has a metal gate electrode 106 over a stack of nanosheet channels 502/504 separated into two portions by a dielectric fin structure 112 which functions as a forksheet dielectric wall, hereinafter, forksheet structure 502/112 or 404, [0044], CMOS device 404 is a forksheet structure, Figs. 7 and 35) over a substrate (502/112 is over a substrate 202, [0044], Fig. 7) and extending lengthwise along a first direction (502/112 extends in the y-direction which is a first direction, [0044], Fig. 7), the forksheet structure 502/112 having a dielectric wall 112 separating a stack of n-type nanostructures from a stack of p-type nanostructures (forksheet structure 502/112 has 112 separating adjacent nanostructure stacks, wherein the channels 502 in contact with first gate electrode 3302 are a material associated with a first work function (e.g. p-type), hereinafter, p-type nanostructures 502/3302, and the channel 502 in contact with second gate electrode 3304 are a material associated with a second work function (e.g. n-type), hereinafter, n-type nanostructures 502/3304, [0090], Fig. 7, Annotated Fig. 33);
a gate structure (gate structure 3302/3304 may be composed of an electrode that further may be an individual or split gate, wherein for a split gate structure, a first gate electrode 3302 and a second gate electrode 3304 are in contact with channel 502, [0089], Figs. 7 and 33) over the forksheet structure 404 and extending lengthwise along a second direction perpendicular to the first direction (gate structure 3302/3304 extends in the x—direction which is a second direction perpendicular to the first direction (e.g. x, y, and z - directions are orthogonal)), the gate structure 3302/3304 in direct contact with the stacks of n-type 502/3304 and p-type nanostructures 502/3302 and in direct contact with the dielectric wall 112 (forksheet structure 404 has 112 separating adjacent n-type nanostructures 502/3304 and p-type nanostructures 502/3302, [0090], Fig. 7, Annotated Fig. 33);
a first gate interconnect (upper conductive layer 214 is a first gate interconnect, [0094], Fig. 35) over and in direct contact with the gate structure 3302/3304 (214 is over and in direct contact with 3302/3304, Fig. 35); and
a first gate via (contact vias 118 is a first gate via, [0107], Fig. 41) over and in direct contact with the first gate interconnect 214 (118 is over and in direct contact with 214, [0107], Fig. 42).
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Annotated Fig. 33 (Su) – Illustrates dielectric fin structure 112 separating adjacent nanostructure stacks, wherein the adjacent nanostructure stacks are n-type and p-type, respectively
Claim 2, Su discloses the semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7) of claim 1.
Su discloses wherein the first gate interconnect 214 is directly above the dielectric wall 112 (first gate interconnect 214 is directly above dielectric wall 112 within forksheet structure 404 and gate structure 3302/3304, [0095], Fig. 35).
Claim 3, Su discloses the semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7) of claim 2.
Su discloses wherein the first gate interconnect 214 is directly contacting a top surface of the dielectric wall 112 (boundary 3306 may be arranged over and directly contacting a top surface of one of the dielectric fin structures 112, hereinafter, dielectric boundary wall 112/3306, [0090], Figs. 33 and 35).
Claim 4, Su discloses the semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7) of claim 1.
Su discloses wherein a width of the first gate interconnect 214 is greater than a width of the dielectric wall 112 along the second direction (width of 214 is the entire width of 404 contained between high-k dielectric spacer structures 114 (width of 214 is less than d1 (e.g. < approximately 30 – 80 nm, [0035]) and greater than d5 (e.g. > approximately 20 – 40 nm), specifically, wherein the width of 214 is approximately 80% of d1, Fig. 4) is greater than a width of 112 (width of 112, w2 = 6 nm) in the x-direction (e.g. second direction), [0032], Figs. 13 and 35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Do (US 2022/0189944 A1).
Claim 5, Su discloses the semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7) of claim 1.
Su does not explicitly disclose a second gate interconnect over and in direct contact with the gate structure, wherein the second gate interconnect has a smaller dimension than that of the first gate interconnect.
However, Su/Do discloses a second gate interconnect over and in direct contact with the gate structure (Do, first gate interconnect 232 is over and in direct contact with gate structure G3, further, second gate interconnect CM15 is over and in direct contact with gate structure G3, [0098], Fig. 7; Su, Figs. 5-7), wherein the second gate interconnect has a smaller dimension than that of the first gate interconnect (Do, second gate interconnect CM15 has a smaller dimension than that of the first gate interconnect CM15 considering the height of the via as measured in the z-direction, [0098], Fig. 7; Su, Figs. 5-7). The combination to utilize varying dimension gate interconnects allows for arranging multiple transistor devices closer to one another, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices (Su, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to arrange the multiple transistor devices closer to one another, manipulating the configuration of the respective gate interconnects, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices.
Claim 6, Su/Do discloses the semiconductor device (Do, Fig. 7; Su, Figs. 5-7) of claim 5.
Su/Do discloses a second gate via (Do, second gate via VB13, [0096], Fig. 7; Su, Figs. 5-7) over and in direct contact with the second gate interconnect (Do, VB13 is over and in direct contact with second gate interconnect CM15 which is over and in direct contact with gate structure G3, [0098], Fig. 7; Su, Figs. 5-7); and
an interconnect structure (Do, interconnect structure CW12/DW1, [0092], Fig. 7; Su, Figs. 5-7) having first and second metal lines (Do, interconnect structure having first metal lines CW12 (M1) and second metal lines DW1 (M2), [0091], Fig. 7; Su, Figs. 5-7) over and in direct contact with the first and the second gate vias, respectively (Do, M1 and M2 are over and in direct contact with first second gate via VB13, respectively, [0091], Fig. 7; Su, contact vias 118 is a first gate via, [0107], Figs. 4-7). The combination to utilize varying dimension gate interconnects allows for arranging multiple transistor devices closer to one another, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices (Su, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to arrange the multiple transistor devices closer to one another, manipulating the configuration of the respective gate interconnects, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices.
Claim 21, Su discloses a semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7), comprising:
a forksheet structure (structure of semiconductor device is a forksheet as it has a metal gate electrode 106 over a stack of nanosheet channels 502/504 separated into two portions by a dielectric fin structure 112 which functions as a forksheet dielectric wall, hereinafter, forksheet structure 502/112 or 404, [0044], CMOS device 404 is a forksheet structure, Figs. 7 and 35) over a substrate (502/112 is over a substrate 202, [0044], Fig. 7) and extending lengthwise along a first direction (502/112 extends in the y-direction which is a first direction, [0044], Fig. 7), the forksheet structure 502/112 having a dielectric wall 112 separating a stack of n-type nanostructures from a stack of p-type nanostructures (forksheet structure 502/112 has 112 separating adjacent nanostructure stacks, wherein the channels 502 in contact with first gate electrode 3302 are a material associated with a first work function (e.g. p-type), hereinafter, p-type nanostructures 502/3302, and the channel 502 in contact with second gate electrode 3304 are a material associated with a second work function (e.g. n-type), hereinafter, n-type nanostructures 502/3304, [0090], Fig. 7, Annotated Fig. 33);
a gate structure (gate structure 3302/3304 may be composed of an electrode that further may be an individual or split gate, wherein for a split gate structure, a first gate electrode 3302 and a second gate electrode 3304 are in contact with channel 502, [0089], Figs. 7 and 33) over the forksheet structure 404 and extending lengthwise along a second direction different from the first direction (gate structure 3302/3304 extends in the x—direction which is a second direction perpendicular to the first direction (e.g. x, y, and z - directions are orthogonal)), the gate structure 3302/3304 engaging with the stacks of n-type 502/3304 and p-type nanostructures 502/3302 and in direct contact with the dielectric wall 112 (forksheet structure 404 further includes gate structure 3302/3304 with 112 engaging adjacent n-type nanostructures 502/3304 and p-type nanostructures 502/3302, [0090], Fig. 7, Annotated Fig. 33); and
a first gate interconnect (upper conductive layer 214 is a first gate interconnect, [0094], Fig. 35) over and interfacing with the gate structure 3302/3304 (214 is over and interfacing with 3302/3304, Fig. 35), wherein the first gate interconnect 214 is vertically aligned with the dielectric wall 112 (first gate interconnect 214 is directly above dielectric wall 112 within forksheet structure 404 and gate structure 3302/3304, [0095], Fig. 35) and has a greater width than the dielectric wall 112 (width of 214 is the entire width of 404 contained between high-k dielectric spacer structures 114 (width of 214 is less than d1 (e.g. < approximately 30 – 80 nm, [0035]) and greater than d5 (e.g. > approximately 20 – 40 nm), specifically, wherein the width of 214 is approximately 80% of d1, Fig. 4) is greater than a width of 112 (width of 112, w2 = 6 nm) in the x-direction (e.g. second direction), [0032], Figs. 13 and 35).
Su does not explicitly disclose wherein the first gate interconnect spans a smaller width along the second direction than the gate structure, and the first gate interconnect is embedded in an interlayer dielectric (ILD) layer over and landing on the gate structure.
However, Do discloses wherein the first gate interconnect (Su, first gate interconnect 214/3302, [0094], Figs. 35 and 36; Do, first gate interconnect 232, [0098], Figs. 4-7) spans a smaller width along the second direction (i.e. x-direction) than the gate structure (Do, first gate interconnect 232 spans a smaller width in the x-direction than the gate structure G3, [0098], Fig. 7; Su, Figs. 5-7), and the first gate interconnect (Su, first gate interconnect 214/3302, [0094], Figs. 35 and 36; Do, first gate interconnect 232, [0098], Figs. 4-7) is embedded in an interlayer dielectric (ILD) layer over and landing on the gate structure (Do, first gate interconnect 232 is embedded in a dielectric layer that is an interlayer dielectric layer 210 over and landing on the gate structure G3, [0022], Fig. 7; Su, Figs. 5-7). The combination to utilize a first interconnect that has a smaller horizontal width than the gate structure would allow for continued scalability of device geometries and higher device integration density of integrated circuit technologies (Do, [0001]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a first interconnect that has a smaller horizontal width than the gate structure would allow for continued scalability of device geometries and higher device integration density of integrated circuit technologies (Do, [0001]).
Claim 22, Su/Do discloses the semiconductor device (Do, Fig. 7; Su, Figs. 5-7) of claim 21.
Su discloses wherein a portion of the gate structure 3302/3304 vertically separates the first gate interconnect 214 from the dielectric wall 112 (Su, a portion of 3302/3304 vertically separates 214 from 112, [0094], Fig. 35; Do, Fig. 7).
Claim 23, Su/Do discloses the semiconductor device (Do, Fig. 7; Su, Figs. 5-7) of claim 21.
Su discloses wherein the first gate interconnect 214 lands on a top surface of the dielectric wall 112 to electrically connect portions of the gate structure 3302/3304 separated by the dielectric wall 112 (Su, CMOS device 404 further includes boundary 3306 may be arranged over and directly contacting a top surface of one of the dielectric fin structures 112, hereinafter, dielectric boundary wall 112/3306, [0095], Figs. 33 and 35; Do, Fig. 7).
Claim 24, Su/Do discloses the semiconductor device (Do, Fig. 7; Su, Figs. 5-7) of claim 21.
Su discloses a first gate via (Su, contact vias 118 is a first gate via, [0107], Fig. 41; Do, Fig. 7) over and interfacing with the first gate interconnect 214 (Su, 118 is over and in direct contact with 214, [0107], Fig. 42; Do, Fig. 7), wherein the first gate interconnect 214 has a greater width than the first gate via 118 (Su, width of 214 is greater than width of 118; width of 214 is approximately 80% of d1 (e.g. < approximately 30 – 80 nm, [0035]; Do, Fig. 7), Fig. 4, width of via 118 is approximately d6, (Su, e.g. approximately 10 – 50 nm, [0034]), Fig. 19; Do, Fig. 7).
Claim 25, Su/Do discloses the semiconductor device (Do, Fig. 7; Su, Figs. 5-7) of claim 21.
Su does not explicitly disclose a second gate interconnect over and interfacing with the gate structure, wherein the second gate interconnect is vertically offset from the dielectric wall.
However, Do discloses a second gate interconnect over and interfacing with the gate structure (Do, first gate interconnect 232 is over and in direct contact with gate structure G3, further, second gate interconnect CM15 is over and in direct contact with gate structure G3, [0098], Fig. 7; Su, dielectric wall 112, [0044], Figs. 5-7), wherein the second gate interconnect is vertically offset from the dielectric wall (Do, second gate interconnect CM15 is vertically offset from the dielectric wall I2 which separates active regions AR1/AR2, [0098], Fig. 7; Su, dielectric wall 112, [0044], Figs. 5-7). The combination to utilize a gate interconnect vertically offset from the dielectric wall ensures proper isolation of adjacent active regions wherein the interconnect over and interfacing with the gate structure allows for control of the interfacing gate structure (Do, [0067]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a gate interconnect vertically offset from the dielectric wall ensures proper isolation of adjacent active regions wherein the interconnect over and interfacing with the gate structure allows for control of the interfacing gate structure.
Claim 26, Su discloses the semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7) of claim 21.
Su does not explicitly disclose wherein both the first and the second gate interconnects are directly above the forksheet structure.
However, Do discloses wherein both the first and the second gate interconnects are directly above the forksheet structure (Su, first gate interconnect 214/3302 and second gate interconnect 214/3304 are directly above forksheet structure 502/112, [0094], Figs. 35 and 36; Do, first gate interconnect 232 and second gate interconnect CM15 are directly above the forksheet structure further including active pattens interfacing with dielectric wall I2, hereinafter, forksheet structure F1/I2/F2, [0098], Figs. 4-7). The combination to utilize the position of the first and second gate interconnects directly above the forksheet structure allows for arranging multiple transistor devices closer to one another, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices (Su, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the position of the first and second gate interconnects directly above the forksheet structure, manipulating the configuration of the structures mitigates leakage and cross-talk amongst the multiple transistor devices.
Claim 27, Su discloses a semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7), comprising:
a forksheet structure (structure of semiconductor device is a forksheet as it has a metal gate electrode 106 over a stack of nanosheet channels 502/504 separated into two portions by a dielectric fin structure 112 which functions as a forksheet dielectric wall, hereinafter, forksheet structure 502/112 or 404, [0044], CMOS device 404 is a forksheet structure, Figs. 7 and 35) over a substrate (502/112 is over a substrate 202, [0044], Fig. 7) and extending lengthwise along a first direction (502/112 extends in the y-direction which is a first direction, [0044], Fig. 7), the forksheet structure 502/112 having a dielectric wall 112 separating a stack of n-type nanostructures from a stack of p-type nanostructures (forksheet structure 502/112 has 112 separating adjacent nanostructure stacks, wherein the channels 502 in contact with first gate electrode 3302 are a material associated with a first work function (e.g. p-type), hereinafter, p-type nanostructures 502/3302, and the channel 502 in contact with second gate electrode 3304 are a material associated with a second work function (e.g. n-type), hereinafter, n-type nanostructures 502/3304, [0090], Fig. 7, Annotated Fig. 33);
a gate structure (gate structure 3302/3304 may be composed of an electrode that further may be an individual or split gate, wherein for a split gate structure, a first gate electrode 3302 and a second gate electrode 3304 are in contact with channel 502, [0089], Figs. 7 and 33) over the forksheet structure 404 and extending lengthwise along a second direction different from the first direction (gate structure 3302/3304 extends in the x—direction which is a second direction perpendicular to the first direction (e.g. x, y, and z - directions are orthogonal)), the gate structure 3302/3304 has a first gate portion 3304 engaging with the stack of n-type nanostructures 502/3304 and a second gate portion 3302 engaging with the stack of p-type nanostructures 502/3302 dielectric wall 112, wherein the first and the second gate portions 3302/3304 are physically separated from each other by the dielectric wall 112/3306 (boundary 3306 may be arranged over and directly contacting a top surface of one of the dielectric fin structures 112, hereinafter, dielectric boundary wall 112/3306, [0090], Figs. 33 and 35);
a first gate interconnect (upper conductive layer 214 is a first gate interconnect where it is over and interfacing with the first portion of gate structure 3302, hereinafter, 214/3302, [0094], Fig. 35) over and interfacing with the first portion of gate structure 3302 (214/3302 is over and in direct contact with 3302, Fig. 35); and
a second gate interconnect (upper conductive layer 214 is a first gate interconnect where it is over and interfacing with the first portion of gate structure 3304, hereinafter, 214/3304, [0094], Fig. 35) over and interfacing with the second portion of gate structure 3302 (214/3304 is over and in direct contact with 3304, Fig. 35).
Su does not explicitly disclose wherein the first and the second gate interconnects are of different dimensions.
However, Do discloses wherein the first and the second gate interconnects (Do, first gate interconnect 232 is over and in direct contact with gate structure G3, further, second gate interconnect CM15 is over and in direct contact with gate structure G3, [0098], Fig. 7; Su, Figs. 5-7) are of different dimensions (Do, second gate interconnect CM15 and the first gate interconnect 232 are of different dimensions, [0098], Fig. 7; Su, Figs. 5-7). The combination to utilize varying dimension gate interconnects allows for arranging multiple transistor devices closer to one another, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices (Su, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to arrange the multiple transistor devices closer to one another, manipulating the configuration of the respective gate interconnects, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices.
Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Do as applied to claim 27 above, and further in view of Lilak (US 2021/0296315 A1).
Claim 28, Su/Do discloses the semiconductor device (Su, integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7; Do, Fig. 7) of claim 27.
Su/Do discloses a second forksheet structure (Su, first forksheet structure is the dielectric wall 112 centered between adjacent n-type and p-type nanostructures 502, hereinafter, first forksheet structure, 502/112, [0044], second forksheet structure is the dielectric wall 112 in contact with the high-k dielectric spacer 114 on the left hand side of the first forksheet structure 502/112, whereinafter, second forksheet structure 502/112/114 [0095], Figs. 7 and 35; Do, Fig. 7) over the substrate (Su, 502/112/114 is over a substrate 202, [0044], Fig. 7; Do, Fig. 7) and extending lengthwise along the first direction (Su, 502/112 extends in the y-direction which is a first direction, [0044], Fig. 7; Do, Fig. 7), the second forksheet structure having a second dielectric wall separating another stack of n-type nanostructures from another stack of p-type nanostructures (Su, second forksheet structure 502/112/114 has 112 separating adjacent p-type nanostructures 502/3302 and n-type nanostructures 502/3304,[0090], Fig. 7 and Annotated Fig. 22, a plurality of devices are formed adjacent to each other, Fig. 1; Do, Fig. 7).
Su/Do does not explicitly disclose wherein the gate structure further includes a third portion physically separated from the second portion by the second dielectric wall, wherein the second gate interconnect is disposed above the second dielectric wall and electrically connects the second portion to the third portion of the gate structure.
However, Lilak wherein the gate structure further includes a third portion (Lilak, gate structure 813 is composed for a first, second, and third gate portion within the first, second, and third transistors 820A/820B/820C, hereinafter, first gate electrode portion 813A, second gate electrode portion 813B, and third gate electrode portion 813C, further including first and second gate interconnect, [0123], Figs. 8A/8B and 15A/15B; Su, Fig. 7; Do, first gate interconnect 232 is over and in direct contact with gate structure G3, further, second gate interconnect CM15 is over and in direct contact with gate structure G3, [0098], Fig. 7) physically separated from the second portion by the second dielectric wall (Lilak, third gate electrode portion 813C is physically separated from second gate electrode portion 813B by backbone 810, hereinafter, second dielectric wall 810BC, further, first gate electrode portion 813A is physically separated from second gate electrode portion 813B by backbone 810, hereinafter, first dielectric wall 810AB, further including first and second gate interconnect, [0123], Figs. 8A/8B and 15A/15B; Su, Fig. 7; Do, first gate interconnect 232 is over and in direct contact with gate structure G3, further, second gate interconnect CM15 is over and in direct contact with gate structure G3, [0098],, [0098], Fig. 7),
wherein the second gate interconnect is disposed above the second dielectric wall and electrically connects the second portion to the third portion of the gate structure (Lilak, third gate electrode portion 813C is physically separated from second gate electrode portion 813B by backbone 810, hereinafter, second dielectric wall 810BC, further, first gate electrode portion 813A is physically separated from second gate electrode portion 813B by backbone 810, hereinafter, first dielectric wall 810AB, further including first and second gate interconnect, [0123], Figs. 8A-8B and 15A-15B; Su, Fig. 7; Do, first gate interconnect 232 is over and in direct contact with gate structure G3, further, second gate interconnect CM15 is over and in direct contact with gate structure G3, [0098], Fig. 7). The combination to utilize multiple adjacent gate electrode portions electrically connected to semiconductor structures separated by the dielectric wall to improve device density and allows for arranging multiple transistor devices closer to one another, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices (Su, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a local interconnect disposed over the dielectric wall and electrically connected to multiple adjacent gate electrode portions electrically connected to semiconductor structures separated by the dielectric wall, manipulating the configuration of the structures mitigates leakage and cross-talk amongst the multiple transistor devices.
Claim 29, Su/Do/Lilak discloses the semiconductor device (Su, integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7; Do, Fig. 7; Lilak, first and second ) of claim 28.
Su/Do/Lilak discloses wherein the second gate interconnect has a greater dimension than the first gate interconnect (Do, second gate interconnect CM15 has a smaller dimension than that of the first gate interconnect CM15 considering the height of the via as measured in the z-direction, [0098], Fig. 7; Su, Figs. 5-7; Lilak, Figs. 8A/8B and 15A/15B). The combination to utilize varying dimension gate interconnects allows for arranging multiple transistor devices closer to one another, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices (Su, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to arrange the multiple transistor devices closer to one another, manipulating the configuration of the respective gate interconnects, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices.
Claim 30, Su/Do discloses the semiconductor device (Su, integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7; Do, Fig. 7) of claim 27.
Su/Do discloses a first gate via over and interfacing with the first gate interconnect (Su, first gate via 118 is over and in direct contact with first gate interconnect 214, [0107], Fig. 42; Do, first gate interconnect 232); and
a second gate via over and interfacing with the second gate interconnect (Do, second gate via VB13 is over and interfacing with the second gate interconnect CM15, which is over and in direct contact with gate structure G3, [0098] and [0107], Figs. 7 and 42; Su, Figs. 5-7),
wherein the first gate via or the second gate via has a smaller width dimension than that of the first gate interconnect or the second gate interconnect along the second direction (Do, second gate via VB13 has a smaller width dimension than that of the second gate interconnect CM15, which is over and in direct contact with gate structure G3, [0098] and [0107], Figs. 7 and 42; Su, Figs. 5-7). The combination to utilize varying dimension gate interconnects allows for arranging multiple transistor devices closer to one another, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices (Su, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to arrange the multiple transistor devices closer to one another, manipulating the configuration of the respective gate interconnects, the isolation structures must be effective enough to mitigate leakage and cross-talk amongst the multiple transistor devices.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 1 above, and further in view of Wang (US 2021/0118801 A1).
Claim 7, Su discloses the semiconductor device (integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7) of claim 1.
Su discloses a source/drain (S/D) feature (source/drain regions 102 are source/drain (S/D) features, [0042], Fig. 6) adjacent to the stack of n-type 502/3304 or p-type nanostructures 502/3302, Figs. 5-7 and 42-44); and
an S/D contact (metal wires 218 is an S/D contact, [0027], Fig. 6) over and in direct contact with the S/D feature 102 and the dielectric wall 112 (218 is over and in direct contact with 102 as well as 112, [0027], Figs. 5-7).
Su does not explicitly disclose wherein a top surface of the first gate interconnect is above a top surface of the S/D contact.
However, Wang discloses wherein a top surface of the first gate interconnect is above a top surface of the S/D contact (Wang, top surface of first gate interconnect 235 is above a top surface of S/D contact 224, [0032], Fig. 8; Su, first gate interconnect 214, [0094], Fig. 35, S/D contact 218, [0027], Figs. 5-7). The combination to utilize a gate interconnect above a S/D contact would allow for the implementation of common rail lines in subsequent local interconnections and may aid in even distribution of current evenly, avoiding any current crowding effects, resulting in reduction in resistance between vertically adjacent interconnect layers/contacts (Wang, [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a gate interconnect above a S/D contact would allow for the implementation of common rail lines in subsequent local interconnections and may aid in even distribution of current evenly, avoiding any current crowding effects, resulting in reduction in resistance between vertically adjacent interconnect layers/contacts.
Claim 8, Su/Wang discloses the semiconductor device (Su, integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7; Wang, Fig. 8) of claim 7.
Su/Wang discloses wherein the first gate interconnect (Su, first gate interconnect 214 is composed of tungsten, [0094], Fig. 35; Wang, first gate interconnect 235 is composed of tungsten, [0032], Fig. 8) and the S/D contact (Su, S/D contact 218 is composed of tungsten, [0102], Fig. 38; Wang, S/D contact 224 is composed of tungsten, [0027], Fig. 8) are of the same material composition (Su, both 214 and 218 are composed of the same material (e.g. tungsten), [0094] and [0102], Figs. 35 and 38; Wang, both 224 and 235 are composed of the same material (e.g. tungsten), [0027] and [0032], Fig. 8).
Claim 9, Su/Wang discloses the semiconductor device (Su, integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7; Wang, Fig. 8) of claim 8.
Su/Wang discloses wherein the first gate interconnect (Su, first gate interconnect 214 is composed of tungsten, [0094], Fig. 35; Wang, first gate interconnect 235 is composed of tungsten, [0032], Fig. 8) and the S/D contact (Su, S/D contact 218 is composed of tungsten, [0102], Fig. 38; Wang, S/D contact 224 is composed of tungsten, [0027], Fig. 8) includes tungsten (Su, both 214 and 218 are composed of the same material (e.g. tungsten), [0094] and [0102], Figs. 35 and 38; Wang, both 224 and 235 are composed of the same material (e.g. tungsten), [0027] and [0032], Fig. 8).
Claim 10, Su/Wang discloses the semiconductor device (Su, integrated chip comprising nanostructure field effect transistors (NSFETs) divided by dielectric fin structures is a semiconductor device, [0004] – [0006], Figs. 1 and 5-7; Wang, Fig. 8) of claim 9.
Su/Wang discloses an S/D via (Su, via 118 directly over and in direct contact with S/D contact 218 is a S/D via, hereinafter, S/D via 118/218, [0107], Fig. 42; Wang, Fig. 8) over and in direct contact with the S/D contact (Su, S/D via 118/218 is directly over and in direct contact with S/D contact 218, [0107], Fig. 42; Wang, Fig. 8),
wherein the first gate via and the S/D via include tungsten (Su, contact vias 118, further including S/D via 118/218, are composed of tungsten, [0107], Fig. 42; Wang, S/D contact 224 and common rail line 236 are composed of tungsten, [0027] and [0032], Fig. 8).
Conclusion
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812