DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 3/6/2025, responding to the Office action mailed on 11/24/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-18 and 21-22 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7-9, 11-12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (DE 112011105995 B4) in view of Wong et al. (TW 202103323 A).
Re Claim 1 Rachmady teaches a method (FIG. 3C), comprising:
forming a structure (FIG. 3C) having a dummy gate stack (326, page 15 par 1) over a multi-layer stack (ML) (308 and 310 as shown in FIG. 3A, page 15 par 2) disposed on a semiconductor substrate (301, page 15 par 2), the ML including alternating channel layers (308, page 18 par 4) and non-channel layers (310, page 18 par 4);
recessing the ML (308 and 310) in a first source/drain (S/D) region (334 on front side of 326, page 14 par 3) and a second S/D region (334 on back side of 326) on two sides of the dummy gate stack (326, FIG 3D and 3E);
removing the non-channel layers (310) to form first openings (342) between the channel layers (343, 308 becomes 343, page 16 par 4, FIG. 3I)
wherein the first openings (342) span from the first S/D region (338) to the second S/D region (339);
depositing a dielectric material (346, page 19 par 3) in the first openings (FIG .3J);
forming epitaxial S/D features (338 and 339, page 15 par 2) in the first (338) and the second (339) S/D regions (FIG. 3J); and
removing the dummy gate stack (326, page 15 par 1) to form a gate trench (FIG. 3F and 3G);
removing the dielectric material (346) from the gate trench to form second openings between the channel layers (343, 308 becomes 343, page 16 par 4, FIG. 3J and 3K); and
forming a metal gate stack (352, page 20 par 1) in the gate trench and the second openings (FIG. 3L).
Rachmady does not teach recessing the dielectric material to form undercuts; and
forming inner spacers in the undercuts,
Wong teaches recessing the dielectric material (216, page 10 par 3) to form undercuts (218, FIG. 8); and
forming inner spacers (220) in the undercuts (218, FIG. 9);
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Wong into the structure of Rachmady since Wong is about transistor semiconductor devices.
The ordinary artisan would have been motivated to modify Wong in combination with Rachmady in the above manner for the motivation of recessing the shaping the dielectric material and adding spacers to help optimize the space in the channel regions since space is critical as semiconductor devices continue to be manufacturing as smaller than previously. Page 2 par 2 states, “The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation.”
Re Claim 3 Rachmady in view of Wong teaches the method of claim 1, prior to the removing the dummy gate stack (Wong, 210, page 4 par 4), further comprising forming an interlayer dielectric (ILD) layer (242, page 14 par 5) over the epitaxial S/D features (230, page 8 par 3), wherein the depositing the dielectric material (242) includes performing an atomic layer deposition (ALD) process (page 14 par 5, FIG. 17A).
Re Claim 7 Rachmady in view of Wong teaches the method of claim 1, wherein the inner spacers (Wong, 220) include a different composition from the dielectric material (216, use silicon oxide for 216 and a low-k dielectric material for 220. Wong page 10 par 1 states, “For example, the dielectric layer 216 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, or a combination thereof.” Wong page 11 par 1 states, “For example, the dielectric layer 220 may include silicon oxide, a low-k dielectric material, tetraethoxysilane oxide, doped silicon oxide (such as borophosphosilicate glass, fluorine-doped silicon Salt glass, phosphosilicate glass, borosilicate glass, or the like), other suitable dielectric materials, or a combination of the above.”).
Re Claim 8 Rachmady in view of Wong teaches the method of claim 1, wherein the dielectric material (Wong, 220) includes at least one of silicon oxide, silicon oxynitride (SiON), aluminum oxide (A1203), silicon nitride, and a combination thereof (Page 11 par 1 states, “For example, the dielectric layer 220 may include silicon oxide…).
Re Claim 9 Rachmady in view of Wong teaches the method of claim 1, wherein the channel layers (Ju, 308) include elemental silicon, and wherein the non-channel layers include silicon germanium (SiGe) (Ju page 6 par 3 states, “In an embodiment, the epitaxial layers of the first composition (e.g., used to form layers 310) are SiGe and the epitaxial layers of the second composition (e.g., used to form layers 308) are silicon (Si).”
Re Claim 11 Rachmady in view of Wong teaches the method of claim 1, wherein after removing the dielectric material (Wong, 216), a first remaining portion of the dielectric material (216) extends between a first inner spacer (220) of the inner spacers and a gate dielectric layer (262, page 16 par 1) of the metal gate stack (260) in one of the second openings between two adjacent channel layers (204a, page 5 par 3, FIG. 20A).
Re Claim 12 Rachmady in view of Wong teaches the method of claim 11, wherein a top surface of the first remaining portion of the dielectric material (Wong, top part of 216) and a top surface of the gate dielectric layer (262) of the metal gate stack (260) are coplanar and are in direct contact with a bottom surface of a top channel layer (top 204a) of the two adjacent channel layers (204A second from top, FIG. 20A).
Re Claim 15 Rachmady teaches a method (FIG. 3C), comprising:
receiving a structure (FIG. 3C) having a dummy gate stack (326, page 15 par 1) over a multi-layer stack (ML) (308 and 310 as shown in FIG. 3A, page 15 par 2) disposed on a semiconductor substrate (301, page 15 par 2), the ML including alternating channel layers (308, page 18 par 4) and non-channel layers (310, page 18 par 4) and two source/drain (S/D) regions (334 on each side of 326, page 14 par 3) on two sides of the channel layers and non- channel layers (FIG. 3C and 3D);
replacing the non-channel layers (310) with a dielectric material (346, page 19 par 3) extending continuously between the two S/D regions (338 and 339 {region occupied by 334 in FIG. 3D}, FIG. 3J);
forming epitaxial S/D features (page 15 par 2) in the two S/D regions (338 and 339, FIG. 3J); and
replacing the dummy gate stack (326) and a portion of the dielectric material (346) with a metal gate stack (352, page 20 par 1, FIG. 3L).
Rachmady does not teach recessing the dielectric material from two sides of the dielectric material to form undercuts;
forming inner spacers in the undercuts;
Wong teaches recessing the dielectric material (216, page 10 par 3) from two sides of the dielectric material to form undercuts (218, FIG. 8);
forming inner spacers (220) in the undercuts (218, FIG. 9);
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Wong into the structure of Rachmady since Wong is about transistor semiconductor devices.
The ordinary artisan would have been motivated to modify Wong in combination with Rachmady in the above manner for the motivation of recessing the shaping the dielectric material and adding spacers to help optimize the space in the channel regions since space is critical as semiconductor devices continue to be manufacturing as smaller than previously. Page 2 par 2 states, “The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation.”
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (DE 112011105995 B4) in view of Wong et al. (TW 202103323 A) as applied to claim 1 above, and further in view of Choi et al. (US 9941174 B2).
Re Claim 2 Rachmady in view of Wong teaches the method of claim 1, wherein the dielectric material (Rachmady, 346) extends continuously from the first S/D region (338) to the second S/D region (339, FIG. 3J), but does not teach depositing the dielectric material further includes depositing the dielectric material in the first S/D region and in the second S/D regions
Choi teaches depositing the dielectric material (40, col 8 line 36) further includes depositing the dielectric material in the first S/D region (region above 35 on left in FIG. 17A) and in the second S/D regions (region above 35 on right in FIG. 17A, FIG. 19A shows a first and second S/D region 55P, col 12 line 30 which occupies the same space as 40 in FIG. 17A).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Choi into the structure of Rachmady in view of Wong since Choi is about transistor semiconductor devices.
The ordinary artisan would have been motivated to modify Choi in combination with Rachmady in view Wong in the above manner for the motivation of optimally integrating a dielectric material in the S/D regions to ensure the sidewalls are optimally formed to help the device function at a peak level. Col 1 line 27 states, “Uneven sidewalls are generally not good for the performance of a metal oxide semiconductor (MOS) transistor.”
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (DE 112011105995 B4) in view of Wong et al. (TW 202103323 A) as applied to claim 1 above, and further in view of Iwai et al. (CN 114730763 A).
Re Claim 4 Rachmady in view of Wong teaches the method of claim 1, wherein the dielectric material (Rachmady, 346) is silicon oxide (page 19 last par).
Rachmady in view of Wong does not teach the recessing the dielectric material includes etching the dielectric material with hydrofluoric acid (HF).
Iwai teaches the recessing the dielectric material includes etching the dielectric material with hydrofluoric acid (HF) (page 60 par 0 states, “…using an isotropic etching process using hydrofluoric acid to etch the dielectric filling material…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Iwai into the structure of Rachmady in view of Wong since Lin is about transistor semiconductor devices.
The ordinary artisan would have been motivated to modify Iwai in combination with Rachmady in view of Wong in the above manner for the motivation of using HF as an etchant material since it is known to have a high etch rate for silicon oxide. NPL article Etching with Hydrofluoric Acid states, “Hydrofluoric acid is the only etchant which attacks amorphous SiO2, quartz, or glasses at significant high etch rate.
Claims 6 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (DE 112011105995 B4) in view of Wong et al. (TW 202103323 A) as applied to claim 1 above, and further in view of Yeong et al. (US 20210202758 A1).
Re Claim 6 Rachmady in view of Wong teaches the method of claim 1, but does not teach forming the metal gate stack includes:
forming a high-k dielectric layer in the gate trench and the second openings; and
forming a metal gate electrode over the high-k dielectric layer to fill the gate trench and the second openings, the metal gate electrode wrapping around each of the channel layers.
Yeong teaches forming the metal gate (123, [0055]) stack includes:
forming a high-k dielectric layer (120) [0054] in the gate trench and the second openings (FIG. 16); and
forming a metal gate electrode (122) [0055] over the high-k dielectric layer (120) to fill the gate trench and the second openings, the metal gate electrode wrapping around each of the channel layers (FIG. 16).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yeong into the structure of Rachmady in view of Wong since Yeong is about transistor semiconductor devices.
The ordinary artisan would have been motivated to modify Yeong in combination with Rachmady in view of Wong in the above manner for the motivation of using a high-k dielectric material to fill the gate trench and second openings to optimize the space in the semiconductor as the industry continues to shrink the actual chip size. [0003] states, “The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.”
Re Claim 16 Rachmady in view of Wong teaches the method of claim 15, but does not teach prior to the replacing the dummy gate stack and the portion of the dielectric material, further comprising forming an interlayer dielectric (ILD) layer over the epitaxial S/D features.
Yeong teaches prior to the replacing the dummy gate stack (102) and the portion of the dielectric material (131), further comprising forming an interlayer dielectric (ILD) layer over the epitaxial S/D features (112, FIG. 13, 114 is added in [0044], 102 is removed in [0046], and parts of 131 are removed in [0053]).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yeong into the structure of Rachmady in view of Wong since Yeong is about transistor semiconductor devices.
The ordinary artisan would have been motivated to modify Yeong in combination with Rachmady in view of Wong in the above manner for the motivation of optimizing the available space in the chip by forming an ILD layer over the S/D to allow the chip to function at a peak capacity while the industry continues to demand smaller devices. [0003] states, “The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.”
Re Claim 17 Rachmady in view of Wong and Yeong teaches the method of claim 15, wherein replacing the dummy gate stack (Yeong, 102) and the portion of the dielectric material (131) includes:
removing the dummy gate stack (102) [0046] to form a gate trench (103, FIG. 14);
removing the portion of the dielectric material (131) to form openings between the channel layers (54, [0012], FIG. 15); and
forming the metal gate stack (123) [0055] in the gate trench and the openings (FIG. 16).
Re Claim 18 Rachmady in view of Wong and Yeong teaches the method of claim 17, wherein the removing the portion of the dielectric material (Yeong, 131) includes applying an etching process [0053] with an etchant selectively removing the dielectric material (131) without significantly etching the channel layers (54, FIG. 15).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (DE 112011105995 B4) and Wong et al. (TW 202103323 A) as applied to claim 1 above, and further in view of (JP 2022533516 A), ‘JP’ hereafter
Re Claim 10 Ju in view of Rachmady and Wong and Yeong teaches the method of claim 1, but does not teach the removing the dielectric material includes applying an etching process with an etchant having an etching selectivity of the dielectric material to the channel layers greater than 10.
JP page 6 par 1 teaches, “Thus, in still other exemplary embodiments, the etch selectivity of the insulator fill material to the etch stop material is about 10:1, or about 20:1, or about 30:1, or about 40:1 or greater, and so on. , in the range of about 5:1 to about 50:1.” Use the dielectric material as the insulator fill material and the channel layers as the etch stop material.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by JP into the structure of Rachmady in view of Wong and Yeong since JP is about stacked semiconductor layers. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the ideal etchant selectivity.
The ordinary artisan would have been motivated to modify JP in combination with Rachmady in view of Wong and Yeong in the above manner for the motivation of finding optimal etchant selectivity.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (DE 112011105995 B4) and Wong et al. (TW 202103323 A) as applied to claim 1 above, and further in view of Zhang et al. (US 20200105929 A1).
Re Claim 13 Ju in view of Rachmady and Wong teaches the method of claim 11, wherein a second remaining portion of the dielectric material (Wong, bottom of 216) extends laterally between the first inner spacer (220) of the inner spacers and the gate dielectric layer (262) of the metal gate stack (260, FIG. 20A).
Rachmady in view of Wong does not teach the first and second remaining portions of the dielectric material are separated by the first inner spacer and the gate dielectric layer of the metal gate stack.
Zhang teaches the first and second remaining portions of the dielectric material (52) [0035] are separated by the first inner spacer (54) and the gate dielectric layer (30) [0004] of the metal gate stack (30 and 32, FIG. 2K).
Modified FIG. 2K is shown below with parts identified
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Zhang into the structure of Rachmady in view of Wong since Zhang is about transistor semiconductor devices.
The ordinary artisan would have been motivated to modify Zhang in combination with Rachmady in view of Wong in the above manner for the motivation of integrating spacers to help optimize the current in the device and ensure electrical integrity of the source/drain region and the channel layers to help the device function optimally. [0003] states, “Spacers are employed for electrically isolating the gates from the source/drain regions of nanosheet transistors.”
Re Claim 14 Rachmady in view of Wong and Zhang teaches the method of claim 13, wherein the first remaining portion of the dielectric material (Zhang, 52 on top surface of 54) extends to a first channel layer (top Si Channel) of the two adjacent channel layers, and wherein the second remaining portion of the dielectric material (52 on bottom surface of 54) extends to a second channel layer (Si Channel 2nd from top) of the two adjacent channel layers (See modified FIG. 2K above).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art fails to teach the claim 21 limitation:
…forming a structure comprising:
a stack of alternating first semiconductor layers and second semiconductor layers,
wherein the first semiconductor layers comprise a first semiconductor material and the second semiconductor layers comprise a second semiconductor material, wherein a pair of neighboring first semiconductor layer and second semiconductor comprise an intermix region having both the first semiconductor material and the second semiconductor material…
Claim 22 depends on claim 21 and is allowable for implicitly including the allowable subject matter above.
Pertinent Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Rachmady (DE 112011105995 B4) teaches a stack of alternating first semiconductor layers and second semiconductor layers, a dummy gate structure over the stack, forming source/drain trenches in the stack and on two sides of the dummy gate structure, removing the second semiconductor layers to form openings, depositing a dielectric layer in the openings, forming source/drain features in the source/drain trenches, removing the dummy gate structure to form a gate trench, and forming a metal gate structure in the gate trench and in the openings.
b. Choi (US 9941174 B2) teaches forming a dummy gate stack, depositing a dielectric layer in the source/drain trenches, removing a portion of the dielectric layer in the source/drain trenches, and forming source/drain features in the source/drain trenches.
c. Wong (TW 202103323 A) teaches a stack of alternating first semiconductor layers and second semiconductor layers, a dummy gate structure over the stack, forming source/drain trenches on two sides of the dummy gate structure, removing (part) of the second semiconductor layers, and depositing a dielectric layer in the source/drain trenches and in the openings.
d. Yeong (US 20210202758 A1) teaches a stack of alternating first semiconductor layers and second semiconductor layers, removing the second semiconductor layers, depositing a dielectric layer in the openings, and removing a portion of the dielectric material.
e. Zhang (US 20200105929 A1) teaches a stack of alternating first and second semiconductor layers, forming a dummy gate stacks and source/drain trenches, removing the second semiconductor layers, forming source/drain features, removing the gate structure, and forming metal gates.
Response to Arguments
Applicant’s arguments with respect to claims 1-4 and 6-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 4/6/26