DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 -4, 6-9,15,19, 22, 23 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by McLellan (US-20180102338-A1; McLellan).
Regarding claim 1, McLellan discloses a module comprising: a component carrier (Fig. 3, 15; ¶24) with a stack comprising at least one electrically conductive layer structure (Fig. 3, 175/178/180/182/195; ¶27) and at least one electrically insulating layer structure (Fig. 3, 105/110/190; ¶27) , the stack having at least one bridging component (Fig. 3, 55; ¶24) embedded therein , wherein the bridging component has a first main surface (top or bottom) and a second main surface (top or bottom) opposite the first main surface, wherein the bridging component comprises a matrix of dielectric (Fig. 3, 230; ¶29) or semiconductor material, the matrix being delimited by the first main surface and the second main surface and an inner electrically conductive redistribution structure (Fig. 3, 205/210/250/255/260/215; ¶29) embedded in the matrix and between the first main surface and the second main surface, the inner electrically conductive redistribution structure defining first contacting areas (Fig. 3, 210 or 205; ¶24) provided on the first main surface and second contacting areas (Fig. 3, 210 or 205; ¶24) provided on the second main surface, the first contacting areas being connected to the second contacting areas through an electrically conductive path passing entirely through the matrix (clear from figure)provided in the bridging component, wherein at least one of the first contacting area (Fig. 3, 210 or 205; ¶24) or at least one second contacting area is directly or indirectly connected to at least two electronic components. (Fig. 3, 25/30; ¶22)
Regarding claim 2, McLellan discloses the module according to claim 1, wherein the component carrier (Fig. 3, 15; ¶24) comprises two component carrier main surfaces (Top and bottom), and wherein the first and second main surfaces of the bridging component (Fig. 3, 55; ¶24) are directly connected to a respective one of the component carrier main surfaces. (top of trench)
Regarding claim 3, McLellan discloses the module according to claim 1, wherein solder balls (Fig. 3, 45 or 225; ¶22/28) are provided on at least one of the component carrier (Fig. 3, 15; ¶24) main surfaces, the solder balls being directly or indirectly connected to at least one first contacting area (Fig. 3, 210 or 205; ¶24) or at least one second contacting area (Fig. 3, 210 or 205; ¶24) of the respective bridging component (Fig. 3, 55; ¶24) main surface. (first or second main surface)
Regarding claim 4, McLellan discloses the module according to claim 1, wherein a density per volume unit or area unit of a contacting area (Fig. 3, 210 or 205; ¶24) of the first main surface (top) of the bridging component (Fig. 3, 55; ¶24) is different (clear from drawing) from a density per volume unit or area unit of a contacting area (Fig. 3, 210 or 205; ¶24) of the second main surface (bottom) of the bridging component.
Regarding claim 6, McLellan discloses the module according to claim 1, wherein the component carrier (Fig. 3, 15; ¶24) comprises at least two bridging components (Fig. 3, 50/55; ¶24) embedded in the stack. (Fig. 3, 105/110/190; ¶27)
Regarding claim 7, McLellan discloses the module according to claim 6, wherein at least one of the at least two electronic components (Fig. 1/3, 25; ¶22) in the component carrier is connected to the at least two bridging components. (Fig. 1/3, 50/55; ¶24)
Regarding claim 8, McLellan discloses the module according to claim 7, wherein each of the at least two bridging components (Fig. 3, 50/55; ¶24) comprises a first main surface, wherein the at least one of the at least two electronic components (Fig. 3, 25/30; ¶22) is connected (electrically) to each first main surface of the at least two bridging components facing the same component carrier main surface.
Regarding claim 9, McLellan discloses the module according to claim 1, wherein the bridging component (Fig. 3, 55; ¶24) is connected to a third electronic component. (I/O; ¶28)
Regarding claim 11, McLellan discloses the module according to claim 1, wherein at least one of the at least two electronic components (Fig. 3, 25; ¶22) is additionally connected to a further redistribution structure (Fig. 3, 195 to 175; ¶27) directly provided in the component carrier. (Fig. 3, 15; ¶24)
Regarding claim 12, McLellan discloses the module according to claim 1, wherein at least one of the at least two electronic components (Fig. 3, 30; ¶22) is exclusively connected to the at least one bridging component. (Fig. 3, 55; ¶24)
Regarding claim 13, McLellan discloses the module according to claim 1, wherein at least one of the at least two electronic components (Fig. 3, 25; ¶22) is electrically connected to the bridging component (Fig. 3, 55; ¶24) and electrically connected to another element Fig. 3, 195 to 175; ¶27) of the component carrier (Fig. 3, 15; ¶24) or the module.
Regarding claim 15, McLellan discloses the module according to claim 1, wherein the bridging component (Fig. 3, 55; ¶24) comprises connection elements (Fig. 3, 250; ¶29) embedded in the matrix (Fig. 3, 230; ¶29), the connection elements forming the electrically conductive redistribution structure together with the first and second contacting areas (Fig. 3, 205/210; ¶24), wherein a mean distance between the first contacting areas is different from a mean distance between the second contacting areas.
The distance between 210 varies which effects the mean distance. The distance between 205 is consistently smaller than at least one of the spaces between 210. Therefore the mean distance is different.
Regarding claim 19, McLellan discloses the module according to claim 1, further comprising: a mold encapsulating (¶34) at least one of the at least two electronic components. (Fig. 3, 25 or 30; ¶22/34)
Regarding claim 22, McLellan discloses the module according to claim 1, wherein at least one of the at least two electronic components (Fig. 3, 25 or 30; ¶22/34) comprises at least one of a group consisting of a processor, a memory, a passive component, and a power chip.(¶23)
Regarding claim 23, McLellan discloses the module according to claim 1, wherein the component carrier (Fig. 3, 15; ¶24)comprises at least one of the following features: at least one component (Fig. 3, 50; ¶24) being surface mounted on and/or embedded in the component carrier, wherein the at least one component is selected from a group consisting of an electronic component, an electrically non-conductive and/or electrically conductive inlay, a heat transfer unit, a light guiding element, an optical element, a bridge, an energy harvesting unit, an active electronic component, a passive electronic component, an electronic chip, an RF chip, a storage device, a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, an actuator, a microelectromechanical system, a microprocessor, a capacitor, a resistor, an inductance, an accumulator, a switch, a camera, an antenna, a magnetic element, a further component carrier, and a logic chip; wherein at least one of the electrically conductive layer structures (Fig. 3, 175/178/180/182/195; ¶26) of the component carrier comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten; wherein the electrically insulating layer structure (Fig. 3, 105/110/190; ¶26) comprises at least one of the group consisting of resin, epoxy resin or bismaleimide-triazine resin, FR-4, FR-5, cyanate ester resin, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based build-up film, polytetrafluoroethylene, a ceramic, and a metal oxide; wherein the component carrier (Fig. 1, 15;¶25) is shaped as a plate; wherein the component carrier (¶25) is configured as one of the group consisting of a printed circuit board, a substrate, and an interposer; wherein the component carrier is configured as a laminate-type component carrier.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 10, 21, 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over McLellan (US-20180102338-A1; McLellan) in view of Mallik et al. (US 20200395313 A1; Mallik).
Regarding claim 5, McLellan discloses the module according to claim 4, but is silent on wherein a density per volume unit or area unit of the contacting area of the first main surface, which is directly connected to at least one of the at least two electronic components, is higher than a density of the contacting area provided on the opposed second main surface.(bottom)
Mallik discloses a module wherein a density per volume unit or area unit of the contacting area (Fig. 6, pad distribution 684 and associating bridge wiring; ¶69-70) of the first main surface (Fig. 6, top surface 640; ¶69-70), which is directly connected to at least one of the at least two electronic components (Fig. 6, 620; ¶69-70), is higher than a density of the contacting area (Fig. 6, bottom surface distribution of pads; ¶69-70) provided on the opposed second main surface.(bottom)
Applicant claims a main surface for the bridge and a component carrier main surface for the component carrier. Examiner interprets the main surface of claim 5 to be associated with the bridge.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have a higher density bottom surface contacts for optimized signal routing within the module.
Regarding claim 10, McLellan discloses the module according to claim 9, but is silent on wherein the bridging component is connected to the third electronic component via the first main surface.
Mallik discloses a bridging component (Fig. 6A, 640; ¶69-70) is connected to the third electronic component (Fig. 6A, 683; ¶69-70) via the first main surface (top).
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to connect the bridge to a third electronic component for increasing the chip density and capabilities of the module.
Regarding claim 21, McLellan discloses the module according to claim 1, but is silent on wherein the bridging component is configured to supply electric power to at least one of the at least two electronic components.
Mallik discloses a module wherein a bridging component (Fig. 2B, 240; ¶42) configured to supply electric power (¶42) an electronic component. (Fig. 2B, 240; ¶42)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to send power through the bridge to the chip to optimize power distribution and signal routing in the module.
Regarding claim 25, McLellan discloses the method according to claim 24, but is silent on wherein the method is carried out on panel level.
Mallik discloses forming a substrate on panel level. (¶56)
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form a substrate on panel level for accommodating multiple electronic components on or in a single substrate.
Claim(s) 14, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over McLellan (US-20180102338-A1; McLellan).
Regarding claim 14, McLellan discloses the module according to claim 1, wherein at least one of the at least two electronic components (Fig. 3, 25 or 30; ¶22) is connected to a power supply (not labeled) to distribute power from the power supply to the at least one of the at least two electronic components.
McLellan does not specifically disclose a power configuration. However, if at least one chip is not connected to power through the carrier the device will not work.
Therefore, before the effective filing date of the of the invention one of ordinary skill in the art would connect at least one electronic component to power to have a functioning device.
Regarding claim 18, McLellan discloses the module according to claim 1, wherein the module comprises a mounting base (not shown) on which the component carrier (Fig. 3, 15; ¶24) is mounted.
The cited art does not specifically disclose a mounting base. However, ball grid array 45 is for the purpose of mounting the module (package) to a main board.
Therefore before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to connect the package to a mounting board for making a computing device.
Regarding claim 20, McLellan discloses the module according to claim 1, wherein the bridging component (Fig. 3, 55; ¶24) and a further bridging component (Fig. 3, 55; ¶24) are arranged side by side in the stack at the same vertical level.
McLellan discloses it should be understood that the chiplets (bridges) 50 and 55 may number other than two, be of various footprints and be spatially arranged in a huge variety of ways on the circuit board 15 depending upon the electronic requirements of the circuit board 15, the number of semiconductor chips mounted thereon and other design considerations.
Therefore before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a side by side bridge with the first bridge for increasing the semiconductor chip capacity of the module.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over McLellan (US-20180102338-A1; McLellan) in view of Shih (US-20210050327-A1; Shih).
Regarding claim 16, McLellan discloses the module according to claim 15, but is silent on wherein the connection elements comprise at least two first horizontal electrically conductive redistribution structures in an x direction, at least two second horizontal electrically conductive redistribution structures in a y direction, and at least two vertical electrically conductive redistribution structures in a z direction; at least one of the first horizontal electrically conductive redistribution structures or the second horizontal electrically conductive redistribution structures is electrically connected to at least one vertical electrically conductive redistribution structure.
Shih discloses a module wherein the connection elements comprise at least two first horizontal electrically conductive redistribution structures (Fig. 11, 208; ¶52 Shih) in a x direction (left and right), at least two second horizontal electrically conductive redistribution structures in an y direction (Fig. 11, In three dimensions more pads 208 will be in the y direction ; ¶52 Shih), and at least two vertical electrically conductive redistribution structures in a z direction (Fig. 11, not labeled; ¶52 Shih); at least one of the first and second horizontal electrically conductive redistribution structures is electrically connected to at least one vertical electrically conductive redistribution structure.(Clear form drawings and associated text. If the redistribution are not connected to the vertical vias the device will not work.)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine a redistribution structure of Shih with the bridging component for forming high-density interconnect wiring for chip-to-chip connections.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over McLellan (US-20180102338-A1; McLellan) in view of Shih (US-20210050327-A1; Shih) and further in view of Kim et al. ( US-20150116965-A1; Kim).
Regarding claim 17, McLellan in view of Shih discloses the module according to claim 16, but is silent on comprising at least one of the following features: a mean distance between two first horizontal electrically conductive redistribution structures in the x direction is different from a mean distance between two second horizontal electrically conductive redistribution structures the in the y direction and/or different from a mean distance between two vertical electrically conductive redistribution structures in the z direction; and/or a mean distance between two second horizontal electrically conductive redistribution structures in the y direction is different from a mean distance between two vertical electrically conductive redistribution structures in the z direction.
Kim discloses a package where a bridge comprises a first set of conductive layers (Fig. 5B, Pad; ¶63) in an x-direction having a first spacing and a second set of conductive layers (Fig. 5B, 416/418; ¶64) in a y direction comprising a different spacing.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have the positioning as a matter of design choice . Shifting the position of the redistribution structures would not have modified the operation of the device. 2144.04 (VI)(C)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
