Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9-11 and 15-18 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Idgunji (US 2011/0302460)
Regarding claim 1, the prior art discloses:
A method comprising:
determining a first timing of a transition (200 in fig 4) sequence of a signal on a first path of an IC design (first path is the path that comprises signal CLK and DCLK and/or path that includes launch/source/input and capture/ end/output (see at least fig 3-4, par 6)), the first timing being based on an IC design signoff voltage (par 6);
determining a second timing (210 in fig 4) of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop (par 6) along the first path;
calculating a first path derating factor (par 6) based on a timing gap (Td in fig 4) between the first and second timings of the transition sequence; and
using the first path derating factor to evaluate the IC design (par 6, timing/design analysis, par 20, 101: path evaluation/re-evaluation)
Claims 9 and 15 recite similar subject matter and are rejected for the same reason. For statistical distribution, see scaling/probability (par 6, 9-11, 32, 38, 43-44, 78, 84, 85, 87, 89-9).
(Claim 10) wherein a path of the plurality of paths comprises a data launch path and a data capture path (par 6, 66, 69-71, 92-95), the corresponding transition sequence comprises a time variable between a data launch path transition time and a data capture path transition time (fig 1, 4, 6), and the corresponding timing gap has a value based on a difference between the time variables of the corresponding first and second timings (fig 1, 4, 6).
(Claim 11) wherein the calculating the corresponding path derating factor of the plurality of path derating factors comprises setting a product of the path derating factor and the data launch path transition time equal to a difference between the data launch path transition time and the timing gap (fig 1, 4, 6).
(Claim 16) wherein the path comprises a data launch path and a data capture path (par 6, 66, 69-71, 92-95), and the computer readable storage medium and the computer program code are configured to, with the processor, cause the processor to: calculate the timing gap based on a comparison of a first difference between a data launch path transition and a data capture transition of the first timing of the transition sequence to a second difference between the data launch path transition and the data capture transition of the second timing of the transition sequence (fig 1, 4, 6).
(Claim 17) calculate the path derating factor by setting a product of the path derating factor and a time of the data launch path transition equal to a difference between the data launch path transition time and the timing gap (par 6, 66, 69-71, 92-95, fig 1, 4, 6).
(Claim 18) calculate the path derating factor as one path derating factor of a plurality of path derating factors of a plurality of paths based on corresponding timing gaps between first and second timings of corresponding transition sequences (fig 1, 4, 6), wherein the second timings are calculated by assigning a statistical distribution (i.e., scaling/probability (par 6, 9-11, 32, 38, 43-44, 78, 84, 85, 87, 89-9)) of values to the corresponding voltage drops of the second timings; and perform the timing analysis on the IC design based on the plurality of path derating factors (par 6, timing/design analysis, par 20, 101: path evaluation/re-evaluation)
Claims 1, 8-11 and 15-18 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Fung (US patent 9,275,178)
Regarding claim 1, the prior art discloses:
A method comprising:
determining a first timing of a transition sequence (fig 3, signal rising edge at source) of a signal on a first path (fig 3, path comprise source to output signal) of an IC design, the first timing being based on an IC design signoff voltage, design signoff voltage comprises a slow corner voltage (fig 20)
determining a second timing of the transition sequence (fig 3, signal rising edge at output) of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop (background, col 1) along the first path;
calculating a first path derating factor based on a timing gap (see phase in fig 3) between the first and second timings of the transition sequence; and
using the first path derating factor to evaluate the IC design (timing analysis, design evaluation (fig 1, 20-21, 28, Field of Invention, background)
Claims 9, 15 recite similar subject matter and are rejected for the same reason. For statistical distribution, see graphs and table in fig 20-21, 23-26.
(Claim 10) wherein a path of the plurality of paths comprises a data launch path and a data capture path (see source path/begin of path and output/ end path in fig 3-10, 13-15), the corresponding transition sequence comprises a time variable between a data launch path transition time and a data capture path transition time (fig 3-10, 13-15), and the corresponding timing gap has a value based on a difference between the time variables of the corresponding first and second timings (fig 3-10, 13-15).
(Claim 11) wherein the calculating the corresponding path derating factor of the plurality of path derating factors comprises setting a product of the path derating factor and the data launch path transition time equal to a difference between the data launch path transition time and the timing gap fig 3-10, 13-15).
(Claim 16) wherein the path comprises a data launch path and a data capture path (fig 3-10, 13-15), and the computer readable storage medium and the computer program code are configured to, with the processor, cause the processor to: calculate the timing gap based on a comparison of a first difference between a data launch path transition and a data capture transition of the first timing of the transition sequence to a second difference between the data launch path transition and the data capture transition of the second timing of the transition sequence (fig 3-10, 13-15).
(Claim 17) calculate the path derating factor by setting a product of the path derating factor and a time of the data launch path transition equal to a difference between the data launch path transition time and the timing gap (fig 3-10, 13-15).
(Claim 18) calculate the path derating factor as one path derating factor of a plurality of path derating factors of a plurality of paths based on corresponding timing gaps between first and second timings of corresponding transition sequences (fig 3-10, 13-15), wherein the second timings are calculated by assigning a statistical distribution (see graphs and table in fig 20-21, 23-26) of values to the corresponding voltage drops of the second timings; and perform the timing analysis on the IC design based on the plurality of path derating factors (fig 1, 20-21, 28, Field of Invention, background)
Claims 1, 9-11 and 15-19 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Huynh (US 2017/0262569)
Regarding claim 1, the prior art discloses:
A method comprising:
determining a first timing of a transition sequence (abstract: transition time at input) of a signal on a first path (wire/path (abstract, fig 3-4, 7, 9)) of an IC design, the first timing being based on an IC design signoff voltage (par 46);
determining a second timing of the transition sequence (abstract: transition time at output) of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop (par 7) along the first path;
calculating a first path derating factor (abstract, fig 1-3, 6) based on a timing gap (transition time variation (abstract, fig 9)) between the first and second timings of the transition sequence; and
using the first path derating factor to evaluate the IC design (fig 1-3, 6).
Claims 9, 15 recite similar subject matter and are rejected for the same reason. For statistical distribution, see statistical static timing analysis and/or sigma values in par 2, 24, 26, 98, 100, 104-108, fig 8.
(Claim 10) wherein a path of the plurality of paths comprises a data launch path and a data capture path (input-output of wires/paths (abstract, fig 3-5, 7, 9)), the corresponding transition sequence comprises a time variable between a data launch path transition time and a data capture path transition time (transition time variation (abstract, fig 4, 7, 9)), and the corresponding timing gap has a value based on a difference between the time variables of the corresponding first and second timings (transition time variation (abstract, fig 4-5, 7, 9)).
(Claim 11) wherein the calculating the corresponding path derating factor (abstract, fig 1-3, 6) of the plurality of path derating factors comprises setting a product of the path derating factor and the data launch path transition time equal to a difference between the data launch path transition time and the timing gap ( abstract, fig 4-7, 9)).
(Claim 16) wherein the path comprises a data launch path and a data capture path (input-output of wires/paths (abstract, fig 3-5, 7, 9)), and the computer readable storage medium and the computer program code are configured to, with the processor, cause the processor to: calculate the timing gap based on a comparison of a first difference between a data launch path transition and a data capture transition of the first timing of the transition sequence to a second difference between the data launch path transition and the data capture transition of the second timing of the transition sequence (input-output of wires/paths (abstract, fig 3-5, 7, 9)).
(Claim 17) calculate the path derating factor by setting a product of the path derating factor and a time of the data launch path transition equal to a difference between the data launch path transition time and the timing gap (fig 5-9).
(Claim 18) calculate the path derating factor as one path derating factor of a plurality of path derating factors of a plurality of paths based on corresponding timing gaps between first and second timings of corresponding transition sequences (abstract, fig 3-7, 9), wherein the second timings are calculated by assigning a statistical distribution (see statistical static timing analysis and/or sigma values par 2, 24, 26, 98, 100, 104-108, 116, fig 8) of values to the corresponding voltage drops of the second timings; and perform the timing analysis on the IC design based on the plurality of path derating factors (1-3, 6)
(Claim 19) assign the statistical distribution of values to the voltage drops of the second timings by applying user-defined activity factors and/or a user-defined probability profile to the statistical distribution (par 107, 116).
Allowable Subject Matter
Claims 2-7, 12-14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2-7, 12-14 and 20 would be allowable because the prior art of record does not teach or suggest the limitations in: claim 2, claim 4, claim 12; and claim 20.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851