Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response Election/Restriction filed on 05/11/26.
Summary of claims
Claims 1-25 are pending.
Claims 1 and 8-10 are rejected.
Claims 2-7 and 11-13 are objected.
Claims 21-25 are allowed.
Claims 14-20 are cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 8-10 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Buyuktosunoglu et al. (US Pub. 2015/0032962).
As to claims 1 the prior art teaches a semiconductor device comprising:
single-bit flip-flops (SBFF regions) regions which comprise a multi-bit flip-flop (MBFF) region (see fig 30-33 and 38--43 apograph 0184- 0190);
the MBFF region having a two-dimensional floor plan represented by a grid including rows and a first column extending in corresponding first and perpendicular second directions, each SBFF region representing an intersection of a corresponding row and column (see fig 30-37 paragraph 0163-0170);
the SBFF regions being coupled in a daisy chain for which an output of a preceding one of the SBFF regions in the daisy chain is coupled to an input of a succeeding one of the SBFF regions in the daisy chain (see fig 30-34 and 39-43 paragraph 0177-0187);
and orientations of the SBFF regions relative to the first direction (α-orientations) being arranged in an alternating pattern relative to the second direction so that a two-dimensional representation of a flow path of a data signal along the first column has a serpentine shape (see fig 30-34 and 39-45 paragraph 0197-0207).
As to claim 8 the prior art teaches wherein: in the first column, the serpentine shape of the flow path of the data signal along the first column is a non-self-overlapping serpentine shape (see fig 30-37 paragraph 0158-0164).
As to claim 9 the prior art teaches wherein: in the first column, the serpentine shape of the flow path of the data signal along the first column is a self-overlapping serpentine shape (see fig 30-37 paragraph 0162-0168).
As to claim 10, the prior art teaches a semiconductor device comprising:
single-bit flip-flops (SBFF region) regions which comprise a multi-bit flip-flop (MBFF) region (see fig 30-33 and 38--43 apograph 0184- 0190);
the MBFF region having a two-dimensional floor plan represented by a grid including rows and first and second columns, extending in corresponding first and perpendicular second directions, each SBFF region representing an intersection of a corresponding row and column (see fig 30-37 paragraph 0163-0170);
the SBFF regions being coupled in a daisy chain for which an output of a preceding one of the SBFF regions in the daisy chain is coupled to an input of a succeeding one of the SBFF regions in the daisy chain (see fig 30-34 and 39-43 paragraph 0177-0187);
and orientations of the SBFF regions relative to the first direction (α-orientations) being arranged in an alternating pattern relative to the second direction so that a two-dimensional representation of a flow path of a data signal along each of the first and second columns has a corresponding serpentine shape (see fig 30-34 and 39-45 paragraph 0197-0207).
Allowable Subject Matter
Claims 21-25 are allowed.
Claims 2-7 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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