DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The substitute specification filed on 12/17/2025 is entered.
The replacement drawing filed on 12/17/2025 are entered.
Claim Status
Previous action: 1, 2, 3, 4, 7 through 19, 23, 42, and 63 rejected
Present action: 1, 2, 4, 7 through 19, 23, 42, and 63 rejected
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/3/2025 was filed after the mailing date of the non-final action on 9/17/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 63 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 63 recites the limitation "the semiconductor die" in line 1. There is insufficient antecedent basis for this limitation in the claim. Previously the claims have referred to a semiconductor device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 4, 7, 16, 17, 12, 13, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner (US 2020/0328150) in view of Mahler (US 2009/0039484).
Regarding claim 1.
Lichtenwalner teaches:
A semiconductor device comprising:
a semiconductor vertical power device structure (fig 1,6:10; [para 0027]),
a first metallization layer on the semiconductor vertical power device structure,
the first metallization layer comprising one or more structures (fig 6:40; [para 0042]);
a second metallization layer at least partially overlapping the first metallization layer ( [para 0042]),
a source bonding pad (fig 1:16; [para 0027]) and a gate bonding pad (fig 1:14; [para 0027]);
and an insulating layer (fig 6:46; [para 0032]) between the first metallization layer and the second metallization layer (fig 6 annotated),
the insulating layer comprising an insulating portion (fig 6 annotated; [para 0032]),
the insulating portion patterned to insulate the one or more structures (fig 6:40; [para 0042]) of the first metallization layer.
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Lichtenwalner does not teach the structures are made of metal in the embodiment.
Lichtenwalner teaches a second embodiment comprising
the one or more structures (gate metal layer) comprise metal (fig 5:18; [para 0031])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the structures from metal because of metals high conductivity and ability to be deposited and patterned in fine detail.
Lichtenwalner does not teach the source bonding pad and gate bonding pad are in the same level.
Mahler teaches:
the second metallization layer comprising a source bonding pad (fig 3:5; [para 0045]) and a gate bonding pad (fig 3:7; [para 0045]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bonding pads to be formed in the same level in order to be patterned in a single step and provide a level surface for subsequent steps and to maximize the active area.
Regarding claim 2.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 1, further
Lichtenwalner teaches:
the insulating layer (fig 6:46; [para 0032]) comprises a source contact opening to accommodate a source contact (fig 6:44; [para 0032]).
Regarding claim 4.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 1, further
Lichtenwalner teaches:
further comprising a third metallization layer (fig 6:22; [para 0032,0033]) between the insulating layer (fig 6:46; [para 0032]) and the second metallization layer (fig 6 annotated; [para 0032]),
further comprising a second insulating layer (fig 6:50; [para 0050]) between the third metallization layer (fig 6:22; [para 0032,0033]) and the second metallization layer (fig 6 annotated; [para 0032]),
wherein the second insulating layer (fig 6:50; [para 0050]) comprises a second insulating portion patterned to insulate the one or more structures (fig 6:40; [para 0032]) of the first metallization layer.
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Lichtenwalner teaches a second embodiment comprising
the one or more structures (gate metal layer) comprise metal (fig 5:18; [para 0031])
Regarding claim 7.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 4, further
Lichtenwalner teaches:
the second insulating layer (fig 6:50; [para 0032]) comprises a source contact opening to accommodate a source contact (fig 1,6:16; [para 0032,0033])
Regarding claim 12.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 1, further
Lichtenwalner does not teach a sensor in the above embodiment
Lichtenwalner teaches a second embodiment:
comprising a sensor (fig 12:64; [para 0041]) in the first metallization layer (on the drift region 36; [para 0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a sensor in order to sense strain, temperature or current of the device during operation
Regarding claim 13.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 12, further
Lichtenwalner teaches:
comprising a first via (fig 14:66; [para 0043]) connected to the sensor and a second via (coupled using a number of vias; [para 0043]) connected to the sensor (fig 12:64; [para 0041]),
the first via (fig 14:66; [para 0043]) and the second via each extending through the insulating layer (fig 14:46; [para 0043]).
Regarding claim 16.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 4, further
Lichtenwalner does not teach a sensor in the above embodiment
Lichtenwalner teaches a second embodiment:
further comprising a sensor (fig 14:64; [para 0043]) in the third metallization layer (on the dielectric 46; [para 0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a sensor in order to sense strain, temperature or current of the device during operation
Regarding claim 17.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 16, further
Lichtenwalner teaches:
further comprising a first via (fig 14:66; [para 0043]) connected to the sensor (fig 12:64; [para 0043]) and a second via (coupled using a number of vias; [para 0043]) connected to the sensor (fig 12:64; [para 0043]),
the first via and the second via (fig 14:66; [para 0043]) each extending through a second insulating layer (fig 6:50; [para 0032]) between the third metallization layer and the second metallization layer (fig 14 annotated),
the first via (fig 14:66; [para 0043]) coupled to a first bonding pad in the second metallization layer,
the second via coupled to a second bonding pad (fig 14:62; [para 0043]) in the second metallization layer (fig 12,14; [para 0043]).
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Regarding claim 18.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 1, further
Lichtenwalner teaches:
the one or more structures (fig 3,6:40; [para 0032]) comprise a gate runner (gate electrode) (fig 3,6; [para 0032]).
Lichtenwalner teaches a second embodiment comprising
making a gate metal layer (fig 5:18; [para 0031])
Regarding claim 19.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 1, further
Lichtenwalner teaches:
the one or more structures (fig 3,6:40; [para 0032]) form a gate runner network (coupled) (fig 3,6; [para 0032]).
Lichtenwalner teaches a second embodiment comprising
making a gate metal layer (fig 5:18; [para 0031])
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner (US 2020/0328150) in view of Mahler (US 2009/0039484) as applied to claim 1 and further in view of Haran (US 2021/0082805).
Regarding claim 8.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 1, further
Lichtenwalner teaches:
a via (fig 6:52; [para 0032]),
the via (fig 6:52; [para 0032]) connected to the one or more structures (fig 6:40; [para 0032]),
the via (fig 6:52; [para 0032]) extending through the insulating layer (fig 6:46; [para 0032]),
the via (fig 6:52; [para 0032]) connected to a [gate bonding pad (fig 6:18; [para 0032])in the second metallization layer (fig 6:; [para 0032]).
Lichtenwalner teaches a second embodiment comprising
making a gate metal layer (fig 5:18; [para 0031])
Lichtenwalner in view of Mahler does not teach planar interconnect structures.
Haran teaches:
a via (fig 4:1228b; [para 0064]),
the via (fig 4:1228b; [para 0064]) connected to a planar interconnect structure (fig 4:1228a; [para 0064]) in the second metallization layer (fig 4:1208; [para 0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a planar interconnect structure in order to enable lateral offset of subsequent structures such as a bonding pad.
Regarding claim 9.
Lichtenwalner in view of Mahler in view of Haran teaches the semiconductor device of claim 8,
Lichtenwalner teaches:
a gate bonding pad (fig 6:18; [para 0032]).
Haran teaches:
the planar interconnect structure (fig 4:1228a; [para 0064]) is coupled to a bonding pad (fig 4:1236; [para 0064]).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner (US 2020/0328150) in view of Mahler (US 2009/0039484) as applied to claim 4 and further in view of Haran (US 2021/0082805).
Regarding claim 10.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 4, above
Lichtenwalner teaches:
a via (fig 6:52; [para 0032]),
the via (fig 6:52; [para 0032]) connected to the one or more structures,
the via (fig 6:52; [para 0032]) extending through the insulating layer (fig 6:46; [para 0032]),
.
Lichtenwalner teaches a second embodiment comprising
making a gate metal layer (fig 5:18; [para 0031])
Lichtenwalner in view of Mahler does not teach planar interconnect structures.
Haran teaches:
a via (fig 4:1228b; [para 0064]),
the via (fig 4:1228b; [para 0064]) connected to a planar interconnect structure (fig 4:1228a; [para 0064]) in the third metallization layer (fig 4:1208; [para 0064]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a planar interconnect structure in order to enable lateral offset of subsequent structures such as a bonding pad.
Regarding claim 11.
Lichtenwalner in view of Mahler in view of Haran teaches the semiconductor device of claim 10.
Lichtenwalner teaches:
the via (fig 6:54; [para 0032]) electrically coupled to a gate bonding pad (fig 6:18; [para 0032]).
Haran teaches:
a second via coupled to the planar interconnect structure (fig 4:1288a; [para 0068]),
the second via (fig 4 annotated) electrically coupled to a bonding pad (fig 4:1236; [para 0070]).
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner (US 2020/0328150) in view of Mahler (US 2009/0039484) as applied to claim 13 and further in view of Kadow (US 2013/0187196)
Regarding claim 14.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 13, further
Lichtenwalner teaches:
a third metallization layer,
the first via (fig 6:52; [para 0032]) .
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Lichtenwalner in view of Mahler does not teach planar interconnection.
Kadow teaches:
a third metallization layer,
the first via (fig 2b:311a; [para 0046]) connected to a first planar interconnect structure (fig 2b:311; [para 0046]) in the third metallization layer and the second via connected to a second planar interconnect structure in the third metallization layer (annotated fig 2b; [para 0046]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide planar interconnect in order to enable lateral offset of a subsequent structures such as bonding pads
Regarding claim 15.
Lichtenwalner in view of Mahler in view of Kadow teaches the semiconductor device of claim 14, further
Kadow teaches:
comprising a third via (fig 2b:112a; [para 0046]) connecting the first planar interconnect structure (fig 2b:311; [para 0046]) to a first bonding pad (fig 2b:112; [para 0047]) in the second metallization layer and a fourth via (fig 2b:212a; [para 0047]) connecting the second planar interconnect structure to a second bonding pad (fig 2b:212; [para 0047]) in the second metallization layer.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a planar interconnect feature in order to enable the lateral offset of subsequent structures, further it would have been obvious to provide bonding pads in order to facilitate the connection of the device to external structures.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner (US 2020/0328150) in view of Mahler (US 2009/0039484) as applied to claim 19 and further in view of Hu (US 2021/0043741)
Regarding claim 23.
Lichtenwalner in view of Mahler teaches the semiconductor device of claim 19, above.
Lichtenwalner teaches:
the gate runner network (fig 6:40; [para 0032]) comprises a distributed gate runner network (fig 3,6),
the distributed gate runner network (fig 6:40; [para 0032]) comprising a plurality of non-contacting gate runners,
the non-contacting gate runners being separated from one another in the first metallization layer (fig 6,8; [para 0032,0038]).
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Lichtenwalner does not show the gates do not have a connection in the first metalization layer.
Hu teaches:
the non-contacting gate runners (fig 4:410; [para 0037]) being separated from one another such that there is no conductive electrical connection between the non-contacting gate runners in the layer (fig 4,6) (note there is no connection in the first metalization layer shown in fig 4, the runners are coupled into a network by the second metalization layer shown in fig 6)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to not contact in the first metalization layer so that the only connection between the gate runners will be the via bar and thereby result in an even power distribution across the structure.
Claim(s) 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner (US 2020/0328150) in view of Hu (US 2021/0043741).
Regarding claim 42.
Lichtenwalner teaches:
A semiconductor device, comprising:
a semiconductor structure (fig 6:10; [para 0032]);
and a first metallization layer on the semiconductor structure (fig 6:10; [para 0032]),
the first metallization layer comprising a distributed gate runner network (fig 6:40; [para 0032]);
wherein the distributed gate runner network (fig 6:40; [para 0032]) comprising a plurality of non-contacting gate runners (fig 6:40; [para 0032]),
the non-contacting gate runners (fig 6:40; [para 0032]) being separated from one another in the first metallization layer such that .
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Lichtenwalner does not teach that there is no conductive connection between
Hu teaches:
the non-contacting gate runners (fig 4:410; [para 0037]) being separated from one another such that there is no conductive electrical connection between the non-contacting gate runners in the layer (fig 4,6) (note there is no connection in the first metalization layer shown in fig 4, the runners are coupled into a network by the second metalization layer shown in fig 6)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to not contact in the first metalization layer so that the only connection between the gate runners will be the via bar and thereby result in an even power distribution across the structure.
Claim(s) 63 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner (US 2020/0328150) in view of Mahler (US 2009/0039484) as applied to claim 19 and further in view of Bauer (US 5661315)
Regarding claim 63.
Lichtenwalner in view of Mahler teaches the semiconductor die of claim 19.
Lichtenwalner in view of Bauer does not teach a crosshair gate runner network.
Bauer teaches:
The gate runner network (fig 1a:3; [column 1 lines 25-35]) is a crosshairs gate runner network with spurs (fig 1a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the runner network as across hair with spurs in order to distribute the current uniformly across the surface of the semiconductor device (column 1 lines 34-35).
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
The applicant argues that the applied prior art, Lichtenwalner (US 2020/0328150) in view of Hu (US 2021/0043741), does not teach “a plurality of not-contacting gate runners” and that Hu teaches that the gate structures are recessed within the body.
However, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Lichtenwaler, teaches gate runners that do not contact, but is ambiguous as to whether the over lying line (fig 6:22) is the only connection between the gate structures.
Hu provides a more expansive view of a vertical power device, in which it is clear that the gate structures (fig 4:410) are only connected by the overlying line. When considering the two references it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention that the first layer of metalization could comprise non-contacting, electrically isolated gate structures, and that any connection is confined to overlying metalization layers.
The applicant argues Lichtenwalner teaches away from combination with Mahler because the intention of Lichtenwalner is to increase the active area within the constraints of a limited area (paragraph 2).
However, Lichtenwalner explicitly states “It is generally desirable to maximize the total active area of a power transistor semiconductor die.” This does not teach away from modifications that would result in a larger active area, but rather that this would be the generally expected path. “a reference does not teach away if it merely expresses a general preference for an alternative invention but does not criticize, discredit or otherwise discourage investigation into the invention claimed.” DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 567 F.3d 1314, 1327 (Fed. Cir. 2009). MPEP 2145
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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