Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 & 36 are rejected under 35 U.S.C. 103 as being unpatentable over Nitta et al (US 2006/0145171, hereinafter Nitta).
With respect to claim 14 & 36, Nitta discloses a semiconductor device package, comprising: a conductive submount (e.g. 5 of Fig. 8);
Fig 8 does not explicitly discloses a semiconductor die on the conductive submount; and a metal layer; comprising a first material between the semiconductor die and the conductive submount. wherein the semiconductor device package is free of an intermetallic compound comprising the first material between the metal layer and the conductive submount.
However, in an analogous art, Fig 9 shows a semiconductor die (108) on the conductive submount; and / on (as claimed in claim 36) a metal layer (e.g. 107); comprising a first material (Para 0074, metallic) between the semiconductor die and the conductive submount. wherein the semiconductor device package is free of an intermetallic compound comprising the first material between the metal layer and the conductive submount (105 barrier layer is present preventing formation of IMC between 110 and 5).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Fig 8 and add semiconductor layer between the metal layer and submount to increase carrier injection and recombination efficiency.
Claims 1 – 3, 5 – 7, 9, 15 - 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nitta, further in view of Philliber (US 2005/0242419, hereinafter Philliber).
With respect to claim 1, Nitta discloses a semiconductor device package, comprising: a conductive submount (e.g. 5 of Fig. 8); a metal layer (e.g. 110 Au, Para 0074) comprising a first material (100) on the conductive submount; and a conductive buffer layer (109) comprising a second material (Zn) on the metal layer.
Nitta does not explicitly disclose wherein the second material of the conductive buffer layer (109 Zn) has limited or no solid solubility with respect to the first material of the metal layer (6Au).
In an analogous art, Philliber discloses wherein the second material of the conductive buffer layer has limited or no solid solubility with respect to the first material of the metal layer (Para 0035).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Nitta’s disclose invention and have limited solubility of second material to achieve stability and preventing the excessive intermetallic compound(IMC) formation.
With respect to claim 2, Nitta/Philliber discloses the semiconductor device package of Claim 1, Nitta further discloses wherein the conductive buffer layer (109) is between the metal layer (110) and the conductive submount (5), and wherein the semiconductor device package is free of an intermetallic compound comprising the first material (100) between the metal layer (110) and the conductive submount (5) (no IMC exists between layers as there are intermediary layers).
With respect to claim 3, Nitta/Philliber discloses the semiconductor device package of Claim 2, Nitta further discloses an intermetallic compound (6) comprising the second material between the conductive buffer layer (109) and the conductive submount (5).
With respect to claim 5, Nitta/Philliber discloses the semiconductor device package of Claim 1, Nitta further discloses the metal layer (110 Au, Para 0074) comprises a lower bonding interface (107 - InGaAlP) with the conductive buffer layer and an upper bonding interface (108 GaAs) opposite the lower bonding interface, wherein a first interfacial stress at the upper bonding interface is substantially similar to a second interfacial stress at the lower bonding interface (lattice matched compositions, InGaAlP/GaAs may exhibits substantially identical near-zero interfacial stress to other matched systems).
With respect to claim 6, Nitta/Philliber discloses the semiconductor device package of Claim 5, Nitta further discloses a bonding strength at the lower bonding interface (107 – InGaAlP) is less than a bonding strength of a direct bonding interface between the metal layer (au) and the conductive submount (metal) (in absence of more defined process parameters, in an ideal epitaxial case, InGaAlP strengths match or exceed Au bonds, but non-ideal conditions may make it lower strength possible).
With respect to claim 7, Nitta/Philliber discloses the semiconductor device package of Claim 5, Nitta further discloses a mold structure (100) on (indirectly in contact) the metal layer (110) opposite the conductive submount (5), wherein the upper bonding interface (108) is between the metal layer (110) and the mold structure (100).
With respect to claim 9, Nitta/Philliber discloses the semiconductor device package of Claim 7. wherein Nitta further discloses the metal layer is a first metal layer, and further comprising: a die attach material (101) on (indirectly on) the first metal layer opposite the conductive submount (6); and a second metal layer (106) on the die attach material, Wherein a third interfacial stress at a bonding interface between the first metal layer and the die attach material is substantially similar to a fourth interfacial stress at a bonding interface between the second metal layer and the die attach material (process variation condition dependent).
With respect to claim 15, Nitta discloses the semiconductor device package of Claim 14, further comprising: Nitta further discloses a conductive buffer layer (109) comprising a second material (Zn) between the conductive submount and the metal layer.
Nitta does not explicitly disclose wherein the second material of the conductive buffer layer (109 Zn) has limited or no solid solubility with respect to the first material of the metal layer (6Au).
In an analogous art, Philliber discloses wherein the second material of the conductive buffer layer has limited or no solid solubility with respect to the first material of the metal layer (Para 0035).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Nitta’s disclose invention and have limited solubility of second material to achieve stability and preventing the excessive intermetallic compound(IMC) formation.
With respect to claim 16, Nitta/Philliber discloses the semiconductor device package of Claim 15, Nitta further discloses an intermetallic compound (6) comprising the second material between the conductive buffer layer (109) and the conductive submount (5).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta /Philliber further in view of De Jaeger et al (US 9,634,107, hereinafter Jaeger).
With respect to claim 4, Nitta/Philliber discloses the semiconductor device package of Claim 2, wherein the first material (100) comprises a noble metal or alloy thereof (Para 0074) and the second material comprises metal.
Nitta/Phillibar does not disclose that the second material comprises metal at least one of nickel, cobalt, molybdenum, chromium, titanium, or alloys thereof.
In analogous art, Jaeger discloses the second material comprises metal at least one of nickel, cobalt, molybdenum, chromium, titanium, or alloys thereof (e.g. Abstract, substituting gold with Ti).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Nitta/Phillibar’s disclosure and replacing gold with titanium to achieve low temperature annealing to protect device.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta /Philliber further in view of Oliver (US 2020/0108528, hereinafter Oliver).
With respect to claim 8, Nitta /Philliber discloses the semiconductor device package of Claim 7.
Nitta/Philliber does not disclose wherein the mold structure comprises at least one of epoxy, silicone, or bismaleimide.
In an analogous art, Oliver discloses (Para 0034, exemplary substrate ….resin-based bismaleimide substrate or glass epoxy).
Therefore, POSITA would modify Nitta/Philliber disclosure to form substrate with resin based material to enhance light output.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta /Philliber further in view of Suchiro (2006/0060867, hereinafter Suchiro).
With respect to claim 11, Nitta/Philliber discloses the semiconductor device package of Claim 1.
Nitta/Philliber does not explicitly disclose wherein the conductive submount (5) comprises copper, iron, or alloys thereof.
In an analogous art, Suchiro discloses the conductive submount (5) comprises copper, iron, or alloys thereof (Para 0083, copper).
Therefore, POSITA would be motivated to substitute for copper to achieve excellent electric and thermal conductivity.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta /Philliber further in view of Bibl et al (US 8,426,227, hereinafter Bibl).
With respect to claim 12, Nitta/Philliber discloses the semiconductor device package of Claim 1.
Nitta/Philliber does not discloses the conductive buffer layer (109 Gold or zinc) has a thickness of about 0.1 microns to about 5 microns, or about 0.2 microns to about 1 micron.
Bibl discloses the conductive buffer layer (109 Gold or zinc) has a thickness of about 0.1 microns to about 5 microns, or about 0.2 microns to about 1 micron (Col 8, lines 15 – 25).
Therefore, POSITA would be motivated to achieve such thickness as discloses by Bibl to balance between adhesion, conductivity and minimal light absorption.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta /Philliber further in view of Waldrip et al (US 6,775,314, hereinafter Waldrip).
With respect to claim 13, Nitta/Philliber discloses the semiconductor device package of Claim 1.
Nitta/Phillisber does not disclose wherein the conductive buffer layer comprises a multi-layer structure including a plurality of alternating sublayers having respective thicknesses of about 0.1 microns to about 1 micron.
In analogous art, Waldrip discloses wherein the conductive buffer layer comprises a multi-layer structure including a plurality of alternating sublayers having respective thicknesses of about 0.1 microns to about 1 micron (implied thickness - Col 3, lines 30 – 65 – AIN interlayer alone is 150 angstrom).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Nitta/Philliber’s disclosure with Waldrip to improve light extraction.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta/Philliber further in view of De Jaeger et al (US 9,634,107, hereinafter Jaeger).
With respect to claim 17, Nitta/Philliber discloses the semiconductor device package of Claim 15, wherein the first material (100) comprises a noble metal or alloy thereof (Para 0074) and the second material comprises metal.
Nitta does not disclose that the second material comprises metal at least one of nickel, cobalt, molybdenum, chromium, titanium, or alloys thereof.
In analogous art, Jaeger discloses the second material comprises metal at least one of nickel, cobalt, molybdenum, chromium, titanium, or alloys thereof (e.g. Abstract, substituting gold with Ti).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Nitta’s disclosure and replacing gold with titanium to achieve low temperature annealing to protect device.
Claims 18 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nitta.
With respect to claim 18, Nitta further discloses the semiconductor device package of Claim 14, Nitta further discloses the metal layer (110 Au, Para 0074) comprises a lower bonding interface (107 - InGaAlP) with the conductive buffer layer and an upper bonding interface (108 GaAs) opposite the lower bonding interface.
Nitta does not explicitly discloses wherein a first interfacial stress at the upper bonding interface is substantially similar to a second interfacial stress at the lower bonding interface.
However, in another disclosure Nitta discloses wherein a first interfacial stress at the upper bonding interface is substantially similar to a second interfacial stress at the lower bonding interface (in another disclosure, lattice matched compositions, InGaAlP/GaAs may exhibits substantially identical near-zero interfacial stress to other matched systems) to avoid stress and reduce thermal resistance.
With respect to claim 19, Nitta discloses the semiconductor device package of Claim 18, Nitta further discloses a mold structure (100) on (indirectly in contact) the metal layer (110) opposite the conductive submount (5), wherein the upper bonding interface (108) is between the metal layer (110) and the mold structure (100).
With respect to claim 20, Nitta further discloses the semiconductor device package of Claim 18, Nitta further discloses a bonding strength at the lower bonding interface (107 – InGaAlP) is less than a bonding strength of a direct bonding interface between the metal layer (au) and the conductive submount (metal) (in absence of more defined process parameters, in an ideal epitaxial case, InGaAlP strengths match or exceed Au bonds, but non-ideal conditions may make it lower strength possible).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Mcknight-Macheil et al (US 2016/0307826, hereinafter Mcknight).
With respect to claim 21, Mcknight discloses a semiconductor device package, comprising: a conductive submount (e.g. 550 of Fig. 7); a semiconductor die on (100 – on is broad term and included any layer in contact directly or indirectly) the conductive submout and a conductive layer stack comprising a metal layer (e.g. 530) between the conductive submount and semiconductor die, the metal layer comprising a lower bonding interface (bottom surface of the 530) adjacent (lower bonding interface bonded via 529 to 550) the conductive submount and an upper bonding interface (top surface of leadframe layer 530) opposite the lower bonding interface.
In Figure 7 above, Mcknight does not explicitly disclose wherein a first interfacial stress at the upper bonding interface is substantially similar to a second interfacial stress at the lower bonding interface.
However, wherein a first interfacial stress at the upper bonding interface is substantially similar to a second interfacial stress at the lower bonding interface (both interfaces uses similar copper alloys and sintered silver attachment for CTE matching, ensuring balanced (substantially similar) stress to avoid warpage/delamination.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Merritt et al (US 6,027,957, hereinafter Merritt).
With respect to claim 30, Merritt discloses a semiconductor device package, comprising: a conductive submount (12 of Fig.1); and a metal layer (14) on the conductive submount, the metal layer comprising a lower bonding interface (bottom surface of the 14 contacting indirectly to submount 12) adjacent (indirect contact with submount surface via interlayers) the conductive submount. And a conductive buffer layer (for instance, 16 stacked with multiple layer) between the conductive submout 12 and the metal layer 14
Merritt does not explicitly disclose in Figure 1 wherein a bonding strength at the lower bonding interface is less than a bonding strength of a direct bonding interface between the metal layer and the conductive submount.
However, Merritt discloses wherein a bonding strength (alloy bond from interlayer and inter diffusion minimal thickness Col 4, lines 45 – 67) at the lower bonding interface is less (controlled diffusion composition yields weaker remelt/thinner bond; Abstract; Col 4 lines 45-67; Col 2 lines 10-40) than a bonding strength of a direct (un-melted high-melt second solder without interdiffusion Col 3, lines 20 – 30 claim 1) bonding interface between the metal layer and the conductive submount to avoid brittleness and stress from intermetallic compounds while reducing thermal resistances.
Claim 45 is rejected under 35 U.S.C. 103 as being unpatentable over Marbell et al (US 2021/0265250, hereinafter Marbell), in view of Mcknight).
With respect to claim 45, Marbell discloses a semiconductor device package, comprising: a conductive submount (abstract, metal submount 102/404);
a semiconductor die (400 HEMT – indeed a semiconductor device, Para 0045) on the conductive submount; and a conductive layer stack (200 IPD component) between the semiconductor die and the conductive submount (e.g. 200 is between 400 and extended portion of the conductive submount 102/404) , the conductive layer stack comprising a die attach material (422), at least one metal layer comprising a first material (the at least one IPD component 200 may include a metallization layer 240), and at least one conductive buffer layer (240 implemented as full face metallic layer…the at least one IPD component 200 may be double sided having two metallic layers outer/inner layer of made of copper, aluminum or gold).
Marbell does not disclose a second material having limited or no solid solubility with respect to the first material.
In analogous art, Mcknight discloses a second material having limited or no solid solubility with respect to the first material. Mcknight teaches at least one conductive buffer layer comprising a second material having limited to limited to no solubility with respect to the first material (copper lead frame alloy as buffer with limited solubility in sintered silver die attach prevent Intermetallic (Para 0073).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Marbell’s disclosed invention and having no solid solubility to reduce stress in the packaging.
Allowable Subject Matter
Claims 10, 47, 50 – 52, 55 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 10, Prior art of record as applied does not disclose or render obvious “wherein the conductive buffer layer is a first conductive buffer layer, and further comprising: a transistor die on the die attach material opposite the first metal layer; and a second conductive buffer layer between the transistor die and the second metal layer, wherein the second conductive buffer layer and the second metal layer comprise a back metal layer of the transistor die, and wherein a fifth interfacial stress at a bonding interface between the second metal layer and the second conductive buffer layer is substantially similar to the second interfacial stress at the lower bonding interface between the first metal layer and the first conductive buffer layer.” In combination with all other limitations of intervening claims.
Claims 48 – 49, 53 – 54, 56 are objected to by virtue of dependency on claims 47, 50-52 or 55.
Response to Arguments
Applicant's arguments filed 04/13/2026 have been fully considered but they are not persuasive.
Regarding claim 14, applicant argues as follows:
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Examiner respectfully submits the following:
Fig 8 does not explicitly discloses a semiconductor die on the conductive submount; and a metal layer; comprising a first material between the semiconductor die and the conductive submount. wherein the semiconductor device package is free of an intermetallic compound comprising the first material between the metal layer and the conductive submount.
However, in an analogous art, Fig 9 shows a semiconductor die (108) on the conductive submount; and a metal layer (e.g. 107); comprising a first material (Para 0074, metallic) between the semiconductor die and the conductive submount. wherein the semiconductor device package is free of an intermetallic compound comprising the first material between the metal layer and the conductive submount (105 barrier layer is present preventing formation of IMC between 110 and 5).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Fig 8 and add semiconductor layer between the metal layer and submount to increase carrier injection and recombination efficiency.
Regarding claim 1, applicant agues as follows:
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Examiner respectfully disagree and submits the following:
As cited in paragraph 0035, base metal can be gold, while metal can be any one of for example silver which is – for example - not soluble in its pure form. Therefore, argument is found not persuasive in view above and several other disclosures in the applied reference.
Arguments regarding amended claims 21, 30, 36 and 45 have been addressed above in the claim’s rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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