DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 11/14/2025. Claims 1-15 & 21-25 are pending in this application. Claims 16-20 are canceled.
Claim Objections
2. The claims are objected because of the following reasons:
Re claim 21,
-line 4: delete “deep trench capacitor circuitry;” which is duplicated/repeated,
-line 11: after “trench”, insert --capacitor--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 21, 22, 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al. (US 2022/0028825) in view of Pandit et al. (US 2022/0375898).
Re claim 21, Jeng teaches, under BRI, Figs. 2-6, [0021, 0026, 0027, 0038, 0040], a package (100), comprising:
-a first integrated circuit die (102, 121, 132), comprising:
deep trench capacitor circuitry (DTC 121), and
a seal ring structure (132);
-a second integrated circuit die (152), comprising:
a power management integrated circuit (e.g., formed of 142, 144, 148, 150); and
-a discharge path (conductive line 130A, via 124A) incorporated into the seal ring structure (132), electrically coupling (e.g., via conductive elements in 152 & via 160) the deep trench circuitry (121) to the power management integrated circuit (of 152).
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Jeng teaches logic dies [0081], but does not explicitly teach the second integrated circuit die comprising logic circuitry.
Pandit teaches IC die comprising logic circuit [0027, 0042].
As taught by Pandit, one of ordinary skill in the art would utilize & modify the above teaching to obtain the second integrated circuit die comprising logic circuitry as claimed, because logic circuitry is known as an essential element in IC die, and it aids in facilitating the communication between the dies.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Pandit in combination with Jeng due to above reason.
Re claim 22, Jeng teaches the discharge path (124A, 130A) connects to a voltage terminal of the power management integrated circuit (e.g., power supply modules, Fig. 26, [0081]).
Re claim 24, Jeng teaches the discharge path (124A, 130A) is incorporated into a portion of an inner seal ring structure of the seal ring structure (132).
Re claim 25, Jeng teaches the discharge path is for (as intended use) a diode source voltage of the power management integrated circuit (e.g., power supply modules & diodes as active devices, [0081, 0084]).
4. Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng as modified by Pandit as applied to claims 21 & 22 above, and further in view of Huang et al. (US 9,450,402).
The teachings of Jeng/Pandit have been discussed above.
Re claim 23, Jeng/Pandit does not explicitly teach the voltage terminal connects to an n- type contact of an electrostatic discharge diode or a p-type contact of the electrostatic discharge diode.
Huang teaches, Figs. 1-2, abstract & claim 27, the voltage terminal (of Vcc) connects to an n- type contact of an electrostatic discharge diode or a p-type contact (106) of the electrostatic discharge diode (22).
As taught by Huang, one of ordinary skill in the art would utilize & modify the above teaching to obtain the voltage terminal connects to an n- type contact of an electrostatic discharge diode or a p-type contact of the electrostatic discharge diode as claimed, because it aids in enhancing protection and reducing leakage in the formed package.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Jeng/Pandit due to above reason.
5. Claim(s) 21, 22 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2016/0126324) in view of Gandhi et al. (US 2021/0366873).
Re claim 21, Yu teaches, under BRI, Figs. 5-7, [0022, 0023, 0027, 0029, 0030], a package (10), comprising:
-a first integrated circuit die (17), comprising:
capacitor circuitry (81), and
a seal ring structure (50 in region 13);
-a second integrated circuit die (under 17 in region 11) comprising:
a power management integrated circuit (e.g., transistor); and
-a discharge path (61) incorporated into the seal ring structure (50), electrically coupling the deep trench circuity (81) to the power management integrated circuit (transistor) (within semiconductor structure 10).
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Yu does not explicitly teach deep trench capacitor circuitry & logic circuitry.
Gandhi teaches deep trench capacitor circuitry [0059] & logic circuitry (e.g. processor) [0032].
As taught by Gandhi, one of ordinary skill in the art would utilize & modify the above teaching to obtain deep trench capacitor circuitry & logic circuitry as claimed, because it aids in achieving desired design of chip package with enhanced performance at lower cost.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Gandhi in combination with Yu due to above reason.
Re claim 22, Yu teaches the discharge path (61) connects with a voltage terminal of the power management integrated circuit (based in integrated structure of 10, Fig. 5).
Re claim 24, Yu teaches, Fig. 5, the discharge path (61) is incorporated into a portion on an inner seal ring structure of the seal ring structure (50 in region 13).
Allowable Subject Matter
6. Claims 1-15 are allowed. The allowed subject matters include:
“a discharge path, incorporated into the seal ring structure, connecting the deep trench capacitor circuitry, the first seal ring segment, and the first voltage terminal; and
a second discharge path, incorporated into the seal ring structure, connecting the deep trench capacitor circuitry, the second seal ring segment, and the second voltage terminal,
wherein each of the first discharge path and the second discharge path electrically couple the deep trench circuitry to the power management integrated circuit” (claim 1); and
“a first discharge path, incorporated into the seal ring structure, connecting the first trench capacitor, the first seal ring segment, and the first voltage terminal, wherein the first discharge path electrically couples the first trench capacitor to the power management integrated circuit;
a second discharge path, incorporated into the seal ring structure, connecting the first trench capacitor, the second seal ring segment, and the second voltage terminal, wherein the second discharge path electrically couples the first trench capacitor to the power management integrated circuit; and
a third discharge path, incorporated into the seal ring structure, connecting the second trench capacitor, the first seal ring segment, and the first voltage terminal, wherein the third discharge path electrically couples the second trench capacitor to the power management integrated circuit” (claim 10).
Response to Arguments
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 12/4/25
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