Prosecution Insights
Last updated: April 19, 2026
Application No. 18/163,394

WAFER-LEVEL DIE-TRANSFER TOOL AND METHOD

Non-Final OA §103
Filed
Feb 02, 2023
Examiner
PETERSON, ERIK T
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
271 granted / 353 resolved
+8.8% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
40 currently pending
Career history
393
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
39.3%
-0.7% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
29.7%
-10.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 353 resolved cases

Office Action

§103
DETAILED ACTION A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 11, 2026, has been entered. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 11-17 and 19-27 are rejected under 35 U.S.C. 103 as being unpatentable over Arita et al. (US 2007/0264832, of record) in view of Smeys et al. (US 2011/0260248, of record), Okamoto (JP 2012-244013, citations from attached machine translation, newly cited), and Iwai (US 2010/0216313, newly cited). (Re Claim 11) Arita teaches a die-transfer method, comprising: attaching a frontside of a wafer to a first tape (Fig. 6A, wafer 1, tape 4); before attaching the frontside of the wafer to the first tape, forming first trenches on the frontside of the wafer through a first sawing process (Fig. 4), wherein the first trenches are formed to extend into a semiconductor substrate of the wafer but do not penetrate the semiconductor substrate after forming the first trenches and attaching the frontside of the wafer to the first tape (Fig. 6A); performing a second sawing process to a backside of the wafer, wherein the second sawing process cut the wafer into a plurality of dies (Fig. 6D); providing a second tape over the first tape with an adhesive surface of the second tape facing backsides of the dies (Fig. 7B, second tape 6). Arita is silent regarding after the second sawing process, moving the second tape downward to a first position above the backsides of the dies; applying a downward pressure from above the second tape so that the backsides of the dies contact and adhere to the second tape; and detaching the dies from the first tape by elevating the second tape to a second position higher than the first position. In addition, Arita is silent regarding first and second frames and movements thereof during the process. It is noted Arita cuts the tape 4 to the size of the wafer to avoid burning the tape during the plasma etching (¶80). A PHOSITA would recognize this adds extra steps to the process and also makes it more difficult to remove the dies from the tape as there is nothing significant to clamp or grip. A PHOSITA desiring to improve upon Arita’s process would be motivated to look to related plasma dicing art to teach alternatives where cutting the tape is not necessary. Related art from Iwai teaches an improved plasma etching apparatus wherein a wafer mounted on a conventional tape frame can be placed in the plasma etcher and a shield (40) is used to protect the tape and frame from the plasma (see Figs. 1-5). This advantageously allows for the wafer to be mounted to a tape frame for easier handling while avoiding having to trim the tape to the size of the wafer. A PHOSITA would find it obvious to perform the plasma etching according to Iwai such that the wafer can be mounted on a conventional tape frame which allows for easier handling while avoiding the need to trim the tape, and as discussed below, easier to transfer the dies and detach from the first tape. The use of tape frames is conventional practice in the art when using tape carriers. Arita shows the second tape is attached to the backsides of the dies (Fig. 7B), and applying a pressure to the back of the tape to ensure adhesion would be obvious to a PHOSITA since this is how tape is conventionally used and applied. Arita shows when the tapes are separated (Fig. 7C), the dies transfer to the second tape because the adhesive is stronger than the adhesive between the dies and the first tape. With respect to the movements of the tape, it is noted the claimed moving downward and elevating are relative terms with respect to an observer and the claims do not establish a reference point for determining which direction is down. Further still, since the dies are adhered to at least one of the tapes at all times, this transferring process is independent of gravity and the tapes/dies may be horizontal, or upside down, or any other orientation, and the process will still transfer the dies as intended. Regardless, a PHOSITA would be motivated to look to related tape-transferring art to determine how to automate this and perform these steps efficiently since Arita provides no guidance. Related art from Okamoto teaches (see Figs. 1-4) a process for transferring dies from one tape frame to another tape frame by moving the second tape and frame downward (Figs. 3a-3b) above the dies, then pressing the backside of the tape using a roller (Figs 3c-4a: 56/57), and then elevating the second tape and frame to a position higher than the first position (Fig. 4f), while keeping the first frame stationary to complete the transfer. Also by using conventional tape frames, the handling and transfer process is easier as the frames keep the tape stretched and securely attached to a rigid support to prevent the tape from flopping around thereby providing mechanical integrity. A PHOSITA would recognize this is preferrable to Arita’s process of trimming the tape and then having to peel the tape from the dies with nothing to grip except for the tape itself. When using tape frames according to Okamoto, the frames advantageously provide something much more substantial to grip or clamp onto to allow one to peel the dies from the first tape. In view of Okamoto, a PHOSITA would find it obvious to move the second tape and frame downward, adhere the tape to the dies by applying a pressure to the backsides using a roller, and then elevate the second tape and frame to a position higher than the first position using the disclosed apparatus to detach the dies when performing the steps corresponding to Arita’s Figs. 7B-7C as this would be an efficient way to automate Arita’s die transfer process. Regarding the limitations wherein the first trenches are formed to extend into a semiconductor substrate of the wafer but do not penetrate the semiconductor substrate, Arita is understood to teach a conventional SOI wafer (¶76), noting the bulk silicon layer 51, the buried oxide layer 52, and the (silicon) device layer 53. A PHOSITA would obviously recognize Arita’s semiconductor wafer structure as a conventional SOI wafer such as the SOI wafer taught by Smeys (see Fig. 1: SOI wafer 110+114+112). An SOI wafer is made of a bulk silicon layer, a buried oxide layer, and then a thin silicon device layer. A PHOSITA would find it obvious to use a conventional SOI wafer as taught by Smeys for Arita’s wafer. In light of Smeys’ SOI wafer structure, Arita’s first trenches extend into the uppermost silicon device layer and the buried oxide layer of the semiconductor substrate, but do not penetrate the bulk silicon layer of the semiconductor substrate. (Re Claim 12) wherein applying the downward pressure from above the second tape comprises moving a roller over the second tape (Okamoto Figs. 3c-4a). (Re Claim 13) further comprising: flipping the second tape so that the adhesive surface of the second tape faces downward (see Fig. 7B, the adhesive tape 6 is adhered to the dies and the adhesive faces downward, also see Okamoto Fig. 3a). (Re Claim 14) wherein the second tape is elevated at a constant speed until all of the dies are transferred from the first tape to the second tape. Arita and Okamoto (Fig. 4) are silent regarding wherein the second tape is elevated at a constant speed until all of the dies are transferred from the first tape to the second tape. Categorically, with respect to the claimed speed, there are two choices: the speed is either constant or variable. A PHOSITA would recognize that each will result in transferring the dies, and each would be obvious to try. With respect to deciding whether to use a constant speed or a variable speed, a PHOSITA would recognize a constant speed would be the obvious choice as this would be the easiest to control and would provide the most consistent and repeatable results. A constant peeling speed would be obvious to a PHOSITA. (Re Claim 15) Arita teaches a die-transfer method, comprising: attaching a frontside of a wafer to a first tape (Fig. 6A, wafer 1, tape 4); before attaching the frontside of the wafer to the first tape, forming first trenches on the frontside of the wafer through a first sawing process (Fig. 4), wherein the first trenches are formed to extend into a semiconductor substrate of the wafer but do not penetrate the semiconductor substrate after forming the first trenches and attaching the frontside of the wafer to the first tape (Fig. 6A); performing a second sawing process to a backside of the wafer, wherein the second sawing process cut the wafer into a plurality of dies (Fig. 6D). Arita is silent regarding after the second sawing process, moving the second tape downward to a first position above the backsides of the dies; applying a downward pressure from above the second tape so that the backsides of the dies contact and adhere to the second tape; and detaching the dies from the first tape by elevating the second tape to a second position higher than the first position. In addition, Arita is silent regarding first and second frames and movements thereof during the process. It is noted Arita cuts the tape 4 to the size of the wafer to avoid burning the tape during the plasma etching (¶80). A PHOSITA would recognize this adds extra steps to the process and also makes it more difficult to remove the dies from the tape as there is nothing significant to clamp or grip. A PHOSITA desiring to improve upon Arita’s process would be motivated to look to related plasma dicing art to teach alternatives where cutting the tape is not necessary. Related art from Iwai teaches an improved plasma etching apparatus wherein a wafer mounted on a conventional tape frame can be placed in the plasma etcher and a shield (40) is used to protect the tape and frame from the plasma (see Figs. 1-5). This advantageously allows for the wafer to be mounted to a tape frame for easier handling while avoiding having to trim the tape to the size of the wafer. A PHOSITA would find it obvious to perform the plasma etching according to Iwai such that the wafer can be mounted on a conventional tape frame which allows for easier handling while avoiding the need to trim the tape, and as discussed below, easier to transfer the dies and detach from the first tape. The use of tape frames is conventional practice in the art when using tape carriers. Arita shows the second tape is attached to the backsides of the dies (Fig. 7B), and applying a pressure to the back of the tape to ensure adhesion would be obvious to a PHOSITA since this is how tape is conventionally used and applied. Arita shows when the tapes are separated (Fig. 7C), the dies transfer to the second tape because the adhesive is stronger than the adhesive between the dies and the first tape. With respect to the movements of the tape, it is noted the claimed moving downward and elevating are relative terms with respect to an observer and the claims do not establish a reference point for determining which direction is down. Further still, since the dies are adhered to at least one of the tapes at all times, this transferring process is independent of gravity and the tapes/dies may be horizontal, or upside down, or any other orientation, and the process will still transfer the dies as intended. Regardless, a PHOSITA would be motivated to look to related tape-transferring art to determine how to automate this and perform these steps efficiently since Arita provides no guidance. Related art from Okamoto teaches (see Figs. 1-4) a process for transferring dies from one tape frame to another tape frame by moving the second tape and frame downward (Figs. 3a-3b) above the dies, then pressing the backside of the tape using a roller (Figs 3c-4a: 56/57), and then elevating the second tape and frame to a position higher than the first position (Fig. 4f), while keeping the first frame stationary to complete the transfer. Also by using conventional tape frames, the handling and transfer process is easier as the frames keep the tape stretched and securely attached to a rigid support to prevent the tape from flopping around thereby providing mechanical integrity. A PHOSITA would recognize this is preferrable to Arita’s process of trimming the tape and then having to peel the tape from the dies with nothing to grip except for the tape itself. When using tape frames according to Okamoto, the frames advantageously provide something much more substantial to grip or clamp onto to allow one to peel the dies from the first tape. In view of Okamoto, a PHOSITA would find it obvious to move the second tape and frame downward, adhere the tape to the dies by applying a pressure to the backsides using a roller, and then elevate the second tape and frame to a position higher than the first position using the disclosed apparatus to detach the dies when performing the steps corresponding to Arita’s Figs. 7B-7C as this would be an efficient way to automate Arita’s die transfer process. Regarding the limitations wherein the first trenches are formed to extend into a semiconductor substrate of the wafer but do not penetrate the semiconductor substrate, Arita is understood to teach a conventional SOI wafer (¶76), noting the bulk silicon layer 51, the buried oxide layer 52, and the (silicon) device layer 53. A PHOSITA would obviously recognize Arita’s semiconductor wafer structure as a conventional SOI wafer such as the SOI wafer taught by Smeys (see Fig. 1: SOI wafer 110+114+112). An SOI wafer is made of a bulk silicon layer, a buried oxide layer, and then a thin silicon device layer. A PHOSITA would find it obvious to use a conventional SOI wafer as taught by Smeys for Arita’s wafer. In light of Smeys’ SOI wafer structure, Arita’s first trenches extend into the uppermost silicon device layer and the buried oxide layer of the semiconductor substrate, but do not penetrate the bulk silicon layer of the semiconductor substrate. (Re Claim 16) wherein after detaching the dies from the first tape, a plurality of non-die portions of the wafer remain on the first tape (non-die portions 3, Fig. 7C). (Re Claim 17) further comprising: creating vacuum attraction from a bottom of the first tape while elevating the second tape (Okamoto Figs. 3-4, suction table 42, lines 71-76, 109-150). (Re Claim 19) wherein the second sawing process forms second trenches on the backside of the wafer to connect the first trenches, so that the wafer is cut into the dies (Fig. 6D). (Re Claim 20) wherein the second tape has greater adhesive strength than the first tape (this is obvious, perhaps inherent, in view of Fig. 7C where the tapes are vertically separated and the dies transfer to 6, if the adhesive on 4 was stronger, then the dies would remain attached to 4). (Re Claim 21) Arita teaches a die-transfer method, comprising: attaching a frontside of a wafer to a first tape (Fig. 6A, wafer 1, tape 4); before attaching the frontside of the wafer to the first tape, forming first trenches on the frontside of the wafer through a first sawing process (Fig. 4), wherein the first trenches are formed to extend into a semiconductor substrate of the wafer but do not penetrate the semiconductor substrate after forming the first trenches and attaching the frontside of the wafer to the first tape (Fig. 6A); performing a second sawing process to a backside of the wafer to cut the wafer into a plurality of dies and a plurality of non-die portions, wherein a thickness of the non-die portions is less than a thickness of the dies (Fig. 6D, non-die portions 3); providing a second tape over the first tape with an adhesive surface of the second tape facing backsides of the dies (Fig. 7B, second tape 6). Arita is silent regarding after the second sawing process, moving the second tape downward to a first position above the backsides of the dies; applying a downward pressure from above the second tape so that the backsides of the dies contact and adhere to the second tape; and detaching the dies from the first tape by elevating the second tape to a second position higher than the first position. In addition, Arita is silent regarding first and second frames and movements thereof during the process. It is noted Arita cuts the tape 4 to the size of the wafer to avoid burning the tape during the plasma etching (¶80). A PHOSITA would recognize this adds extra steps to the process and also makes it more difficult to remove the dies from the tape as there is nothing significant to clamp or grip. A PHOSITA desiring to improve upon Arita’s process would be motivated to look to related plasma dicing art to teach alternatives where cutting the tape is not necessary. Related art from Iwai teaches an improved plasma etching apparatus wherein a wafer mounted on a conventional tape frame can be placed in the plasma etcher and a shield (40) is used to protect the tape and frame from the plasma (see Figs. 1-5). This advantageously allows for the wafer to be mounted to a tape frame for easier handling while avoiding having to trim the tape to the size of the wafer. A PHOSITA would find it obvious to perform the plasma etching according to Iwai such that the wafer can be mounted on a conventional tape frame which allows for easier handling while avoiding the need to trim the tape, and as discussed below, easier to transfer the dies and detach from the first tape. The use of tape frames is conventional practice in the art when using tape carriers. Arita shows the second tape is attached to the backsides of the dies (Fig. 7B), and applying a pressure to the back of the tape to ensure adhesion would be obvious to a PHOSITA since this is how tape is conventionally used and applied. Arita shows when the tapes are separated (Fig. 7C), the dies transfer to the second tape because the adhesive is stronger than the adhesive between the dies and the first tape. With respect to the movements of the tape, it is noted the claimed moving downward and elevating are relative terms with respect to an observer and the claims do not establish a reference point for determining which direction is down. Further still, since the dies are adhered to at least one of the tapes at all times, this transferring process is independent of gravity and the tapes/dies may be horizontal, or upside down, or any other orientation, and the process will still transfer the dies as intended. Regardless, a PHOSITA would be motivated to look to related tape-transferring art to determine how to automate this and perform these steps efficiently since Arita provides no guidance. Related art from Okamoto teaches (see Figs. 1-4) a process for transferring dies from one tape frame to another tape frame by moving the second tape and frame downward (Figs. 3a-3b) above the dies, then pressing the backside of the tape using a roller (Figs 3c-4a: 56/57), and then elevating the second tape and frame to a position higher than the first position (Fig. 4f), while keeping the first frame stationary to complete the transfer. Also by using conventional tape frames, the handling and transfer process is easier as the frames keep the tape stretched and securely attached to a rigid support to prevent the tape from flopping around thereby providing mechanical integrity. A PHOSITA would recognize this is preferrable to Arita’s process of trimming the tape and then having to peel the tape from the dies with nothing to grip except for the tape itself. When using tape frames according to Okamoto, the frames advantageously provide something much more substantial to grip or clamp onto to allow one to peel the dies from the first tape. In view of Okamoto, a PHOSITA would find it obvious to move the second tape and frame downward, adhere the tape to the dies by applying a pressure to the backsides using a roller, and then elevate the second tape and frame to a position higher than the first position using the disclosed apparatus to detach the dies when performing the steps corresponding to Arita’s Figs. 7B-7C as this would be an efficient way to automate Arita’s die transfer process. Regarding the limitations wherein the first trenches are formed to extend into a semiconductor substrate of the wafer but do not penetrate the semiconductor substrate, Arita is understood to teach a conventional SOI wafer (¶76), noting the bulk silicon layer 51, the buried oxide layer 52, and the (silicon) device layer 53. A PHOSITA would obviously recognize Arita’s semiconductor wafer structure as a conventional SOI wafer such as the SOI wafer taught by Smeys (see Fig. 1: SOI wafer 110+114+112). An SOI wafer is made of a bulk silicon layer, a buried oxide layer, and then a thin silicon device layer. A PHOSITA would find it obvious to use a conventional SOI wafer as taught by Smeys for Arita’s wafer. In light of Smeys’ SOI wafer structure, Arita’s first trenches extend into the uppermost silicon device layer and the buried oxide layer of the semiconductor substrate, but do not penetrate the bulk silicon layer of the semiconductor substrate. (Re Claim 22) wherein when the backsides of the dies contact and adhere to the second tape, the non-die portions do not contact and adhere to the second tape (see Figs. 7B-7C). (Re Claim 23) wherein after all the dies of the wafer are transferred from the first tape to the second tape, the non-die portions remain on the first tape (see Figs. 7B-7C). (Re Claim 24) wherein the second tape is elevated at a constant speed until all of the dies are transferred from the first tape to the second tape. Arita and Okamoto (Fig. 4) are silent regarding wherein the second tape is elevated at a constant speed until all of the dies are transferred from the first tape to the second tape. Categorically, with respect to the claimed speed, there are two choices: the speed is either constant or variable. A PHOSITA would recognize that each will result in transferring the dies, and each would be obvious to try. With respect to deciding whether to use a constant speed or a variable speed, a PHOSITA would recognize a constant speed would be the obvious choice as this would be the easiest to control and would provide the most consistent and repeatable results. A constant peeling speed would be obvious to a PHOSITA. (Re Claim 25) wherein the second tape has greater adhesive strength than the first tape (this is obvious, perhaps inherent, in view of Fig. 7C where the tapes are vertically separated and the dies transfer to 6, if the adhesive on 4 was stronger, then the dies would remain attached to 4). (Re Claim 26) wherein applying the downward pressure from above the second tape comprises moving a roller over the second tape (Yamamoto Fig. 20). (Re Claim 27) wherein the second sawing process comprises forming second trenches on the backside of the wafer to connect the first trenches, thereby cutting the wafer into the dies and the non-die portions (Fig. 6D). Claims 28 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Arita et al., Smeys et al., Okamoto, and Iwai, as applied above, and further in view of Mikami et al. (US 2020/0144095), of record. (Re Claim 28) further comprising: performing a thinning process to the backside of the wafer, after forming the first trenches and before performing the second sawing process. Arita is silent regarding performing a thinning process to the backside of the wafer, after forming the first trenches and before performing the second sawing process. A PHOSITA would recognize thinning the wafer from the backside is a conventional processing step as taught by Mikami (Fig. 1A: trenches are formed, Fig. 2A: wafer is thinned from backside, prior to a second sawing step in Fig. 4B). Thinning a wafer is advantageous as this reduces the amount of unnecessary bulk silicon material allowing for smaller devices, better electrical performance, heat dissipation, and more power efficient .Thinning from the backside is obvious because devices are typically formed in the frontside and if the frontside is thinned, the devices will be destroyed. Also, thinning before completely cutting through the wafer increases the yield of the thinning process since if the dies are already singulated, the individual dies have less mechanical integrity and adhesion and are more likely to delaminate. A PHOSITA would find it obvious to perform the thinning as taught by Mikami, after Arita forms the first trenches. (Re Claim 31) further comprising: after performing the second sawing process, performing an expanding process to expand the first tape so that a distance between one of the plurality of dies and an adjacent non-die portion of the plurality of non-die portions is increased. Arita is silent regarding a tape expansion process. A PHOSITA would recognize this is conventional practice in the dicing art, making it easier to pick dies from the tape after dicing without damaging the dies. Related art from Mikami discloses tape expansion after the sawing step that singulates the bulk wafer (¶¶92, 102). A PHOSITA would find it obvious to expand the tape after dicing in order to make the subsequent pick-and-place operation easier and less likely to damage dies if they are too close to one another. Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Arita et al., Smeys et al., Okamoto, and Iwai, as applied above, and further in view of Hwang et al. (US 2005/0153522), of record, Vaupel et al. (US 2014/0367015), of record, and Grivna et al. (US 2014/0127880), of record. (Re Claim 32) further comprising: after performing the second sawing process, performing a curing process to the first tape to reduce the adhesive strength of the first tape. Arita is silent regarding performing a curing process to the first tape to reduce the adhesive strength of the first tape. A PHOSITA desiring to improve upon Arita’s process would be motivated to look to related art to teach possible modifications. It is noted Arita peels the first tape from the dies after the second sawing process and clearly the adhesion between the dies and the first tape is less than the adhesion between the dies and the second tape since the dies remain attached to the second tape. Rather than rely on natural differences in adhesion between the two tapes, UV adhesives are well known in the art and can be UV cured to either increase or decrease adhesion as desired. Related art from Hwang teaches using a UV curable tape wherein UV exposure decreases adhesion to make it easier to peel (¶35). Related art from Vaupel also teaches a UV curable adhesive tape’s adhesive strength can be reduced by the UV exposure (¶¶21, 25, 26). Related art from Grivna also similarly recognizes the advantages of such UV adhesive tapes can be exposed to UV light to decrease the adhesion to make peeling from the tape easier (¶¶29, 36, 37, 41). In view of the prior art, a PHOSITA would find it obvious to use a UV curable adhesive tape for Arita’s first tape wherein the adhesive strength can deliberately reduced when desired to make it easier to release the tape. Allowable Subject Matter Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments have been considered but are moot in view of the new grounds of rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Feb 02, 2023
Application Filed
Jul 22, 2025
Non-Final Rejection — §103
Oct 23, 2025
Response Filed
Nov 05, 2025
Final Rejection — §103
Jan 11, 2026
Request for Continued Examination
Jan 16, 2026
Response after Non-Final Action
Jan 27, 2026
Non-Final Rejection — §103
Mar 26, 2026
Interview Requested
Apr 07, 2026
Applicant Interview (Telephonic)
Apr 07, 2026
Examiner Interview Summary

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+12.0%)
2y 8m
Median Time to Grant
High
PTA Risk
Based on 353 resolved cases by this examiner. Grant probability derived from career allow rate.

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