DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on October 15,2025 is acknowledged.
Claim Objections
Claims 28 and 34 are objected to because of the following informalities: The limitations “the arched/convex top surface of the conductive capping layer is greater than 0 and less than 90°C” should be expressed in degrees only not in degrees Celsius. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21, 26-29, 34 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Bae et al (US Publication No. 2022/0328485).
Regarding claim 21, Bae discloses a method for forming a semiconductor device structure, comprising: forming a first dielectric layer Fig 14A, 128 over a substrate Fig 14A, 110; forming a gate electrode layer Fig 15A, GL in the first dielectric layer Fig 15A; recessing the gate electrode layer to form a recessed top surface lower than a top surface of the first dielectric layer¶0191; forming a first dielectric capping layer Fig 15A, 140 over the recessed top surface of the gate electrode layer Fig 15A, GL; forming an opening in the first dielectric layer to expose a source/drain region in the substrate ¶0193; forming a first conductive layer in the opening ¶0194; forming a conductive capping layer Fig 2B, CAP, Fig 3B-3E or Fig 3G, CAPG with an arched top surface in the opening and over the first conductive layer¶0055; and forming a second dielectric capping layer Fig 2B, 170 and Fig 3G, 146G ¶0109 in the opening to cover the arched top surface of the conductive capping layer Fig 2B and Fig 3G.
Regarding claim 26, Bae discloses wherein a top surface of the first dielectric capping layer Fig 2A, 140 is substantially level with a top surface of the second dielectric capping layer Fig 2A, 170.
Regarding claim 27, Bae discloses wherein a bottom surface of the conductive capping layer is lower than the recessed top surface of the gate electrode layer Fig 2A.
Regarding claim 28, Bae discloses wherein an angle between the top surface of the first conductive layer and the arched top surface of the conductive capping layer is greater than 0 and less than 90° Fig 3C-3G.
Regarding claim 29, Bae discloses method for forming a semiconductor device structure, comprising: forming a first dielectric layer Fig 14A, 128 over a substrate; forming a gate electrode layer Fig 15A, GL in the first dielectric layer Fig 15A, 128; forming an opening adjacent to the gate electrode layer and in the first dielectric layer¶0193; forming a first conductive layer in the opening¶0194; forming a conductive capping layer Fig 2B, CAP and Fig 3B-3E with a convex top surface in the opening and over the first conductive layer Fig 2B and Fig 3B-3E; and forming a dielectric capping layer Fig 2B, 170 and Fig 3G, 146G ¶0109 in the opening to cover the convex top surface of the conductive capping layer Fig 3G.
Regarding claim 34, Bae discloses wherein an angle between the top surface of the first conductive layer and the convex top surface of the conductive capping layer is greater than 0 and less than 90° Fig 3C-3G.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al (US Publication No. 2022/0328485) in view of Chen et al (US Publication No. 2017/0186849).
Regarding claim 16, Bae discloses a method for forming a semiconductor device structure Fig 2A-3H, comprising: forming a first dielectric layer Fig 2A, 128 or Fig 12A, 128 over a substrate Fig 12A, 110; forming a gate structure in the first dielectric layer Fig 2A and Fig 12A, wherein the gate structure comprises: a gate dielectric layer; a gate electrode layer formed over the gate dielectric layer Fig 2A; and a gate spacer structure Fig 2A, 120 covering a sidewall of the gate electrode layer Fig 2A; etching the first dielectric layer to form an opening that exposes a source/drain region in the substrate ¶0193; forming a first conductive layer in the opening ¶0194, wherein a top surface of the first conductive layer is lower than a top surface of the gate spacer structure Fig 2A and Fig 16A; forming a conductive capping layer layer Fig 2B, CAP and Fig 3B-3E with an arched top surface in the opening to cover the top surface of the first conductive ¶0055; and forming a first dielectric capping layer Fig 2B, 170 in the opening to cover the arched top surface of the conductive capping layer ¶0070; and forming a second conductive layer Fig 2B, CAV ¶0071, wherein the second conductive layer is electrically connected to the source/drain region via the first conductive layer Fig 2A-3H. Bae discloses all the limitations but silent on the second conductive layer in the first dielectric capping layer. Whereas Chen discloses forming a conductive capping layer Fig 7, 90; and forming a first dielectric capping layer Fig 9, 100 in the opening to cover the conductive capping layer Fig 9; and forming a second conductive layer Fig 10, 115 in the first dielectric capping layer Fig 10, 100, wherein the second conductive layer is electrically connected to the source/drain region Fig 10. Bae and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bae because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the interconnection of Bae and incorporate the teaching of Chen to improve device connectivity.
Regarding claim 17, Bae discloses recessing the gate electrode layer ¶0191; and forming a second dielectric capping layer Fig 15A, 140 over the recessed gate electrode layer¶0191, wherein a bottom surface of the second dielectric capping layer is higher than the arched top surface of the conductive capping layer Fig 2A, and a top surface of the second dielectric capping layer Fig 2A, 140 and Fig 15A, 140 is substantially level with a top surface of the first dielectric capping layer Fig 2A, 170.
Regarding claim 20, Bae discloses successively forming a second dielectric layer Fig 21A-22A, 182 and a third dielectric layer Fig 21A-22A, 184 to cover the gate structure and the first dielectric capping layer before forming the second conductive layer Fig 21A-22A, CAV and after forming the first dielectric capping layer Fig 21A-22A.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Bae et al (US Publication No. 2022/0328485) in view of Chen et al (US Publication No. 2017/0186849) and in further view of Tsai et al (US Publication No. 2020/0135912).
Regarding claim 19, Bae discloses all the limitations except for the removal of the spacer layer. Whereas Tsai discloses wherein a portion of the spacer structure is removed during the etching of the first dielectric layer, and wherein a space formed by the removal of the portion of the spacer structure is filled with at least one of the first conductive layer, the first dielectric capping layer, and the second conductive layer Fig 2J-2L. Bae and Tsai are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bae because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the etching step of Bae and incorporate the teaching of Tsai to provide a wider opening to facilitate device interconnectivity.
Claim 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al (US Publication No. 2022/0328485) in view of Tsai et al (US Publication No. 2020/0135912).
Regarding claim 22, Bae discloses all the limitations but silent on the masking layer. Whereas Tsai discloses wherein forming the opening comprises: forming a masking layer Fig 2E, 154 to cover the dielectric capping layer and expose the first dielectric layer Fig 2E-2F; and etching the exposed first dielectric layer using the masking layer as an etch mask Fig 2F. Bae and Tsai are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bae because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the etching step of Bae and incorporate the teaching of Tsai by providing a masking layer to protect adjoining layer and precisely etch the desired surface.
Regarding claim 23, Tsai discloses wherein forming the first conductive layer comprises: forming a conductive material layer over the masking layer Fig 2G and filling the opening Fig 2G; and removing the conductive material layer over the masking layer and a portion of the conductive material layer in the opening to form the first conductive layer Fig 2H. While Bae discloses the first conductive layer has a top surface lower than the recessed top surface of the gate electrode layer Fig 2A.
Allowable Subject Matter
Claims 18, 24-25, 30-33, 35 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest method described in claims 18, 24-25, 30-33, 35.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811