DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102 and § 103, filed 2/17/2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lan, Wen-Ting et al. (Pub No. US 20210159311 A1) (hereinafter, Lan), and further in view of Jhan, Yi-Ruei et al. (Pub No. US 20210257480 A1) (hereinafter, Jhan).
6. Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102 and § 103, filed 2/17/2026, with respect to the rejection(s) of claim 9 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lan, Wen-Ting et al. (Pub No. US 20210159311 A1) (hereinafter, Lan).
Regarding claim 9, referring to Figures Fig 1K-2/2G-1, the dielectric wall structure is now anticipated in its broadest reasonable interpretation by Protection layers, Dielectric fin structure, Capping layers and Inner spacers (120/122/126/116/142), i.e. the inner spacers 142 have been added.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 9-10, 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lan, Wen-Ting et al. (Pub No. US 20210159311 A1) (hereinafter, Lan).
Re Claim 9 (Currently Amended), Lan teaches a semiconductor structure, comprising:
a dielectric wall structure (Protection layers/Dielectric fin structure/Capping layers/Inner spacers; 120/122/126/116/142; Fig 1K-2/2G-1; ¶[0032]) formed over a substrate (Substrate; 102; Fig 1D, wherein the dielectric wall structure comprises:
a bottom portion (Protection layers/Dielectric fin structure/Inner spacers; 120/122/142; Fig 1K-2; ¶[0032]), wherein the bottom portion has a first sidewall (Sidewall of 120 extending up along the source/drain region 144; Fig 1L-2) continuously extending from a top point (Top of dielectric fin 122; Fig 1L-2) to a bottom point (Bottom of dielectric fin 122; Fig 1L-2); and
a cap layer (Dielectric capping layers; 126; Fig 1J-2; ¶[0036]) formed over the bottom portion;
a first isolation feature (Interlayer dielectric layer, dielectric capping layer and/or gate dielectric layer; 150/126/164; Fig 1T-2; ¶[0054]) formed over and interfacing (150 interfaces with 126; Fig 1T-2) with the dielectric wall structure;
first channel structures (Left side second semiconductor material layers; 108; Fig 1K-2; ¶[0022]) attached to the dielectric wall structure;
and a first gate structure (Left side gate structures; 160-1; Fig 2G-1; ¶[0068]) abutting the first channel structures, the dielectric wall structure, and the first isolation feature.
wherein the first channel structures attached to first portions (Right side inner spacers; 142; Fig 1K-2; ¶[0047]) of the first sidewall surface of the bottom portion of the dielectric wall structure,
while the first gate structure attached to second portions (Left side inner spacers (not labelled; Fig 2G-1) of the first sidewall of the bottom portion of the dielectric wall structure.
Re Claim 10 (Original), Lan teaches the semiconductor structure as claimed in claim 9, further comprising:
second channel structures (Right side second semiconductor material layers; 108; Fig 1K-2; ¶[0022]) attached to a second sidewall surface (Right sidewalls of capping layers 116; Fig 2A-2) of the dielectric wall structure (Protection layers/Dielectric fin structure/Capping layers; 120/122/126/116; Fig 1K-2/2G-1; ¶[0032]) opposite the first sidewall surface of the dielectric wall structure; and
a second gate structure (Right side gate structures; 160-1; Fig 2G-1; ¶[0068]) abutting the second channel structures, the dielectric wall structure, and the first isolation feature,
wherein the first gate structure is isolated from the second gate structure by the first isolation feature (Dielectric capping layer; 126; Fig 1T-2; ¶[0054]).
Re Claim 12 (Original), Lan teaches the semiconductor structure as claimed in claim 10, further comprising:
a base fin structure (Base of fins 104-1 below channels 108; Fig 1A-1/1F-2) protruding from the substrate, wherein the dielectric wall structure (Protection layers/Dielectric fin structure/Capping layers; 120/120'/122/126/116; Fig 1K-2/2G-1; ¶[0032]) is in direct contact (Base fin directly contacts 120'; Fig 1F-2) with the base fin structure.
Re Claim 13 (Original), Lan teaches the semiconductor structure as claimed in claim 12, wherein the base fin structure (Base of fins 104-1 below channels 108; Fig 1A-1/1F-2) vertically overlaps the first channel structures (Left side second semiconductor material layers; 108; Fig 1K-2; ¶[0022]) and the second channel structure (Right side second semiconductor material layers; 108; Fig 1K-2; ¶[0022]).
Re Claim 14 (Original), Lan teaches the semiconductor structure as claimed in claim 12, wherein a bottom surface (Bottom surface of 120'; Fig 1F-2) of the dielectric wall structure (Protection layers/Dielectric fin structure/Capping layers; 120/120'/122/126/116; Fig 1K-2/2G-1; ¶[0032]) is lower than a top surface (Top surface of 102/104-1 right below 120'; Fig 1F-2) of the base fin structure (Base of fins 104-1 below channels 108; Fig 1A-1/1F-2).
Re Claim 15 (Original), Lan teaches the semiconductor structure as claimed in claim 9, further comprising:
a second isolation feature (Center isolation structure and liner layer; 114/112; Fig 2G-2; ¶¶[0025, 0027]) laterally spaced apart from the first isolation feature (Lateral isolation structure and liner layer; 114/112; Fig 2G-2; ¶¶[0025, 0027]),
wherein the first isolation feature and the second isolation feature physically contact opposite sides (Opposite sides of gate structure surrounding channels are contacted by liner layer 112) of the first gate structure, and the second isolation feature is thicker (Center isolation structure 114 is thicker than lateral isolation features; Fig 2G-2) than the first isolation feature.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1-3, 5-6 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lan, Wen-Ting et al. (Pub No. US 20210159311 A1) (hereinafter, Lan), and further in view of Jhan, Yi-Ruei et al. (Pub No. US 20210257480 A1) (hereinafter, Jhan).
Lan, Fig 1K-2: Intermediate stage of removing sacrificial layers from fin structure
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Re Claim 1 (Currently Amended), Lan teaches a semiconductor structure, comprising:
channel structures (Second semiconductor material layers; 108; Fig 1K-2; ¶[0022]) vertically stacked over a substrate (Substrate; 102; Fig 1H-1; ¶[0021]);
Lan, Fig 1L-2: Intermediate stage showing source/drain structures inserted adjacent to fin structures
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a source/drain structure (Source/drain structures; 144; Fig 1L-2; ¶[0049]) laterally attached to the channel structures along a first direction (Direction along sidewall of 122, e.g. y-direction; Fig 1L-2);
a dielectric wall structure (Protection layers/Dielectric fin structure/Capping layers; 120/122/126/116; Fig 1K-2; ¶[0032]) laterally attached to the channel structures along a second direction (Direction along channel structures, e.g. x-direction; Fig 1K-2) different from the first direction, wherein the dielectric wall structure comprises:
a bottom portion (Protection layers/Dielectric fin structure; 120/122; Fig 1K-2; ¶[0032]); and
Lan, Fig 1T-2: Forming isolation feature over cap layer
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a cap layer (Dielectric capping layers; 126; Fig 1T-2; ¶[0036]) formed over the bottom portion;
an isolation feature (Interlayer dielectric layer and/or gate dielectric layer; 150/164; Fig 1T-2; ¶[0054]) vertically overlapping the cap layer of the dielectric wall structure;
Lan, Figs 2G-1/2G-2: Forming gate structures around channel structures
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and a gate structure (Gate electrode layer; 166; Fig 2G-1; ¶[0069]) formed around the channel structures and covering a sidewall (Gate electrode 166 is disposed on sidewall of gate spacer 138; Fig 1T-2) of the isolation feature.
However, Lan does not teach wherein an interface between a top surface of the cap layer and the isolation feature is lower than a top surface of the gate structure.
In the same field of endeavor, Jhan teaches wherein an interface between a top surface of the cap layer (High-K dielectric layer; 230; Fig 13B; ¶[0032]) and the isolation feature (Dielectric fin; 228; Fig 13B; ¶[0031]) is lower than a top surface (Top surface of 268; Fig 13B) of the gate structure (Gate electrode; 268; Fig 13B; ¶[0048]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an interface between a top surface of the cap layer and the isolation feature that is lower than a top surface of the gate structure, as taught by Jhan, for the semiconductor structure as taught by Lan. One would have been motivated to do this with a reasonable expectation of success because the gate structure being above and surrounding the interface between the cap layer and isolation feature allows for the gate structure to maximize electrostatic control over the channel, which suppresses leakage current and enables further miniaturization.
Re Claim 2 (Currently Amended), Lan teaches the semiconductor structure as claimed in claim 1, wherein a void (Air gaps; 146; Fig 1L-2; ¶[0049]) is encapsulated by the bottom portion (Protection layers/Dielectric fin structure; 120/122; Fig 1L-2; ¶[0032]) of the dielectric wall structure (Protection layers/Dielectric fin structure/Capping layers; 120/122/126/116; Fig 1K-2; ¶[0032]).
Lan, Fig 1L-2: Semiconductor structure with void in bottom portion
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Re Claim 3 (Original), Lan teaches the semiconductor structure as claimed in claim 1, wherein the isolation feature (Interlayer dielectric layer and/or gate dielectric layer; 150/164; Fig 1T-2; ¶[0054]) has a first dimension (Length of 138/150 along y-direction; Fig 1T-2) along the second direction,
the cap layer (Dielectric capping layers; 126; Fig 1J-2; ¶[0036]) has a second dimension (Length of 126 along y-direction; Fig 1T-2) along the second direction, and
the first dimension is smaller (Length of 138 and 150 are smaller than length of 126 along y-direction; Fig 1T-2) than the second dimension.
Lan, Fig 2A-1/2A-2: Forming dielectric wall structure between channels
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Re Claim 5 (Original), Lan teaches the semiconductor structure as claimed in claim 1, wherein the dielectric wall structure (Protection layers/Dielectric fin structure/Capping layers; 120/122/126/116; Fig 1K-2; ¶[0032]) comprises:
a dielectric shell layer (Protection layers; 120/120'; Fig 2A-1; ¶[0029]); and
a core portion (Dielectric fin structures; 122; Fig 2A-2; ¶[0032]) over the dielectric shell layer,
wherein the dielectric shell layer is sandwiched between the core portion and the channel structures (Second semiconductor material layers; 108; Fig 1K-2; ¶[0022]), and the dielectric shell layer and the core portion are made of different materials (Protection layers 120/120' may be SiCN, SiCON, SiN and dielectric fins tructures 122 may be SiO2; ¶¶[0034-0035]).
Re Claim 6 (Original), Lan teaches the semiconductor structure as claimed in claim 5, wherein the dielectric shell layer (Protection layers; 120/120'; Fig 2A-1; ¶[0029]) comprises:
a bottom region (Protection layer; 120'; Fig 2A-1; ¶[0029]) vertically below the core portion (Dielectric fin structures; 122; Fig 2A-2; ¶[0032]);
a sidewall region (Protection layer; 120; Fig 2A-1; ¶[0029]) laterally around the core portion; and
an extending region (Protection layer extends around capping layer 116; Fig 2A-1) laterally around the cap layer (Capping layers; 126/116; Fig 1K-2; ¶[0032]).
Re Claim 21 (New), Lan teaches the semiconductor structure as claimed in claim 1, wherein a width (Width of gate dielectric layer along x-direction (horizontal); 164; Fig 2G-1) of the isolation feature (Gate dielectric layer; 164; Fig 2G-1; ¶[0054]) is smaller than a width (Width of the protection layer 120 along x-direction (horizontal); Fig 2G-1) of the dielectric wall structure (Protection layer; 120; Fig 2G-1; ¶[0032]) in a cross-sectional view along the second direction (Direction along channel structures; Fig 2G-1).
Allowable Subject Matter
11. Claims 16-20 are allowed.
Claims 7 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the closest prior art Lan, Wen-Ting et al. (Pub No. US 20210159311 A1) (hereinafter, Lan) either singularly or in combination fails to anticipate or render obvious
“The semiconductor structure as claimed in claim 6, wherein the extending region of the dielectric shell layer has a first thickness along the second direction, the sidewall region of the dielectric shell layer has a second thickness along the second direction, and the first thickness is smaller than the second thickness,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 11, the closest prior art Lan, Wen-Ting et al. (Pub No. US 20210159311 A1) (hereinafter, Lan) either singularly or in combination fails to anticipate or render obvious
“The semiconductor structure as claimed in claim 10, further comprising:
a first source/drain structure attached to the first sidewall surface of the dielectric wall structure; and
a second source/drain structure attached to the second sidewall surface of the dielectric wall structure,
wherein a first top surface of a first portion of the dielectric wall structure sandwiched between the first source/drain structure and the second source/drain structure is lower than a second top surface of a second portion of the dielectric wall structure sandwiched between the first channel structures and the second channel structures,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 16, the closest prior art Lan, Wen-Ting et al. (Pub No. US 20210159311 A1) (hereinafter, Lan) and Prince, Matthew J. et al. (Pub No. US 20240213026 A1) (hereinafter, Prince) either singularly or in combination fails to anticipate or render obvious
“A method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over a substrate;
patterning the semiconductor stack to form a first fin structure and a second fin structure, wherein the first fin structure has a first sidewall and a second sidewall opposite the first sidewall, and the second fin structure has a third sidewall facing the second sidewall of the first fin structure and a fourth sidewall opposite the third sidewall;
forming a bottom portion of a dielectric wall structure in a first space between the second sidewall of the first fin structure and the third sidewall of the second fin structure;
forming a cap layer of the dielectric wall structure over the bottom portion in the first space;
removing the first semiconductor material layers of the first fin structure to form first channel structures and removing the first semiconductor material layers of the second fin structure to form second channel structures;
forming a first gate structure abutting the first channel structures and a second gate structure abutting the second channel structures;
partially removing the first gate structure and the second gate structure to form a first trench exposing the cap layer of the dielectric wall structure; and
forming a first isolation feature in the first trench to electrically isolate the first gate structure and the second gate structure,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 7, Lan does not teach a “dielectric shell layer which has a first thickness in a first direction which is smaller than a second thickness in a second direction,” and the prior art of record cannot be reasonably combined to create a dielectric shell of the desired thicknesses of the applicant’s invention.
Re claim 11, Lan does not disclose a dielectric wall between the source/drain structures which has a first top surface lower than a second top surface of a dielectric wall between channel structures.
Re claim 16, Lan in view of Prince does not disclose partially removing the first gate structure and the second gate structure to form a first trench exposing the cap layer of the dielectric wall structure. Although Prince discloses forming a trench in a gate structure, it does not lead to exposing a cap layer of a dielectric wall structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Lin, Zhi-Chang et al. (Pub No. US 20210134797 A1) (hereinafter, Lin) discloses semiconductor nanostructures disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.
[2] Wang, Chen-Han et al. (Pub No. US 20210083090 A1) (hereinafter, Wang) discloses the method for manufacturing the semiconductor structure includes forming nanowire structures over a substrate and forming a gate structure across nanowire structures. The method for manufacturing the semiconductor structure also includes forming a source/drain structure adjacent to the gate structure and forming a Si layer over the source/drain structure. The method for manufacturing the semiconductor structure also includes forming a SiGe layer over the Si layer and oxidizing the SiGe layer to form an oxide layer. The method for manufacturing the semiconductor structure also includes forming a contact through the Si layer over the source/drain structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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