DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 02/02/2023, 01/09/2025 and 03/18/2025 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Election/Restrictions
The Applicant elected Invention I, and Species 2 which are directed to Claims 1-14 without traverse in the reply filed on 11/13/2025 and are acknowledged and under consideration.
Response to Amendment
The amendment with respect to claims 5, 11, and 13-14 filed on 11/13/2025 have been fully considered for examination based on their merits. The previously presented claims 1-4, 6-10, and 12 have been considered. New Claims 21-26 have been considered and entered. Claims 15-20 are canceled.
Specification
The amendment to the Specification filed on 11/13/2025 has been considered and entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jingyun Zhang et al, (hereinafter ZHANG), US 20200373300 A1.
Regarding Claim 1, ZHANG teaches a method for manufacturing a semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), comprising:
forming a first channel structure (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) in a first region (Fig. 1A, 104, first nanosheet stack) and a second channel structure (Fig. 1A, 110, channel layer in the 106, second nanosheet stack) in a second region (Fig. 1A, 106, second nanosheet stack);
forming a first type of source/drain structures (Fig. 13A, 1310/1320, [0056]) attached to opposite sides of the first channel structure (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) and a second type of source/drain structures (Fig. 13A, 1310/1320, [0056]) attached to opposite sides of the second channel structure (Fig. 1A, 110, channel layer in the 106, second nanosheet stack);
forming a first gate dielectric layer (Fig. 4, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]) having a first portion (Fig. 4, 402 in the 104, first nanosheet stack) covering the first channel structure (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) and a second portion (Fig. 4, 402 in the 106, second nanosheet stack) covering the second channel structure (Fig. 1A, 110, channel layer in the 106, second nanosheet stack);
driving (Fig. 14, steps 1402-1408) a first metal element (Fig. 14, 1408; Fig. 10, 1002, dipole layer formation and contacts the dielectric layer, 404 of the dipole diffusion in the first nanosheet stack(s), 104, [0067-0069]) into the first portion of the first gate dielectric layer (Figs. 7/10, 402, gate dielectric layer in the 104, first nanosheet stack);
forming a cap layer over both the first portion (Figs. 7/10, 1006, capping layer in the 104, first nanosheet stack) and the second portion (Figs. 7/10, 1006, capping layer in the 106, second nanosheet stack) of the first gate dielectric layer (Fig. 4, 402) after driving the first metal element (Fig. 14, 1408; Fig. 10, 1002, dipole layer formation and contacts the dielectric layer, 404 of the dipole diffusion in the first nanosheet stack(s), 104, [0067-0069]) into the first portion (Figs. 7/10, 104, first nanosheet stack) of the first gate dielectric layer (Fig. 4, 402);
performing an annealing process (annealing process such as spike annealing, [0069]) on the first gate dielectric layer (Fig. 10, 402) under the cap layer (Fig. 10, 1006); and
forming a work function metal layer (Figs. 13/13A, a work function setting metal layer (not shown) may be deposited onto the gate dielectric layer 1202, [0072-0074]; optionally, the work function layer may form a replacement gate structure, 1302, 1304 on one or more the channel layers, 110, [0074]) that continuously extends from the first region (Figs. 1A/12, 104, first nanosheet stack) to the second region (Figs. 1A/12, 106, second nanosheet stack) and covering the first channel structure (Figs. 1A/12, 110, channel layer in the 104, first nanosheet stack) the second channel structure (Figs. 1A/12, 110, channel layer in the 106, second nanosheet stack).
Regarding Claim 5, ZHANG teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]) as claimed in claim 1, wherein the first channel structure (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) and the second channel structure (Fig. 1A, 110, channel layer in the 106, second nanosheet stack) are suspended over a substrate (Figs. 1A/13A, 102) and spaced apart from each other (Fig. 1A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of Jae-Jung Kim et al, (hereinafter KIM), US 20220352389 A1.
Regarding Claim 2, ZHANG teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]) as claimed in claim 1, further comprising: forming a second gate dielectric layer (Fig. 10, 404, dielectric layer, [0060]) over both the first portion (Fig. 4, 404 in the 104, first nanosheet stack) and the second portion (Fig. 4, 404 in the 106, second nanosheet stack) of the first gate dielectric layer (Fig. 4, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]) after driving (Fig. 14, steps 1402-1408) the first metal element (Fig. 14, 1408; Fig. 10, 1002, dipole layer formation and contacts the dielectric layer, 404 of the dipole diffusion in the first nanosheet stack(s), 104, [0067-0069]) into the first portion of the first gate dielectric layer (Figs. 7/10, 402, gate dielectric layer in the 104, first nanosheet stack).
Though ZHANG teaches the method involving dipole diffusion in a specific way as demonstrated in the flow chart of Figure 14, ZHANG does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: forming a second gate dielectric layer over both the first portion and the second portion of the first gate dielectric layer after driving the first metal element into the first portion of the first gate dielectric layer.
KIM teaches the method for manufacturing the semiconductor structure (Figs. 4-17, method of manufacturing a semiconductor device, [0058]), further comprising: forming a second gate dielectric layer (Figs. 19/20, 252/254, the first/second high-k dielectric pattern) over both the first portion (Figs. 19/20, Y/X) and the second portion (Figs. 19/20, X/Y) of the first gate dielectric layer (Figs. 19/20, 242/244, the first/second interface pattern) after driving the first metal element (Figs. 1920, 314/312, second/first dipole layer) into the first portion (Figs. 19, Y/X) of the first gate dielectric layer (Figs. 19/20, 242/244, the first/second interface pattern).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG to incorporate the teachings of KIM, such that the method for manufacturing the semiconductor structure, further comprising: forming a second gate dielectric layer over both the first portion and the second portion of the first gate dielectric layer after driving the first metal element into the first portion of the first gate dielectric layer. The said arrangement facilitate for example, the second dipole layer, 314 may be formed by forming and thermally treating a layer aluminum oxide on the second high-k dielectric pattern, 254, so that dipoles of aluminum oxide in the layer may move into the interface between the second interface pattern, 244 and the second high-k dielectric pattern, 254 (KIM, [0107]).
Regarding Claim 6, ZHANG teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]) as claimed in claim 1.
ZHANG does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: driving a second metal element into a second portion of the first gate dielectric layer in the second region, wherein the first metal element is different from the second metal element.
KIM teaches the method for manufacturing the semiconductor structure (Figs. 4-17, method of manufacturing a semiconductor device, [0058]), further comprising: driving a second metal element (Fig. 19, 314, the second dipole layer, may include aluminum oxide dipoles, [0105-0106]) into a second portion (Fig. 19, the second gate structure, 284, [015]) of the first gate dielectric layer (Fig. 19, 244/254, the second interface pattern/the second high-k dielectric pattern, [0105]) in the second region (Fig. 19, Y region,), wherein the first metal element (Fig. 20, 312, the first dipole layer, may include lanthanum oxide dipoles, [0108-0110]) is different from the second metal element (Fig. 19, 314, the second dipole layer, may include aluminum oxide dipoles, [0105-0106]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG to incorporate the teachings of KIM, such that the method for manufacturing the semiconductor structure, further comprising: driving a second metal element into a second portion of the first gate dielectric layer in the second region, wherein the first metal element is different from the second metal element, so that the threshold voltage of the first transistor may move in a negative direction for the first metal element, lanthanum oxide compared to the second element, aluminum oxide for which the threshold voltage of the second transistor may move in a positive direction (KIM, [0106], [0110]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of KIM, and further in view of Cheng Chung Liang, (hereinafter LIANG), KR 20210152376 A.
Regarding Claim 3, ZHANG as modified by KIM teaches the method for manufacturing the semiconductor structure as claimed in claim 2.
ZHANG further teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), wherein the second gate dielectric layer (Fig. 4, 402, IL or Interfacial layer, [0060]) is thinner (annotated Figure 4, however, the drawing is not to scale and for the visual appearance only) than the first gate dielectric layer (Fig. 4, 404, dielectric layer, [0060]).
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Though ZHANG teaches the interfacial layer and the gate dielectric layer with different layer thickness, ZHANG does not explicitly disclose the method for manufacturing the semiconductor structure, wherein the second gate dielectric layer is thinner than the first gate dielectric layer.
LIANG teaches the method for manufacturing the semiconductor structure (Fig. 11, flowchart illustrating a method of manufacturing a semiconductor device, [0004]), wherein the second gate dielectric layer (Fig. 22, 222/220, first gate dielectric layers have a thickness of about 9 Angstroms and/or Fig. 22, 230, the second gate dielectric layer has a thickness of about 6 Angstroms, [0017]) is thinner (Fig. 22, the firs gate dielectric layer (222) may be similar to or slightly thinner than the first IL layer (210); and/or the second gate dielectric layer (230) is substantially thinner than the first gate dielectric layer (222, 220), [0017]) than the first gate dielectric layer (Fig. 22, 210, first interfacial layer, IL, has a thickness of about 10 Angstroms, [0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHANG as modified by KIM to incorporate the teachings of LIANG, such that the method for manufacturing the semiconductor structure, wherein the second gate dielectric layer is thinner than the first gate dielectric layer, so that the thickness controlling within and between the dielectric layers generally control the geometry size (i.e. smallest component that can be created using a manufacturing process) or lines have been reduced, thus the scaling down process generally provides benefits by increasing production efficiency and lowering associated costs (LIANG, [0003]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of KIM, further in view of LIANG, and further in view of Kuo-Cheng Ching et al, (hereinafter CHING), US 20200105758 A1.
Regarding Claim 4, ZHANG as modified by KIM and LIANG teaches the method for manufacturing the semiconductor structure as claimed in claim 3.
ZHANG further teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), wherein the second gate dielectric layer (Fig. 10, 404, dielectric layer, [0060]) and the first gate dielectric layer (Figs. 4/10, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]) are made of a same material (silicon oxide, oxynitride or other suitable materials, [0056], [0061], [0002]).
Though ZHANG teaches the interfacial layer and dielectric layer with oxide type materials (silicon oxide or high-k dielectrics), ZHANG does not explicitly disclose the method for manufacturing the semiconductor structure, wherein the second gate dielectric layer and the first gate dielectric layer are made of a same material.
CHING teaches the method for manufacturing the semiconductor structure semiconductor (Figs. 15B/15C, a method of forming a semiconductor device, [0085]), wherein the second gate dielectric layer (Figs. 15B/15C, 1514, high-k gate dielectric layer, [0063]) and the first gate dielectric layer (Figs. 15B/15C, 1512, interfacial layer, [0063])are made of a same material ([0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHANG modified by KIM and LIANG to incorporate the teachings of CHING, such that the method for manufacturing the semiconductor structure, wherein the second gate dielectric layer and the first gate dielectric layer are made of a same material to enhance the compatibility, and to reduce the materials’ based manufacturing cost, while improving the device performance (CHING, [0001]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of Hwichan Jun et al, (hereinafter JUN), US 20220109047 A1.
Regarding Claim 7, ZHANG teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]) as claimed in claim 1.
ZHANG does not disclose explicitly the method for manufacturing the semiconductor structure, wherein the first region vertically overlaps the second region.
JUN teaches the method for manufacturing the semiconductor structure (Fig. 4A, 400, semiconductor device, methods of manufacturing the multi-stack nanosheet structure, [0008]), wherein the first region (Fig. 4A, 410, 1st nanosheet stack, [0065]) vertically overlaps the second region (Fig. 4A, 420, 2nd nanosheet stack, [0065]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG to incorporate the teachings of JUN, such that the method for manufacturing the semiconductor structure, wherein the first region vertically overlaps the second region, so that the nanosheet layers function as multiple channels for current flow between the source/drain regions of the nanosheet transistor, and due to this structure, improved control of current flow through the multiple channels is enabled in addition to higher device density in a semiconductor device including the nanosheet transistor (JUN, [0003]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of Dan S. Lavric et al, (hereinafter LAVRIC), US 20220093596 A1.
Regarding Claim 8, ZHANG teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]) as claimed in claim 1.
ZHANG does not disclose explicitly the method for manufacturing the semiconductor structure as claimed in claim 1, wherein the work function metal layer is made of a p-type work function metal.
LAVRIC teaches the method for manufacturing the semiconductor structure (Fig. 3, 300, various operations in a method of fabricating an integrated circuit structure, [0007-0008]), wherein the work function metal layer (Fig. 1A, 116B) is made of a p-type work function metal (P-type, [0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG to incorporate the teachings of CHU, such that the method for manufacturing the semiconductor structure, wherein the work function metal layer is made of a p-type work function metal, so that the p-type conductive layer 116B is continuous with the p-type conductive layer 116A in the p-type region, 104, in other words, the p-type conductive layer is continuous between the first NMOS gate stack and the second NMOS gate stack, and is continuous between the second NMOS gate stack and the third NMOS gate stack to scaling multi-gate and nanowire transistors as building blocks of microelectronic circuitry with reduced number of fundamental building blocks fabricated in a given region (LAVRIC, [0033], [0044], [0004]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of CHING.
Regarding Claim 9, ZHANG teaches a method for manufacturing a semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), comprising:
forming a first type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]) and a second type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]) over a substrate (Figs. 1A/13A, 102);
forming first channel structures (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) vertically suspended over the substrate (Figs. 1A/13A, 102) and sandwiched between the first type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]);
forming second channel structures (Fig. 1A, 110, channel layer in the 106, second nanosheet stack) vertically suspended over the substrate (Figs. 1A/13A, 102) and sandwiched between the second type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]);
forming a first gate dielectric layer (Fig. 4, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]) having a first portion (Fig. 4, 402 in the 104, first nanosheet stack) wrapping around the first channel structures (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) and a second portion (Fig. 4, 402 in the 106, second nanosheet stack) wrapping around the second channel structures (Fig. 1A, 110, channel layer in the 106, second nanosheet stack);
forming a first dipole layer (Fig. 14, 1408; Fig. 10, 1002, dipole layer formation and contacts the dielectric layer, 404 of the dipole diffusion in the first nanosheet stack(s), 104, [0067-0069]) in physical contact with the first portion of the first gate dielectric layer (Figs. 7/10, 402, gate dielectric layer in the 104, first nanosheet stack) and spaced apart from the second portion of the first gate dielectric layer (Figs. 7/10, 402, gate dielectric layer in the 106, second nanosheet stack);
forming a second gate dielectric layer (Fig. 10, 404, dielectric layer, [0060]) over the first gate dielectric layer (Figs. 4/10, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]), wherein the first gate dielectric layer (Figs. 4/10, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]) and the second gate dielectric layer (Fig. 10, 404, dielectric layer, [0060]) are made of a same dielectric material (silicon oxide, oxynitride or other suitable materials, [0056], [0061], [0002]);
forming a cap layer (Fig. 10, 1006, capping layer) wrapping around the first channel structures (Figs. 7/10, 1006, capping layer in the 104, first nanosheet stack) and the second channel structures (Figs. 7/10, 1006, capping layer in the 106, second nanosheet stack) over the second gate dielectric layer Fig. 10, 404, dielectric layer, [0060]); and
annealing (annealing process such as spike annealing, [0069]) the first gate dielectric layer (Fig. 10, 402) and the second gate dielectric layer (Fig. 10, 404) after forming ([0069]) the cap layer (Fig. 10, 1006, capping layer).
Though ZHANG teaches the interfacial layer and dielectric layer with oxide type materials (silicon oxide or high-k dielectrics), ZHANG does not explicitly disclose a method for manufacturing a semiconductor, comprising: forming a second gate dielectric layer over the first gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are made of a same dielectric material.
CHING teaches a method for manufacturing a semiconductor (Figs. 15B/15C, a method of forming a semiconductor device, [0085]), comprising: forming a second gate dielectric layer (Figs. 15B/15C, 1514, high-k gate dielectric layer, [0063]) over the first gate dielectric layer (Figs. 15B/15C, 1512, interfacial layer, [0063]), wherein the first gate dielectric layer (Figs. 15B/15C, 1512, interfacial layer, [0063]) and the second gate dielectric layer (Figs. 15B/15C, 1514, high-k gate dielectric layer, [0063]) are made of a same dielectric material ([0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG to incorporate the teachings of CHING, such that a method for manufacturing a semiconductor, comprising: forming a second gate dielectric layer over the first gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are made of a same dielectric material to enhance the compatibility, and to reduce the materials’ based manufacturing cost, while improving the device performance (CHING, [0001]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of CHING, further in view of Ming-Huei Lin et al, (hereinafter LIN), US 20180166274 A1, and further in view of Chung-Liang Cheng et al, (hereinafter CHENG), US 20200294865 A1.
Regarding Claim 10, ZHANG as modified by CHING teaches the method for manufacturing the semiconductor structure as claimed in claim 9.
ZHANG further teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), further comprising:
forming a work function metal layer Fig. 12, a work function setting metal layer (not shown) may be deposited onto the gate dielectric layer 1202, [0072]); and
forming a gate filling layer in direct contact with a top surface of the work function metal layer (Fig. 13A, optionally, the work function layer may form a replacement gate structure, 1302, 1304 on one or more the channel layers, 110, where the metal fill layer form the conductive gate electrode, 1306, [0074]),
Though ZHANG teaches the capping layer, 1006, however, the capping layer has been removed before the deposition of the work function metal layer, henceforth, ZHANG as modified by CHING does not disclose the method for manufacturing a semiconductor structure, further comprising: forming a work function metal layer in direct contact with a top surface of the cap layer.
LIN teaches the method for manufacturing a semiconductor structure, further comprising: forming a work function metal layer (Fig. 11, 260, [0039]) in direct contact (Fig. 11, the work function metal layer, 260 is in direct contact with the bottom barrier layers, 240a/240b′, [0032]) with a top surface of the cap layer (Figs. 6/8/11, 240/240b/240b′ bottom barrier layer, [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by CHING to incorporate the teachings of LIN, such that the method for manufacturing a semiconductor, further comprising: forming a work function metal layer in direct contact with a top surface of the cap layer, so that the treated bottom barrier layer, 240b′, contributes the an increase of the effective work function in the region 400, while maintaining the edges of the bottom barrier layers, 240b′, are in coplanar with the work function metal layers, 260 (LIN, Figure 11, [0031], [0034]).
ZHANG as modified by CHING and LIN does not disclose the method for manufacturing a semiconductor structure, further comprising: wherein a first portion of the work function metal layer formed vertically over a topmost structure of the first channel structures has a first thickness, a second portion of the work function metal layer formed vertically over a topmost structure of the second channel structures has a second thickness that is substantially equal to the first thickness.
CHENG teaches the method for manufacturing a semiconductor structure (Fig. 3, the method of forming the semiconductor device structure, [0140]), further comprising: wherein a first portion (Figs. 2M-1/2M-2, 200N/50N, NMOS region/semiconductor device structure, [0091]) of the work function metal layer (Figs. 2M-1/2M-2, 152N, work function material, [0091]) formed vertically (Figs. 2M-1/2M-2, Z axis) over a topmost structure of the first channel structures (Figs. 2M-1/2M-2, 108N, second semiconductor layers, [0091]) has a first thickness (Figs. 2M-1/2M-2, 152N/T5, work function material have a thickness ranging from about 10 Angstroms to about 20 Angstroms, [0093]), a second portion (Figs. 2M-1/2M-2, 200N/50N, NMOS region/semiconductor device structure, [0091]) of the work function metal layer (Figs. 2M-1/2M-2, 152N, work function material, [0091]) formed vertically (Figs. 2M-1/2M-2, Z axis) over a topmost structure of the second channel structures (Figs. 2M-1/2M-2, 108P, second semiconductor layers, [0091]) has a second thickness (Figs. 2M-1/2M-2, 152P/T5, work function material have a thickness ranging from about 10 Angstroms to about 20 Angstroms, [0093]) that is substantially equal to the first thickness (Figs. 2M-1/2M-2, 152N/152P/T5, work function material have a thickness ranging from about 10 Angstroms to about 20 Angstroms, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by CHING and LIN to incorporate the teachings of CHENG, such that the method for manufacturing a semiconductor, further comprising: wherein a first portion of the work function metal layer formed vertically over a topmost structure of the first channel structures has a first thickness, a second portion of the work function metal layer formed vertically over a topmost structure of the second channel structures has a second thickness that is substantially equal to the first thickness, so that the work function materials, 152N and 152P having uniform thickness is used to tune the threshold voltage of the resulting P-type semiconductor device (CHENG, [0093]).
Claim(s) 11-12, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of CHING, and further in view of LAVRIC.
Regarding Claim 11, ZHANG as modified by CHING teaches the method for manufacturing the semiconductor structure as claimed in claim 9.
ZHANG as modified by CHING does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: driving a first metal element of the first dipole layer into the first portion of the first gate dielectric layer; and removing the first dipole layer before forming the second gate dielectric layer.
LAVRIC teaches the method for manufacturing the semiconductor structure (Fig. 3, 300, various operations in a method of fabricating an integrated circuit structure, [0007-0008]), further comprising:
driving a first metal element (Fig. 3(iv), annealing, [0052-0059]) of the first dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) into the first portion (Figs. 3/2, 300, structure, [0052-0059], in a PMOS region, 204) of the first gate dielectric layer (Fig. 3(iii), high-k dielectric layer, [0052-0059]); and
removing the first dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) before forming the second gate dielectric layer (Fig. 3(iv), gate dielectric includes, the high-k dielectric layer on a dipole material layer, 310A, [0052-0059]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by CHING to incorporate the teachings of LAVRIC, such that the method for manufacturing a semiconductor structure, further comprising: driving a first metal element of the first dipole layer into the first portion of the first gate dielectric layer; and removing the first dipole layer before forming the second gate dielectric layer. The gate stack is formed via high temperature anneal during which dipole, 310 diffuses through the underlying high permittivity oxide layer, 308 to for a net dipole, 310A at the high-k, 308/chemical oxide, 304 interface with the process is understood as being effected due to the difference in the electro-negativities of high-k and the chemical oxide layer, and thus the dipole layer used to tune the threshold voltage of the gate stack of fabricating an integrated circuit (LAVRIC, [0051-0059]).
Regarding Claim 12, ZHANG as modified by CHING and LAVRIC teaches the method for manufacturing the semiconductor structure as claimed in claim 11, further comprising:
LAVRIC teaches the method for manufacturing the semiconductor structure (Fig. 3, 300, various operations in a method of fabricating an integrated circuit structure, [0007-0008]), further comprising:
forming a second dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) in physical contact with the second portion (Figs. 3/2, 300, structure, [0052-0059], in a NMOS region, 206) of the first gate dielectric layer (Fig. 3(iii), high-k dielectric layer, [0052-0059]); and
driving a second metal element (Fig. 3(iv), annealing, [0052-0059]) of the second dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) into the second portion (Figs. 3/2, 300, structure, [0052-0059], in a NMOS region, 206) of the first gate dielectric layer (Fig. 3(iii), high-k dielectric layer, [0052-0059]).
Regarding Claim 24, ZHANG as modified by CHING teaches the method for manufacturing the semiconductor structure as claimed in claim 9.
ZHANG as modified by CHING does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: removing the first dipole layer before forming the second gate dielectric layer after the driving of the first metal element of the first dipole layer into the first portion of the first gate dielectric layer.
LAVRIC teaches the method for manufacturing the semiconductor structure (Fig. 3, 300, various operations in a method of fabricating an integrated circuit structure, [0007-0008]), further comprising:
removing the first dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) before forming the second gate dielectric layer (Fig. 3(iv), gate dielectric includes, the high-k dielectric layer on a dipole material layer, 310A, [0052-0059]) after the driving of the first metal element (Fig. 3(iv), annealing, [0052-0059]) of the first dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) into the first portion (Figs. 3/2, 300, structure, [0052-0059], in a PMOS region, 204) of the first gate dielectric layer (Fig. 3(iii), high-k dielectric layer, [0052-0059]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by CHING to incorporate the teachings of LAVRIC, such that the method for manufacturing a semiconductor structure, further comprising: removing the first dipole layer before forming the second gate dielectric layer after the driving of the first metal element of the first dipole layer into the first portion of the first gate dielectric layer. The gate stack is formed via high temperature anneal during which dipole, 310 diffuses through the underlying high permittivity oxide layer, 308 to for a net dipole, 310A at the high-k, 308/chemical oxide, 304 interface with the process is understood as being effected due to the difference in the electro-negativities of high-k and the chemical oxide layer, and thus the dipole layer used to tune the threshold voltage of the gate stack of fabricating an integrated circuit (LAVRIC, [0051-0059]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of CHING, and further in view of Jisong Jin et al, (hereinafter JIN), US 20220328642 A1.
Regarding Claim 13, ZHANG as modified by CHING teaches the method for manufacturing the semiconductor structure as claimed in claim 9.
ZHANG as modified by CHING does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: forming a dielectric wall structure laterally interposing the first channel structures and the second channel structures, wherein the first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure, and the second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure that is opposite to the first sidewall.
JIN teaches the method for manufacturing the semiconductor structure (Fig. 4, forming a method of a semiconductor structure, [0018]), further comprising: forming a dielectric wall structure (Fig. 2, 140) laterally interposing the first channel structures (Fig. 2, 120/130, channel structure layers/channel layers on I(a) side from the dielectric wall, 140, [0027]) and the second channel structures (Fig. 2, 120/130, channel structure layers/channel layers on I(b) side from the dielectric wall, 140, [0027]), wherein the first portion of the first gate dielectric layer (Fig. 2, 310, gate dielectric layer on I(a) side from the dielectric wall, 140, [0027]) is in direct contact with a first sidewall of the dielectric wall structure (Fig. 2, 42, dielectric wall protrusion on I(a) side from the dielectric wall, [0027]), and the second portion of the first gate dielectric layer (Fig. 2, 310, gate dielectric layer on I(a) side from the dielectric wall, 140, [0027]) is in direct contact with a second sidewall of the dielectric wall structure (Fig. 2, 42, dielectric wall protrusion on I(a) side from the dielectric wall, [0027]) that is opposite to the first sidewall (Fig. 2, I(a)/I(b)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by CHING to incorporate the teachings of JIN, such that the method for manufacturing a semiconductor structure, further comprising: forming a dielectric wall structure laterally interposing the first channel structures and the second channel structures, wherein the first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure, and the second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure that is opposite to the first sidewall. The said arrangement is a new architecture which is referred to as a Forksheet or fork-shaped gate transistor device having a dielectric wall is introduced between an nFET device and a pFET device, further causes smaller spacing between the nFET device and the pFET device in a standard cell, so that Forksheet has better scalability in areas and performance (JIN, [0005]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of CHING, and further in view of JUN.
Regarding Claim 14, ZHANG as modified by CHING teaches the method for manufacturing the semiconductor structure as claimed in claim 9.
ZHANG further teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), further comprising:
patterning (Figs. 1/1A, [0037], [0047]) the first semiconductor stack (Fig. 1A, 106, nanosheet stack, [0047]) and the second semiconductor stack (Fig. 1A, 104, nanosheet stack, [0047]) to form a fin structure (Fig. 1A, pFET/nFET, [0047]);
removing the first semiconductor material layers (Fig. 1A, 108, sacrificial layers, [0039]) of the first semiconductor stack (Fig. 1A, 104, nanosheet stack, [0047]) to form the first channel structures (Fig. 3, 110, the channel layers in the nanosheet stack, 104, [0052]) with the second semiconductor material layers (Fig. 1A, 110, channel layers, [0052]) of the first semiconductor stack (Fig. 1A, 104, nanosheet stack, [0047]); and
removing the first semiconductor material layers (Fig. 1A, 108, sacrificial layers, [0039]) of the second semiconductor stack (Fig. 1A, 106, nanosheet stack, [0047]) to form the second channel structures (Fig. 3, 110, the channel layers in the nanosheet stack, 106, [0052]) with the second semiconductor material layers (Fig. 1A, 110, channel layers, [0052]) of the second semiconductor stack (Fig. 1A, 106, nanosheet stack, [0047]).
ZHANG as modified by CHING does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: the method for manufacturing the semiconductor structure, further comprising: forming a first semiconductor stack over the substrate and a second semiconductor stack over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack comprises first semiconductor material layers and second semiconductor material layers alternately stacked; wherein the first portion of the first gate dielectric layer vertically overlaps the second portion of the first gate dielectric layer.
JUN teaches the method for manufacturing the semiconductor structure (Fig. 4A, 400, semiconductor device, methods of manufacturing the multi-stack nanosheet structure, [0008]), further comprising:
forming a first semiconductor stack (Fig. 4A, 410, 1st nanosheet stack, [0065]) over the substrate (Fig. 4A, 405) and a second semiconductor stack (Fig. 4A, 420, 2nd nanosheet stack, [0065]) over the first semiconductor stack (Fig. 4A, 410, 1st nanosheet stack, [0065]), wherein each of the first semiconductor stack (Fig. 4A, 410, 1st nanosheet stack, [0065]) and the second semiconductor stack (Fig. 4A, 420, 2nd nanosheet stack, [0065]) comprises first semiconductor material layers (Fig. 4A, 410C/410S, 1st nanosheet layer/1st sacrificial layer, [0062]) and second semiconductor material layers (Fig. 4A, 420C/420S, 2nd nanosheet layer/2nd sacrificial layer, [0062]) alternately stacked;
wherein the first portion of the first gate dielectric layer (Fig. 3A, 315, 1st gate structure of 310, nanosheet layer stack, [0050]) vertically overlaps the second portion (Fig. 3A, 325, 2nd gate structure of 320, nanosheet layer stack, [0050]) of the first gate dielectric layer (Fig. 3A, 315, 1st gate structure of 310, nanosheet layer stack, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by CHING to incorporate the teachings of JUN, such that the method for manufacturing the semiconductor structure, further comprising: forming a first semiconductor stack over the substrate and a second semiconductor stack over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack comprises first semiconductor material layers and second semiconductor material layers alternately stacked; wherein the first portion of the first gate dielectric layer vertically overlaps the second portion of the first gate dielectric layer, so that the nanosheet layers function as multiple channels for current flow between the source/drain regions of the nanosheet transistor, and due to this structure, improved control of current flow through the multiple channels is enabled in addition to higher device density in a semiconductor device including the nanosheet transistor (JUN, [0003]).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of LIN.
Regarding Claim 21, ZHANG teaches a method for manufacturing a semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), comprising:
forming a first type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]) and a second type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]) over a substrate (Figs. 1A/13A, 102);
forming first channel structures (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) vertically suspended over the substrate (Figs. 1A/13A, 102) and sandwiched between the first type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]);
forming second channel structures (Fig. 1A, 110, channel layer in the 106, second nanosheet stack) vertically suspended over the substrate (Figs. 1A/13A, 102) and sandwiched between the second type of source/drain structures (Figs. 13A/1A, 1310/1320, on both sides 110, channel layer in the 104, first nanosheet stack, [0056]);
forming a first gate dielectric layer (Fig. 4, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]) having a first portion (Fig. 4, 402 in the 104, first nanosheet stack) wrapping around the first channel structures (Fig. 1A, 110, channel layer in the 104, first nanosheet stack) and a second portion (Fig. 4, 402 in the 106, second nanosheet stack) wrapping around the second channel structures (Fig. 1A, 110, channel layer in the 106, second nanosheet stack);
forming a first dipole layer (Fig. 14, 1408; Fig. 10, 1002, dipole layer formation and contacts the dielectric layer, 404 of the dipole diffusion in the first nanosheet stack(s), 104, [0067-0069]) in physical contact with the first portion of the first gate dielectric layer (Figs. 7/10, 402, gate dielectric layer in the 104, first nanosheet stack) and spaced apart from the second portion of the first gate dielectric layer (Figs. 7/10, 402, gate dielectric layer in the 106, second nanosheet stack);
driving a first metal element (Fig. 14, 1408; Fig. 10, 1002, dipole layer formation and contacts the dielectric layer, 404 of the dipole diffusion in the first nanosheet stack(s), 104, [0067-0069]) into the first portion of the first gate dielectric layer (Figs. 7/10, 402, gate dielectric layer in the 104, first nanosheet stack);
forming a second gate dielectric layer (Fig. 10, 404, dielectric layer, [0060]) over the first gate dielectric layer (Figs. 4/10, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]), wherein the first gate dielectric layer (Figs. 4/10, 402, Interfacial layer or IL may comprise silicon oxide, oxynitride or other suitable materials, [0056]) and the second gate dielectric layer (Fig. 10, 404, dielectric layer, [0060]) are made of a same dielectric material (silicon oxide, oxynitride or other suitable materials, [0056], [0061], [0002]);
forming a cap layer wrapping around the first channel structures and the second channel structures over the second gate dielectric layer;
forming a cap layer (Fig. 10, 1006, capping layer) wrapping around the first channel structures (Figs. 7/10, 1006, capping layer in the 104, first nanosheet stack) and the second channel structures (Figs. 7/10, 1006, capping layer in the 106, second nanosheet stack) over the second gate dielectric layer Fig. 10, 404, dielectric layer, [0060]); and
forming a work function metal layer (Figs. 13/13A, a work function setting metal layer (not shown) may be deposited onto the gate dielectric layer 1202, [0072] ; optionally, the work function layer may form a replacement gate structure, 1302, 1304 on one or more the channel layers, 110, [0074]); and
forming a gate filling layer a conductive gate electrode in direct contact with a top surface of the work function metal layer (Fig. 13A, optionally, the work function layer may form a replacement gate structure, 1302, 1304 on one or more the channel layers, 110, where the metal fill layer form the conductive gate electrode, 1306, [0074]).
Though ZHANG teaches the capping layer, 1006, however, the capping layer has been removed before the deposition of the work function metal layer, henceforth, ZHANG does not disclose a method for manufacturing a semiconductor structure, comprising: forming a work function metal layer in direct contact with a top surface of the cap layer.
LIN teaches a method for manufacturing a semiconductor structure, comprising: forming a work function metal layer (Fig. 11, 260, [0039]) in direct contact (Fig. 11, the work function metal layer, 260 is in direct contact with the bottom barrier layers, 240a/240b′, [0032]) with a top surface of the cap layer (Figs. 6/8/11, 240/240b/240b′ bottom barrier layer, [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG to incorporate the teachings of LIN, such that a method for manufacturing a semiconductor, comprising: forming a work function metal layer in direct contact with a top surface of the cap layer, so that the treated bottom barrier layer, 240b′, contributes the an increase of the effective work function in the region 400, while maintaining the edges of the bottom barrier layers, 240b′, are in coplanar with the work function metal layers, 260 (LIN, Figure 11, [0031], [0034]).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of LIN, and further in view of LAVRIC.
Regarding Claim 22, ZHANG as modified by LIN teaches the method for manufacturing the semiconductor structure as claimed in claim 21.
ZHANG as modified by LIN does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: forming a second dipole layer in physical contact with the second portion of the first gate dielectric layer; and driving a second metal element of the second dipole layer into the second portion of the first gate dielectric layer.
LAVRIC teaches the method for manufacturing the semiconductor structure (Fig. 3, 300, various operations in a method of fabricating an integrated circuit structure, [0007-0008]), further comprising:
forming a second dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) in physical contact with the second portion (Figs. 3/2, 300, structure, [0052-0059], in a NMOS region, 206) of the first gate dielectric layer (Fig. 3(iii), high-k dielectric layer, [0052-0059]); and
driving a second metal element (Fig. 3(iv), annealing, [0052-0059]) of the second dipole layer (Fig. 3(iii), 310, the material layer, [0052-0059]) into the second portion (Figs. 3/2, 300, structure, [0052-0059], in a NMOS region, 206) of the first gate dielectric layer (Fig. 3(iii), high-k dielectric layer, [0052-0059]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHANG as modified by LIN to incorporate the teachings of LAVRIC, such that a method for manufacturing a semiconductor structure, further comprising: forming a second dipole layer in physical contact with the second portion of the first gate dielectric layer; and driving a second metal element of the second dipole layer into the second portion of the first gate dielectric layer, so that the dipoles can be used to set the threshold voltage (VT) and to enable relative thinning of workfunction metal layers and to provide a multi-VT solution and also provide ultra-low VT with a relatively thinner workfunction metal (LAVRIC, [0027]).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of LIN, and further in view of CHENG.
Regarding Claim 23, ZHANG as modified by LIN teaches the method for manufacturing the semiconductor structure as claimed in claim 21.
ZHANG as modified by LIN does not disclose the method for manufacturing the semiconductor structure, wherein a first portion of the work function metal layer formed vertically over a topmost structure of the first channel structures has a first thickness, a second portion of the work function metal layer formed vertically over a topmost structure of the second channel structures has a second thickness that is substantially equal to the first thickness.
CHENG teaches the method for manufacturing a semiconductor structure (Fig. 3, the method of forming the semiconductor device structure, [0140]), further comprising: wherein a first portion (Figs. 2M-1/2M-2, 200N/50N, NMOS region/semiconductor device structure, [0091]) of the work function metal layer (Figs. 2M-1/2M-2, 152N, work function material, [0091]) formed vertically (Figs. 2M-1/2M-2, Z axis) over a topmost structure of the first channel structures (Figs. 2M-1/2M-2, 108N, second semiconductor layers, [0091]) has a first thickness (Figs. 2M-1/2M-2, 152N/T5, work function material have a thickness ranging from about 10 Angstroms to about 20 Angstroms, [0093]), a second portion (Figs. 2M-1/2M-2, 200N/50N, NMOS region/semiconductor device structure, [0091]) of the work function metal layer (Figs. 2M-1/2M-2, 152N, work function material, [0091]) formed vertically (Figs. 2M-1/2M-2, Z axis) over a topmost structure of the second channel structures (Figs. 2M-1/2M-2, 108P, second semiconductor layers, [0091]) has a second thickness (Figs. 2M-1/2M-2, 152P/T5, work function material have a thickness ranging from about 10 Angstroms to about 20 Angstroms, [0093]) that is substantially equal to the first thickness (Figs. 2M-1/2M-2, 152N/152P/T5, work function material have a thickness ranging from about 10 Angstroms to about 20 Angstroms, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by LIN to incorporate the teachings of CHENG, such that the method for manufacturing a semiconductor, further comprising: wherein a first portion of the work function metal layer formed vertically over a topmost structure of the first channel structures has a first thickness, a second portion of the work function metal layer formed vertically over a topmost structure of the second channel structures has a second thickness that is substantially equal to the first thickness, so that the work function materials, 152N and 152P having uniform thickness is used to tune the threshold voltage of the resulting P-type semiconductor device (CHENG, [0093]).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of LIN, and further in view of JIN.
Regarding Claim 25, ZHANG as modified by LIN teaches the method for manufacturing the semiconductor structure as claimed in claim 21.
ZHANG as modified by LIN the method for manufacturing the semiconductor structure, further comprising: forming a dielectric wall structure laterally interposing the first channel structures and the second channel structures, wherein the first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure, and the second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure that is opposite to the first sidewall.
JIN teaches the method for manufacturing the semiconductor structure (Fig. 4, forming a method of a semiconductor structure, [0018]), further comprising: forming a dielectric wall structure (Fig. 2, 140) laterally interposing the first channel structures (Fig. 2, 120/130, channel structure layers/channel layers on I(a) side from the dielectric wall, 140, [0027]) and the second channel structures (Fig. 2, 120/130, channel structure layers/channel layers on I(b) side from the dielectric wall, 140, [0027]), wherein the first portion of the first gate dielectric layer (Fig. 2, 310, gate dielectric layer on I(a) side from the dielectric wall, 140, [0027]) is in direct contact with a first sidewall of the dielectric wall structure (Fig. 2, 42, dielectric wall protrusion on I(a) side from the dielectric wall, [0027]), and the second portion of the first gate dielectric layer (Fig. 2, 310, gate dielectric layer on I(a) side from the dielectric wall, 140, [0027]) is in direct contact with a second sidewall of the dielectric wall structure (Fig. 2, 42, dielectric wall protrusion on I(a) side from the dielectric wall, [0027]) that is opposite to the first sidewall (Fig. 2, I(a)/I(b)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by LIN to incorporate the teachings of JIN, such that the method for manufacturing a semiconductor structure, further comprising: forming a dielectric wall structure laterally interposing the first channel structures and the second channel structures, wherein the first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure, and the second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure that is opposite to the first sidewall. The said arrangement is a new architecture which is referred to as a Forksheet or fork-shaped gate transistor device having a dielectric wall is introduced between an nFET device and a pFET device, further causes smaller spacing between the nFET device and the pFET device in a standard cell, so that Forksheet has better scalability in areas and performance (JIN, [0005]).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG, in view of LIN, and further in view of JUN.
Regarding Claim 26, ZHANG as modified by LIN teaches the method for manufacturing the semiconductor structure as claimed in claim 21.
ZHANG further teaches the method for manufacturing the semiconductor structure (Fig. 1A, 100, a method of forming a semiconductor device, [0005]), further comprising:
patterning (Figs. 1/1A, [0037], [0047]) the first semiconductor stack (Fig. 1A, 106, nanosheet stack, [0047]) and the second semiconductor stack (Fig. 1A, 104, nanosheet stack, [0047]) to form a fin structure (Fig. 1A, pFET/nFET, [0047]);
removing the first semiconductor material layers (Fig. 1A, 108, sacrificial layers, [0039]) of the first semiconductor stack (Fig. 1A, 104, nanosheet stack, [0047]) to form the first channel structures (Fig. 3, 110, the channel layers in the nanosheet stack, 104, [0052]) with the second semiconductor material layers (Fig. 1A, 110, channel layers, [0052]) of the first semiconductor stack (Fig. 1A, 104, nanosheet stack, [0047]); and
removing the first semiconductor material layers (Fig. 1A, 108, sacrificial layers, [0039]) of the second semiconductor stack (Fig. 1A, 106, nanosheet stack, [0047]) to form the second channel structures (Fig. 3, 110, the channel layers in the nanosheet stack, 106, [0052]) with the second semiconductor material layers (Fig. 1A, 110, channel layers, [0052]) of the second semiconductor stack (Fig. 1A, 106, nanosheet stack, [0047]).
ZHANG as modified by LIN does not explicitly disclose the method for manufacturing the semiconductor structure, further comprising: the method for manufacturing the semiconductor structure, further comprising: forming a first semiconductor stack over the substrate and a second semiconductor stack over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack comprises first semiconductor material layers and second semiconductor material layers alternately stacked; wherein the first portion of the first gate dielectric layer vertically overlaps the second portion of the first gate dielectric layer.
JUN teaches the method for manufacturing the semiconductor structure (Fig. 4A, 400, semiconductor device, methods of manufacturing the multi-stack nanosheet structure, [0008]), further comprising:
forming a first semiconductor stack (Fig. 4A, 410, 1st nanosheet stack, [0065]) over the substrate (Fig. 4A, 405) and a second semiconductor stack (Fig. 4A, 420, 2nd nanosheet stack, [0065]) over the first semiconductor stack (Fig. 4A, 410, 1st nanosheet stack, [0065]), wherein each of the first semiconductor stack (Fig. 4A, 410, 1st nanosheet stack, [0065]) and the second semiconductor stack (Fig. 4A, 420, 2nd nanosheet stack, [0065]) comprises first semiconductor material layers (Fig. 4A, 410C/410S, 1st nanosheet layer/1st sacrificial layer, [0062]) and second semiconductor material layers (Fig. 4A, 420C/420S, 2nd nanosheet layer/2nd sacrificial layer, [0062]) alternately stacked;
wherein the first portion of the first gate dielectric layer (Fig. 3A, 315, 1st gate structure of 310, nanosheet layer stack, [0050]) vertically overlaps the second portion (Fig. 3A, 325, 2nd gate structure of 320, nanosheet layer stack, [0050]) of the first gate dielectric layer (Fig. 3A, 315, 1st gate structure of 310, nanosheet layer stack, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHANG as modified by LIN to incorporate the teachings of JUN, such that the method for manufacturing the semiconductor structure, further comprising: forming a first semiconductor stack over the substrate and a second semiconductor stack over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack comprises first semiconductor material layers and second semiconductor material layers alternately stacked; wherein the first portion of the first gate dielectric layer vertically overlaps the second portion of the first gate dielectric layer, so that the nanosheet layers function as multiple channels for current flow between the source/drain regions of the nanosheet transistor, and due to this structure, improved control of current flow through the multiple channels is enabled in addition to higher device density in a semiconductor device including the nanosheet transistor (JUN, [0003]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210265496 A1 – Figure 1
STATEMENT OF RELEVANCE – Flowchart illustrating a method of forming a semiconductor device.
US 20160104705 A1 – Figure 2
STATEMENT OF RELEVANCE – Thickness variation of gate dielectric layers between first portion and second portion of the semiconductor device, 100.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812