Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 12/29/2025 has been entered. Claim 10 is amended. Claims 1 – 20 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 9, 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Haran ( Pub. No. US 20210305361 A1 ), hereinafter Haran, in view of Haran.
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Regarding Independent Claim 1 ( Previously Presented ), Haran teaches a semiconductor structure, comprising:
a first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) positioned over a substrate ( Haran, FIG. 1, 104; [0033], substrate 104 ), wherein the first stack structure comprises a plurality of nanostructures ( Haran, FIG. 1, 106; [0033], semiconductor layers 106 ) that extend along a first direction ( Haran, FIG. 1, X direction );
a second stack structure ( Haran, FIG. 1, 102, above the one labeled by X; [0033], nanosheet stacks 102 ) adjacent the first stack structure, wherein the second stack structure comprises a plurality of nanostructures ( Haran, FIG. 1, 106; [0033], semiconductor layers 106 ) that extend along the first direction ( Haran, FIG. 1, X direction );
a first gate structure ( Haran, FIG. 1, 110, where is “ crossed by X and Y3 ” and “ above 106 ”; FIG. 8, 802/804; [0036], topmost sacrificial layer 110; [0065], gates 802 and 804 ) formed over the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ), wherein the first gate structure ( Haran, FIG. 1, 110, where is “ crossed by X and Y3 ” and “ above 106 ”; FIG. 8, 802/804; [0036], topmost sacrificial layer 110; [0065], gates 802 and 804 ) extends along a second direction ( Haran, FIG. 1, Y3 direction ); and
a dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) between the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) and the second stack structure ( Haran, FIG. 1, 102, above the one labeled by X ), wherein the dielectric wall comprises a low-k dielectric ( Haran, [0039], shallow trench isolation region 112 … trench can then be filled with dielectric material, such as, a low-k dielectric; [0056], isolation dielectric 306 can be made of any suitable dielectric material, such as, for example, oxides, a low-k dielectric ) material, and the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) has a first sidewall ( Haran, FIG. 10, 602, when b is closer to 0 ) with a sidewall of at least one of the plurality of nanostructures of the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) and a second sidewall ( Haran, FIG. 10, 602, when b is closer to 0 ) with a sidewall of at least one of the plurality of nanostructures of the second stack structure ( Haran, FIG. 1, 102, above the one labeled by X ); and
an isolation structure ( Haran, FIG. 10, 112; FIG. 3, 112; [0039], shallow trench isolation region 112 … The trench can then be filled with dielectric material, such as, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ) adjacent the first stack structure ( Haran, FIG. 1, 102, labeled by X ), wherein:
the first stack structure ( Haran, FIG. 1, 102, labeled by X ) is between the dielectric wall and the isolation structure;
the isolation structure ( Haran, FIG. 10, 112; FIG. 3, 112 ) and the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112 ) are portions of a same material layer;
the isolation structure ( Haran, FIG. 10, 112; FIG. 3, 112 ) extends from a first depth in the substrate to a first height below ( Haran, FIG.10, top surface of 112 below semiconductor layers 106 ) the first stack structure ( Haran, FIG. 1, 102, labeled by X ); and
the dielectric wall ( Haran, FIG. 10, 602 ) includes a single, continuous layer of the low-k dielectric material extending from the first depth to a second height above ( Haran, FIG.10, top surface of 602 above semiconductor layers 106 ) the first stack structure ( Haran, FIG. 1, 102, labeled by X ).
Haran did not explicitly disclose that the dielectric wall has a first sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the first stack structure and a second sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the second stack structure;
However, Haran disclosed that in FIG. 10 silicon nanosheets 106 ( i.e. channel ) is all around ( i.e. gate-all-around, GAA ) by metal gates 802 and 804, therefore there is distance b between isolation structure 602 and channel silicon nanosheets 106;
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use FinFET to replace GAA in Haran FIG. 10, and therefore to have the distance b between isolation structure 602 and channel silicon nanosheets 106 to be 0, which means that the dielectric wall has a first sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the first stack structure and a second sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the second stack structure, since this is within the skill level of one in the art.
Regarding Claim 2 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 1, on which this claim is dependent, Haran further teaches: comprising:
a first source/drain (S/D) structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ) formed adjacent to the first gate structure ( Haran, FIG. 1, 110, where is “ crossed by X and Y3 ” and “ above 106 ”; FIG. 8, 802/804; [0036], topmost sacrificial layer 110; [0065], gates 802 and 804 ), wherein the first S/D structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ) is connected to the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ).
Regarding Claim 3 ( Original ), Haran teaches the semiconductor structure as claimed in claim 2, on which this claim is dependent, Haran further teaches:
wherein the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) has a first portion ( FIG. 8, FIG. 10, 602; [0061], isolation structure 602 ) directly below the first gate structure ( Haran, FIG. 1, 110, where is “ crossed by X and Y3 ” and “ above 106 ”; FIG. 8, 802/804; [0036], topmost sacrificial layer 110; [0065], gates 802 and 804 ) and a second portion ( Haran, FIG. 3, 306 between 304; [0056], isolation dielectric 306; [0051], source and drain regions 304 ) adjacent to the first S/D structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ), the first portion ( FIG. 8, FIG. 10, 602; [0061], isolation structure 602 ) has a first width along the second direction, the second portion ( Haran, FIG. 3, 306 between 304; [0056], isolation dielectric 306; [0051], source and drain regions 304 ) has a second width along the second direction, and the second width ( Haran, FIG. 3, 306 between 304; [0056], isolation dielectric 306; [0051], source and drain regions 304 ) is smaller than the first width (FIG. 8, FIG. 10, 602; [0061], isolation structure 602).
Regarding Claim 4 ( Original ), Haran teaches the semiconductor structure as claimed in claim 3, on which this claim is dependent, Haran further teaches:
wherein the first portion ( FIG. 8, FIG. 10, 602; [0061], isolation structure 602 ) has a first height along a vertical direction, the second portion ( Haran, FIG. 3, 306 between 304; [0056], isolation dielectric 306; [0051], source and drain regions 304 ) has a second height along the vertical direction, and the first height ( FIG. 8, FIG. 10, 602; [0061], isolation structure 602 ) is greater than the second height ( Haran, FIG. 3, 306 between 304; [0056], isolation dielectric 306; [0051], source and drain regions 304 ).
Regarding Claim 5 ( Original ), Haran teaches the semiconductor structure as claimed in claim 1, on which this claim is dependent, Haran further teaches:
wherein a bottom surface ( Haran, FIG. 3, 306 between 304, 112; [0039], shallow trench isolation region 112 ) of the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304; [0039], shallow trench isolation region 112 ) is lower than a bottom surface of the first S/D structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ).
Regarding Claim 6 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 1, on which this claim is dependent, Haran further teaches: comprising:
a cap layer ( Haran, FIG. 8, 602; [0061], isolation structure 602; FIG. 10, 1002; [0077], conductive structure 1002; FIG. 10, 1004; FIG. 8, 602; [0077], gate hard mask 1004; [0061], isolation structure 602 … In some embodiments of the invention, the isolation structure 602 includes silicon nitride ) formed over the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ), wherein the cap layer ( Haran, FIG. 8, 602; [0061], isolation structure 602; FIG. 10, 1002; [0077], conductive structure 1002; FIG. 10, 1004; FIG. 8, 602; [0077], gate hard mask 1004; [0061], isolation structure 602 ) comprises a high-k dielectric material ( Haran, [0077], The gate hard masks 1004 can be made of any suitable material, such as, for example, silicon nitride. In some embodiments of the invention, the gate hard masks 1004 are formed by recessing the gates 802 and 804 and the conductive structure 1002, exposing sidewalls of the isolation structure 602 (Y3 cross-section). The gate hard masks 1004 can then be formed or deposited on the recessed surfaced of the gates 802 and 804 ).
Regarding Claim 7 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 1, on which this claim is dependent, Haran further teaches: comprising:
an isolation structure ( Haran, FIG. 3, 112; [0039], shallow trench isolation region 112 … The trench can then be filled with dielectric material, such as, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ) formed over the substrate ( Haran, FIG. 1, 104; [0033], substrate 104 ), wherein the isolation structure ( Haran, FIG. 3, 112; [0039], shallow trench isolation region 112 ) and the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306 … isolation dielectric 306 can be made of any suitable dielectric material, such as, for example, oxides, a low-k dielectric, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) are made of the same material.
Regarding Claim 8 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 1, on which this claim is dependent, Haran further teaches: comprising:
a spacer layer ( Haran, FIG. 3, 202; [0047], spacers 202 ) adjacent to the first S/D structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ), wherein a top surface of the dielectric wall ( Haran, FIG. 8, 602; [0061], isolation structure 602 ) is higher than a top surface of the spacer layer ( Haran, FIG. 3, 202; [0047], spacers 202 ).
Regarding Claim 9 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 1, on which this claim is dependent, Haran further teaches: comprising:
a liner layer ( Haran, FIG. 3, 202; [0047], spacers 202 ) formed on sidewalls of the dielectric wall ( Haran, FIG. 3, 306 between 304; [0056], isolation dielectric 306; [0051], source and drain regions 304 ).
Regarding Independent Claim 18 ( Previously Presented ), Haran teaches a method for forming a semiconductor structure, comprising:
forming a first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) and a second stack structure ( Haran, FIG. 1, 102, above the one labeled by X; [0033], nanosheet stacks 102 ) over a substrate ( Haran, FIG. 1, 104; [0033], substrate 104 );
forming a dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) between the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) and the second stack structure ( Haran, FIG. 1, 102, above the one labeled by X; [0033], nanosheet stacks 102 ), wherein the dielectric wall comprises a low-k dielectric material ( Haran, [0039], shallow trench isolation region 112 … trench can then be filled with dielectric material, such as, a low-k dielectric; [0056], isolation dielectric 306 can be made of any suitable dielectric material, such as, for example, oxides, a low-k dielectric );
removing a portion ( Haran, FIG. 2 to FIG. 3, 102 is removed a portion; [0033], nanosheet stacks 102 ) of the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) to form a recess ( Haran, FIG. 2 to FIG. 3, 304; [0051], source and drain regions 304 );
forming an S/D structure ( Haran, FIG. 2 to FIG. 3, 304; [0051], source and drain regions 304 ) in the recess ( Haran, FIG. 2 to FIG. 3, 304; [0051], source and drain regions 304 ), wherein a sidewall of the S/D structure is contiguous with a sidewall of the dielectric wall ( Haran, [0047], As further shown in FIG. 2, in some embodiments of the invention, spacers 202 (also known as sidewall spacers or gate spacers) are formed on sidewalls of the sacrificial gates 118; [0048] The spacers 202 can be made of any suitable material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the invention, the spacers 202 include silicon nitride. The spacers 202 can be formed to a thickness of about 5 to 40 nm, although other thicknesses are within the contemplated scope of the invention ); and
removing a portion ( Haran, FIG. 2 to FIG. 3, 102 is removed a portion; [0033], nanosheet stacks 102 ) of the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) to form a plurality of nanostructures ( Haran, FIG. 2 to FIG. 3, 102 is maintained a portion; [0033], nanosheet stacks 102 ), wherein at least one of the plurality of nanostructures ( Haran, FIG. 2 to FIG. 3, 102 is maintained a portion; [0033], nanosheet stacks 102 ) has a sidewall ( Haran, FIG. 10, 602, when b is closer to 0 ) with the sidewall of the dielectric wall ( Haran, FIG. 1, along Y3, between 102; FIG. 10, 602; [0061], isolation structure 602 ).
Haran did not explicitly disclose that wherein at least one of the plurality of nanostructures has a sidewall contiguous with the sidewall of the dielectric wall.
However, Haran disclosed that in FIG. 10 silicon nanosheets 106 ( i.e. channel ) is all around ( i.e. gate-all-around, GAA ) by metal gates 802 and 804, therefore there is distance b between isolation structure 602 and channel silicon nanosheets 106;
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use FinFET to replace GAA in Haran FIG. 10, and therefore to have the distance b between isolation structure 602 and channel silicon nanosheets 106 to be 0, which means that wherein at least one of the plurality of nanostructures has a sidewall contiguous with the sidewall of the dielectric wall, since this is within the skill level of one in the art.
Regarding Claim 19 ( Previously Presented ), Haran teaches the method for forming the semiconductor structure as claimed in claim 17, on which this claim is dependent, Haran further teaches: comprising:
removing a portion ( Haran, FIG. 2 to FIG. 3, 102 is removed a portion; [0033], nanosheet stacks 102; FIG. 3, 114; sacrificial spacer 114 ) of the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ), such that the dielectric wall has a bottom portion ( Haran, FIG. 3, 112; FIG. 10, 112 ) and a top portion ( Haran, FIG. 3, 306 between 304; FIG. 10, 602 ), and the bottom portion ( Haran, FIG. 3, 112; FIG. 10, 112 ) is wider than the top portion ( Haran, FIG. 3, 306 between 304; FIG. 10, 602 ).
Regarding Claim 20 ( Previously Presented ), Haran teaches the method for forming the semiconductor structure as claimed in claim 17, on which this claim is dependent, Haran further teaches: comprising:
simultaneously forming an isolation structure ( Haran, FIG. 3, 306; [0056], isolation dielectric 306; FIG. 10, 112, 602 ) when forming the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; FIG. 10, 112, 602, 1004 ) between the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) and the second stack structure ( Haran, FIG. 1, 102, above the one labeled by X; [0033], nanosheet stacks 102 ), wherein forming the isolation structure ( Haran, FIG. 3, 306; FIG. 10, 112, 602 ) when forming the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 112, 602, 1004 ) comprises:
forming a first opening ( Haran, FIG. 1, along Y2, the opening above 112 and between 106 on the left and 106 on the right; FIG. 5, 504; FIG. 6, 602; FIG. 9, 602 ) between the first stack structure and the second stack structure;
forming a second opening ( Haran, FIG. 2, along Y2, the opening above 110; FIG. 9, the opening between 904 on the left and 904 on the right ) adjacent the first stack structure such that the first stack structure is between the first opening and the second opening;
depositing the low-k dielectric material ( Haran, FIG. 3, 306; [0056], isolation dielectric 306; FIG.6, 602 ) in the first opening and the second opening to a first height above the first stack structure;
forming a mask ( Haran, FIG.9, 904; [0074], mask 904 ) protecting a first portion ( Haran, FIG. 9, 602 ) of the low-k dielectric material in the first opening and exposing a second portion( Haran, FIG. 9, 902 ) of the low-k dielectric material in the second opening ( Haran, FIG. 9, the opening between 904 on the left and 904 on the right ); and
recessing ( Haran, FIG. 9, 902; [0074], As shown in FIG. 9, portions of the isolation structure 602 can be recessed to form a cavity 902 ) the second portion of the low-k dielectric material in the second opening through the mask, yielding the isolation structure ( Haran, FIG. 10, 112, 602 ).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10 – 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haran.
Regarding Independent Claim 10 ( Currently Amended ), Haran teaches a semiconductor structure, comprising:
a gate structure ( Haran, FIG. 1, 110, where is “ crossed by X and Y3 ” and “ above 106 ”; FIG. 8, 802/804; [0036], topmost sacrificial layer 110; [0065], gates 802 and 804 ) formed over a substrate ( Haran, FIG. 1, 104; [0033], substrate 104 );
a first source/drain (S/D) structure ( Haran, FIG. 1, where is “ crossed by X and Y2 ”; FIG. 3, 304; [0051], source and drain regions 304 ) formed adjacent to the gate structure ( Haran, FIG. 1, 110, where is “ crossed by X and Y3 ” and “ above 106 ”; FIG. 8, 802/804; [0036], topmost sacrificial layer 110; [0065], gates 802 and 804 );
a second S/D structure ( Haran, FIG. 1, where is “ crossed by upper 102 and Y2 ”; FIG. 3, 304; [0051], source and drain regions 304 ) adjacent to the first S/D structure; and
a dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) between the first S/D structure ( Haran, FIG. 1, where is “ crossed by X and Y2 ”; FIG. 3, 304; [0051], source and drain regions 304 ) and the second S/D structure ( Haran, FIG. 1, where is “ crossed by upper 102 and Y2 ”; FIG. 3, 304; [0051], source and drain regions 304 ) and underlying the gate structure ( Haran, FIG. 1, 110, where is “ crossed by X and Y3 ” and “ above 106 ”; FIG. 8, 802/804; [0036], topmost sacrificial layer 110; [0065], gates 802 and 804; FIG. 10, 1002; [0077], conductive structure 1002 ), wherein the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304; [0039], shallow trench isolation region 112 ) comprises a low-k dielectric material ( Haran, [0039], shallow trench isolation region 112 … trench can then be filled with dielectric material, such as, a low-k dielectric; [0056], isolation dielectric 306 can be made of any suitable dielectric material, such as, for example, oxides, a low-k dielectric ), a bottom surface ( Haran, FIG. 3, 306 between 304, 112; [0039], shallow trench isolation region 112 ) of the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304; [0039], shallow trench isolation region 112 ) is lower than a bottom surface of the first S/D structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ); and
a cap layer ( Haran, FIG. 8, 602; [0061], isolation structure 602; FIG. 10, 1002; [0077], conductive structure 1002 ) overlying the dielectric wall ( Haran, FIG. 10, 602 ) and having a sidewall contiguous with a sidewall of the gate structure ( Haran, FIG. 10, gates 802 and 804 ), the cap layer ( Haran, FIG. 8, isolation structure 602; [0061], The isolation structure 602 can be made of any suitable dielectric material, such as, for example, … a nitride, silicon nitride, … In some embodiments of the invention, the isolation structure 602 includes silicon nitride ) comprising a different dielectric material than the low-k dielectric material of the dielectric wall ( Haran, FIG. 8, FIG. 10, 116; [0041], The liner 116 can be made of any suitable material, such as, for example, a low-k dielectric or an oxide (e.g., SiO.sub.2) ).
Regarding Claim 11 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 10, on which this claim is dependent, Haran further teaches:
wherein the cap layer ( Haran, FIG. 8, 602; [0061], isolation structure 602; FIG. 10, 1002; [0077], conductive structure 1002; FIG. 10, 1004; FIG. 8, 602; [0077], gate hard mask 1004; [0061], isolation structure 602 ) comprises a high-k dielectric material ( Haran, [0077], The gate hard masks 1004 can be made of any suitable material, such as, for example, silicon nitride. In some embodiments of the invention, the gate hard masks 1004 are formed by recessing the gates 802 and 804 and the conductive structure 1002, exposing sidewalls of the isolation structure 602 (Y3 cross-section). The gate hard masks 1004 can then be formed or deposited on the recessed surfaced of the gates 802 and 804 ).
Regarding Claim 12 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 10, on which this claim is dependent, Haran further teaches:
wherein an interface between the cap layer ( Haran, FIG. 10, 602; [0061], isolation structure 602; FIG. 10, 1002; [0077], conductive structure 1002; FIG. 10, 1004; FIG. 8, 602; [0077], gate hard mask 1004; [0061], isolation structure 602 … In some embodiments of the invention, the isolation structure 602 includes silicon nitride ) and the dielectric wall ( Haran, 602; [0061], isolation structure 602 ) is lower than a top surface of the first S/D structure ( Haran, [0077], The gate hard masks 1004 can be made of any suitable material, such as, for example, silicon nitride. In some embodiments of the invention, the gate hard masks 1004 are formed by recessing the gates 802 and 804 and the conductive structure 1002, exposing sidewalls of the isolation structure 602 (Y3 cross-section). The gate hard masks 1004 can then be formed or deposited on the recessed surfaced of the gates 802 and 804 ).
Regarding Claim 13 ( Original ), Haran teaches the semiconductor structure as claimed in claim 10, on which this claim is dependent, Haran further teaches:
wherein the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) has a top portion ( Haran, FIG. 3, 306 between 304; FIG. 10, 602 ) and a bottom portion ( Haran, FIG. 3, 112; FIG. 10, 112 ), and the bottom portion ( Haran, FIG. 3, 112; FIG. 10, 112 ) is wider than the top portion ( Haran, FIG. 3, 306 between 304; FIG. 10, 602 ).
Regarding Claim 14 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 10, on which this claim is dependent, Haran further teaches: comprising:
an isolation structure ( Haran, FIG. 3, 112; [0039], shallow trench isolation region 112 … The trench can then be filled with dielectric material, such as, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ) formed over the substrate ( Haran, FIG. 1, 104; [0033], substrate 104 ), wherein the isolation structure ( Haran, FIG. 3, 112; [0039], shallow trench isolation region 112 ) and the dielectric wall dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306 … isolation dielectric 306 can be made of any suitable dielectric material, such as, for example, oxides, a low-k dielectric, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) are made of the same material.
Regarding Claim 15 ( Original ), Haran teaches the semiconductor structure as claimed in claim 10, on which this claim is dependent, Haran further teaches:
wherein a portion of the first S/D structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ) is in direct contact with the dielectric wall ( Haran, [0047], As further shown in FIG. 2, in some embodiments of the invention, spacers 202 (also known as sidewall spacers or gate spacers) are formed on sidewalls of the sacrificial gates 118; [0048] The spacers 202 can be made of any suitable material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodiments of the invention, the spacers 202 include silicon nitride. The spacers 202 can be formed to a thickness of about 5 to 40 nm, although other thicknesses are within the contemplated scope of the invention ).
Regarding Claim 16 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 10, on which this claim is dependent, Haran further teaches: comprising:
a spacer layer ( Haran, FIG. 3, 202; [0047], spacers 202 ) adjacent to the first S/D structure ( Haran, FIG. 3, 304; [0051], source and drain regions 304 ), wherein a top surface of the dielectric wall ( Haran, FIG. 8, 602; [0061], isolation structure 602 ) is higher than a top surface of the spacer layer ( Haran, FIG. 3, 202; [0047], spacers 202 ).
Regarding Claim 17 ( Previously Presented ), Haran teaches the semiconductor structure as claimed in claim 10, on which this claim is dependent, Haran further teaches: comprising:
a first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) formed over the substrate ( Haran, FIG. 1, 104; [0033], substrate 104 ), wherein the first stack structure comprises a plurality of nanostructures ( Haran, FIG. 1, 106; [0033], semiconductor layers 106 ); and
a second stack structure ( Haran, FIG. 1, 102, above the one labeled by X; [0033], nanosheet stacks 102 ) formed adjacent to the first stack structure, wherein the second stack structure comprises a plurality of nanostructures ( Haran, FIG. 1, 106; [0033], semiconductor layers 106 ), and the dielectric wall ( Haran, FIG. 3, 306 between 304, 112; FIG. 10, 602, 112; [0056], isolation dielectric 306; [0051], source and drain regions 304 ; [0039], shallow trench isolation region 112; [0061], isolation structure 602 ) is between the first stack structure ( Haran, FIG. 1, 102, labeled by X; [0033], nanosheet stacks 102 ) and the second stack structure ( Haran, FIG. 1, 102, above the one labeled by X; [0033], nanosheet stacks 102 ).
Response to Arguments
Applicant’s argument for claim 1: page 7, line 11 from bottom, cited “ it is respectfully submitted that the elements 112, 602 mapped to the dielectric wall do not include a single, continuous layer of the low-k dielectric material … Regardless of whether the shallow trench isolation 112, the liner 116, and the isolation structure 602 can have the same material, each of the shallow trench isolation 112, the liner 116, and the isolation structure 602 is formed in a different processing step, and the combination thereof cannot be a single, continuous layer. ”.
Examiner’s response: based on the teaching from prior art Haran, [0039], cited “ a shallow trench isolation region 112 (also referred to as an STI region) can be formed adjacent to the nanosheet stacks 102 … The trench can then be filled with dielectric material, such as, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ”; and [0061], cited “an isolation structure 602 is formed over the semiconductor structure 100 … The isolation structure 602 can be made of any suitable dielectric material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ”; therefore, the elements 112, 602 mapped to the dielectric wall could be mapped as a single, continuous layer of the low-k dielectric material. Besides, as long as 112/116/602 have the same material, even though 112/116/602 are formed in different processing steps, the formed structure can be a single and continuous layer, because “ a single and continuous layer ” is determined by the material by which it is formed, not by the steps; for instance, 112 is formed by many steps, but it can be single and continuous, as long as the material in 112 is single and continuous.
Applicant’s argument for claim 1: page 8, line 7, cited “ It is also respectfully submitted that the elements 602, 112 mapped to the dielectric wall do not have a first sidewall contiguous with a sidewall of at least one of the semiconductor layers 106 of the nanosheet stack 102 and a second sidewall contiguous with a sidewall of at least one of the semiconductor layers 106 of the other nanosheet stack 102 … Haran does not teach that the distance "b" can be equal to zero as the Office alleges. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ Haran did not explicitly disclose that the dielectric wall has a first sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the first stack structure and a second sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the second stack structure;
However, Haran disclosed that in FIG. 10 silicon nanosheets 106 ( i.e. channel ) is all around ( i.e. gate-all-around, GAA ) by metal gates 802 and 804, therefore there is distance b between isolation structure 602 and channel silicon nanosheets 106;
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use FinFET to replace GAA in Haran FIG. 10, and therefore to have the distance b between isolation structure 602 and channel silicon nanosheets 106 to be 0, which means that the dielectric wall has a first sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the first stack structure and a second sidewall contiguous with a sidewall of at least one of the plurality of nanostructures of the second stack structure, since this is within the skill level of one in the art. ”.
Applicant’s argument for claim 1: page 9, line 3, cited “ it is also respectfully submitted that the elements 602, 112 mapped to the dielectric wall and an instance of the shallow trench isolation 112 are not respective portions of a same material layer. ”.
Examiner’s response: based on the teaching from prior art Haran, [0039], cited “ a shallow trench isolation region 112 (also referred to as an STI region) can be formed adjacent to the nanosheet stacks 102 … The trench can then be filled with dielectric material, such as, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ”; and [0061], cited “an isolation structure 602 is formed over the semiconductor structure 100 … The isolation structure 602 can be made of any suitable dielectric material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ”; therefore, the elements 112, 602 mapped to the dielectric wall could be same low-k dielectric material.
Applicant’s argument for claim 10: page 10, line 8, cited “ it is respectfully submitted that the isolation structure 602 (e.g., corresponding to the cap layer) does not comprise a different dielectric material than a low-k dielectric material of the isolation structure 602 (e.g., corresponding to the dielectric wall). ”.
Examiner’s response: please refer to claim 10 in Claim Rejections - 35 USC § 102 of this office action, cited “ the cap layer ( Haran, FIG. 8, isolation structure 602; [0061], The isolation structure 602 can be made of any suitable dielectric material, such as, for example, … a nitride, silicon nitride, … In some embodiments of the invention, the isolation structure 602 includes silicon nitride ) comprising a different dielectric material than the low-k dielectric material of the dielectric wall ( Haran, FIG. 8, FIG. 10, 116; [0041], The liner 116 can be made of any suitable material, such as, for example, a low-k dielectric or an oxide (e.g., SiO.sub.2) ). ”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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