DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2014/0197456) (hereafter Wang), in view of Wu et al. (US 2013/0001591) (hereafter Wu591).
Regarding claim 1, Wang discloses a method for forming a diffusion break structure in a finfield effect transistor, wherein the method at least comprises:
step 1, performing a lithography process (“photolithography process” in paragraph 0016) on a substrate 210 (Fig. 3, paragraph 0016) to form a lithography pattern 212 (Fig. 3, paragraph 0016) of a single diffusion break structure 230 (Fig. 17, paragraph 0017), wherein an initial opening width (horizontal length between 212 in Fig. 3) of the lithography pattern is c;
step 2, etching (“photolithography process” in paragraph 0017) the substrate 210 (Fig. 3) to form an etched single diffusion break structure (“trench” in paragraph 0017), wherein an opening width (horizontal length of 230 in Fig. 3) of the etched single diffusion break structure (“trench” in paragraph 0017) is d;
step 3, performing an epitaxial growth process (“epitaxial growing processes” in paragraph 0019), and forming an epitaxial layer 420 (Fig. 5, paragraph 0019) on a surface of the substrate 210 (Fig. 5), wherein a thickness (vertical length of 420 in Fig. 5) of the epitaxial layer 420 (Fig. 5) is t, wherein the epitaxial-layer-covered single diffusion break structure 230 (Fig. 5) has an opening width b;
step 4, etching (see “CMP” in paragraph 0019 and “recessing the isolation regions 230” in paragraph 0020) the substrate and the epitaxial-layer-covered single diffusion break structure 230 (Fig. 5), to form a plurality of fin structures (510 and 520 in Fig. 6, paragraph 0020), wherein the plurality of fin structures (510 and 520 in Fig. 6) are arranged at intervals;
step 5, forming an isolation layer (“thermal oxide liner layer” in paragraph 0022) between two adjacent ones of the plurality of fin structures 420 (Fig. 8A), wherein the adjacent fins 420 (Fig. 8A) are isolated from each other by the isolation layer (“thermal oxide liner layer” in paragraph 0022), wherein top surfaces of the plurality of fin structures 420 (Fig. 8A) is higher (see Fig. 8A, wherein top surfaces of 420 is higher than a top surface of 230, wherein “thermal oxide liner layer” (in paragraph 0022) is portion of 230) than a top surface of the isolation layer (“thermal oxide liner layer” in paragraph 0022); and
step 6, forming a plurality of gates 614 (Fig. 8A, paragraph 0022) spaced apart from each other respectively at the top surface of the isolation layer (“thermal oxide liner layer” in paragraph 0022), at side walls and the top surfaces of the plurality of fin structures 420 (Fig. 8A) in the single diffusion break structure 230 (Fig. 8A).
Wang does not disclose forming an epitaxial layer on a bottom surface of the etched single diffusion break structure and side walls of the etched single diffusion break structure.
Wu591 discloses forming an epitaxial layer 1000 (Fig. 10, paragraph 0013) on a bottom surface and side walls of the etched single diffusion break structure (region 104 is formed in fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang to include forming an epitaxial layer on a bottom surface of the etched single diffusion break structure and side walls of the etched single diffusion break structure, as taught by Wu591, since an epitaxial layer 1000 (Wu591, Fig. 9, paragraph 0013) fills the reduced trenches 900 (Wu591, Fig. 9, paragraph 0013) without forming a void.
Regarding claim 2, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein in step 1, the plurality of fin structures (510 and 520 in Fig. 6) are formed in a portion of the substrate 210 (Fig. 6).
Regarding claim 3, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein the substrate 210 (Fig. 6, paragraph 0013, wherein “silicon”) in step 1 is a silicon substrate.
Regarding claim 4, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein an ion implantation process (“implantation of oxygen (SIMOX)” in paragraph 0013) or epitaxial growth process has been applied to the substrate in step 1.
Regarding claim 5, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein the substrate in step 1 is provided with a hard mask 212 (Fig. 3, paragraph 0016).
Regarding claim 8, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein the opening width d (horizontal length of 230 in Fig. 3) of the etched single diffusion break structure (“trench” in paragraph 0017) depends on the initial opening width c (horizontal length between 212 in Fig. 3) of the lithography pattern 212 (Fig. 3) and an etch bias of the etching process in step 2.
Regarding claim 9, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 8, wherein the opening width d (horizontal length of 230 in Fig. 3) of the etched single diffusion break structure (“trench” in paragraph 0017) in step 2 is d=c-x (see Fig. 3, wherein horizontal length of 230 and horizontal length between 212 are same; and Wang does not disclose etch bias), wherein c is the initial opening width (horizontal length between 212 in Fig. 3) of the lithography pattern in step 1, and x is the etch bias of the etching process in step 2.
Regarding claim 10, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein after step 2, a double patterning technique (see “photolithography process” in paragraph 0016 and “photolithography process” in paragraph 0017) including step 1 and step 2 is repeated to obtain a doubled single diffusion break structure (first 230 from the left corner of Fig. 3) with a smaller spacing (see Fig. 3, wherein a spacing between first 230 and second 230 is smaller than a spacing between second 230 and fifth 230 from the left corner of Fig. 3) between two adjacent ones of the single diffusion break structures.
Regarding claim 11, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein the epitaxial growth process in step 3 is homoepitaxy (see paragraph 0016, wherein 210 is silicon; and see paragraph 0019, wherein 420 is silicon (Si)).
Regarding claim 12, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein the epitaxial growth process in step 3 is heteroepitaxy (see paragraph 0016, wherein 210 is silicon; and see paragraph 0019, wherein 420 is silicon germanium (SiGe)).
Regarding claim 13, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein a doping process (see paragraph 0021, wherein “the second and third fins, 510 and 520, have source/drain regions 530 and a gate region 540”; and see paragraph 0020, wherein “forming second fins 510 in the N-type FET region 315 and third fins 520 in the P-type FET region 325”) is performed on the epitaxial layer in step 3.
Regarding claim 18, Wang further discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, wherein forming the isolation layer (“thermal oxide liner layer” in paragraph 0022) in step 5 further comprises: sub-step 1, depositing an isolation material (“one or more dielectric materials” in paragraph 0017); and sub-step 2, removing redundant isolation material (“excessive dielectric materials” in paragraph 0017) using chemical mechanical polishing (“CMP” in paragraph 0017) or etching back to form the isolation layer.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Wu591 as applied to claim 1 above, and further in view of Yi et al. (US 2016/0254369) (hereafter Yi).
Regarding claim 6, Wang in view of Wu591 discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, however Wang and Wu591 do not disclose in step 1, before formation of the lithography pattern, a carbon layer and a bottom antireflection layer are both formed on the substrate.
Yi discloses in step 1, before formation of the lithography pattern 114 (Fig. 1I, paragraph 0013), a carbon layer 113 (Fig. 1I, paragraph 0013) and a bottom antireflection layer 112 (Fig. 1I, paragraph 0013) are both formed on the substrate 101 (Fig. 1I, paragraph 0005).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Wu591 to form in step 1, before formation of the lithography pattern, a carbon layer and a bottom antireflection layer are both formed on the substrate, as taught by Yi, in order to ensure the control (Yi, paragraph 0084) of the profile and critical dimensions of the pattern to be transferred.
Regarding claim 7, Wang in view of Wu591 discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, however Wang and Wu591 do not disclose in step 1, before formation of the lithography pattern, a carbon layer or a bottom antireflection layer is formed on the substrate.
Yi discloses in step 1, before formation of the lithography pattern 114 (Fig. 1I, paragraph 0013), a carbon layer 113 (Fig. 1I, paragraph 0013) or a bottom antireflection layer 112 (Fig. 1I, paragraph 0013) is formed on the substrate 101 (Fig. 1I, paragraph 0005).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Wu591 to form in step 1, before formation of the lithography pattern, a carbon layer or a bottom antireflection layer is formed on the substrate, as taught by Yi, in order to ensure the control (Yi, paragraph 0084) of the profile and critical dimensions of the pattern to be transferred.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Wu591 as applied to claim 1 above, and further in view of Wu et al. (US 2021/0013108) (hereafter Wu108).
Regarding claim 14, Wang in view of Wu591 discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, however Wang and Wu591 do not disclose forming the plurality of fin structures in step 4 comprises a single lithography-etch process.
Wu108 discloses forming the plurality of fin structures (“fin patterning” in paragraph 0037) in step 4 comprises a single lithography-etch process (“lithography (e.g., extreme ultraviolet (EUV)) in conjunction with RIE” in paragraph 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Wu591 to include forming the plurality of fin structures in step 4 comprises a single lithography-etch process, as taught by Wu108, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing lithography (e.g., extreme ultraviolet (EUV)) in conjunction with RIE from the methods listed in Wu108 (e.g. lithography (e.g., extreme ultraviolet (EUV)) in conjunction with RIE, self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), and/or self-aligned quadruple patterning (SAQP)); if this leads to the anticipated success, in the instant case providing a method of fin patterning, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 15, Wang in view of Wu591 discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, however Wang and Wu591 do not disclose forming the plurality of fin structures in step 4 comprises double patterning technique having lithography-etch-lithography-etch steps.
Wu108 discloses forming the plurality of fin structures (“fin patterning” in paragraph 0037) in step 4 comprises double patterning technique having lithography-etch-lithography-etch steps (“self-aligned double patterning (SADP)” in paragraph 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Wu591 to include forming the plurality of fin structures in step 4 comprises double patterning technique having lithography-etch-lithography-etch steps, as taught by Wu108, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing self-aligned double patterning (SADP) from the methods listed in Wu108 (e.g. lithography (e.g., extreme ultraviolet (EUV)) in conjunction with RIE, self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), and/or self-aligned quadruple patterning (SAQP)); if this leads to the anticipated success, in the instant case providing a method of fin patterning, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 16, Wang in view of Wu591 discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, however Wang and Wu591 do not disclose forming the plurality of fin structures in step 4 is a self aligned double patterning technique.
Wu108 discloses forming the plurality of fin structures (“fin patterning” in paragraph 0037) in step 4 is a self aligned double patterning technique (“self-aligned double patterning (SADP)” in paragraph 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Wu591 to include forming the plurality of fin structures in step 4 is a self aligned double patterning technique, as taught by Wu108, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing self-aligned double patterning (SADP) from the methods listed in Wu108 (e.g. lithography (e.g., extreme ultraviolet (EUV)) in conjunction with RIE, self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), and/or self-aligned quadruple patterning (SAQP)); if this leads to the anticipated success, in the instant case providing a method of fin patterning, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 17, Wang in view of Wu591 discloses the method for forming the diffusion break structure in the finfield effect transistor according to claim 1, however Wang and Wu591 do not disclose forming the plurality of fin structures in step 4 is a self aligned quadruple patterning technique.
Wu108 discloses forming the plurality of fin structures (“fin patterning” in paragraph 0037) in step 4 is a self aligned quadruple patterning technique (self-aligned quadruple patterning (SAQP)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Wu591 to include forming the plurality of fin structures in step 4 is a self aligned double patterning technique, as taught by Wu108, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing self-aligned quadruple patterning (SAQP) from the methods listed in Wu108 (e.g. lithography (e.g., extreme ultraviolet (EUV)) in conjunction with RIE, self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), and/or self-aligned quadruple patterning (SAQP)); if this leads to the anticipated success, in the instant case providing a method of fin patterning, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813