DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
3. Applicant’s election with traverse of Invention I, identified as encompassing claims 1-13 is acknowledged.
The arguments present the opinion that there is no excess examination burden without providing any reasoning and/or evidence to which the Examiner disagrees for reasons detailed in the requirement for restriction.
Therefore, the restriction is maintained and made final.
Claim Objections
4. Claims 3 and 5 are objected to because of the following informalities:
5. Claim 3 recites “the first doped regions are further disposed between the outermost extension parts and the insulating structures”. The current claim depends on claims 1-2 which require “a plurality of first doped regions disposed in the substrate between the plurality of extension parts; and a plurality of second doped regions disposed in the substrate at two outer sides of the plurality of extension parts … a plurality of insulating structures disposed on the substrate between outermost extension parts of the extension parts and the second doped regions”. It is indefinite as to how the first doped regions are between the outermost extension parts but also between the outermost extension parts and the second insulating structures which are on outer sides of the extension parts because they are required to be between outermost extension parts and the second doped regions.
For the purposes of compact prosecution, the interpretation will be taken that there are some of the plurality of the first doped regions between the plurality of extension parts and others of the plurality of the first doped regions between the outermost extension parts and the insulating structures.
6. Claim 5 recites in the last line “in in the” which should be changed to “
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by
Ham (US 5,874,763), hereinafter as H1
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8. Regarding Claim 1, H1 discloses an electrostatic discharge protection device (see in particular Figs. 2-3“Labeled Fig. 2” above, and column 3 lines 19-21 “electrostatic discharge (ESD) protection device”), comprising:
a gate structure (element 42, see Column4 lines 12-13 “gate electrode 42”) disposed on a substrate (element 50, see Column 3 line 58 “semiconductor substrate 50”), wherein the gate structure comprises a body part (labeled element “Body Part”) and a plurality of extension parts (labeled elements “Extension Parts”), the body part is connected to the plurality of extension parts (see “Labeled Fig. 2” above), and an extension direction of the body part is different from an extension direction of the plurality of extension parts (see “Labeled Fig. 2” above);
a plurality of first doped regions (elements 40, 44, see Column 4 lines 18-19 “N-type source and drain regions 44 and 40”) disposed in the substrate between the plurality of extension parts; and
a plurality of second doped regions (elements 46, see Column 3 lines 61-62 “highly doped well contact regions 46 and 47 of first conductivity type (e.g. P+)”) disposed in the substrate at two outer sides of the plurality of extension parts (see Figs. 2-3 and “Labeled Fig. 2” above),
wherein the plurality of first doped regions and the plurality of second doped regions have different conductivity types (N-type versus P-type).
9. Regarding Claim 2, H1 discloses the electrostatic discharge protection device of claim 1, further comprising:
a plurality of insulating structures (outermost gate insulating sidewall liners, see Fig. 3 unlabeled, and elements 54, see Column 4 line 30 “Filed oxide isolation 54”) disposed on the substrate between outermost extension parts of the extension parts and the second doped regions (see Figs. 2-3).
10. Regarding Claim 3, insofar as the claimed can be interpreted and understood despite the 112b issues, H1 discloses the electrostatic discharge protection device of claim 2, wherein the first doped regions are further disposed between the outermost extension parts and the insulating structures (see Fig. 3 elements 44 portions are between the outermost extension parts and the insulating structure elements 54).
11. Regarding Claim 4, H1 discloses the electrostatic discharge protection device of claim 2, wherein the body part is connected to the insulating structures (outermost gate insulating sidewall liners are connected at the intersecting portion with the extension parts).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ham (US 5,874,763), hereinafter as H1, in view of Lin et al. (US 2002/0074602 A1), hereinafter as L1
13. Regarding Claim 5, H1 discloses the electrostatic discharge protection device of claim 1.
H1 does not explicitly disclose wherein the substrate comprises a semiconductor-on-insulator substrate, and the semiconductor-on-insulator comprises: a semiconductor substrate; a semiconductive layer disposed over the semiconductor substrate; and a buried insulating layer located between the semiconductor substrate and the semiconductive layer, wherein the first doped regions and the second doped regions are located in in the semiconductive layer of the semiconductor-on-insulator substrate.
L1 discloses (see Fig. 5 and [0055] “ESD protection device 500”) wherein the substrate comprises a semiconductor-on-insulator substrate (see [0055] “formed with SOI process technology”), and the semiconductor-on-insulator comprises: a semiconductor substrate (element 302, see [0052] “silicon substrate 302”); a semiconductive layer (layer above element 304, see [0052] “p-well 306 that corresponds to substrate 202” – and SOI in the stacked order) disposed over the semiconductor substrate; and a buried insulating layer (element 304, see [0052] “oxide layer 304”) located between the semiconductor substrate and the semiconductive layer (see Fig. 5), wherein the first doped regions (outermost elements 306, see [0052] “p-well 306”) and the second doped regions (elements 210, see [0049] “N+ drain region 210”) are located in in the semiconductive layer of the semiconductor-on-insulator substrate (see Fig. 5).
The SOI substrate as taught by L1 is incorporated as the SOI substrate of H1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with H1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known substrate type for another for which the two are provided as alternatives (see [0055] “Device 500 is configured the same as device 200 except that device 500 is both formed with SOI process technology and with current divider segments 402 formed of polysilicon layer 404 over oxide layer 406”)
Allowable Subject Matter
14. Claims 6-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
15. Claim 6, “a plurality of third doped regions disposed in the substrate at a first side of the body part of the gate structure and between the extension parts of the gate structure; a plurality of fourth doped regions disposed in the substrate at a second side of the body part of the gate structure; and a plurality of fifth doped regions disposed in the substrate at the first side of the body part of the gate structure and outside of and the extension parts of the gate structure, wherein the third doped regions and the first doped regions have the same conductivity type, and the fifth doped regions, the fourth doped regions and the second doped regions have the same conductivity type” – as instantly claimed and in combination with the additionally claimed` limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; pertinent prior art(s) and most relevant portion(s) is provided:
US 10,297,590 (Fig. 9); US 2017/0221878 (Fig. 1A-B); US 2012/0326235 (Fig. 2, 3A); US 2007/0002507 (Fig. 2); US 2004/0141266 (Fig. 3a-b); US 2003/0202307 (Figs. 1-6)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMUEL PARK/Examiner, Art Unit 2818