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DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 10/13/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al (US Publication No. 2022/0406913).
Regarding claim 1, Chen discloses a method, comprising: forming a semiconductor fin Fig 3, 52 over a substrate Fig 3, 50; forming an isolation region Fig 6, 56 around the semiconductor fin Fig 6,52; forming a dummy gate structure Fig 7A, 62 over the semiconductor fin Fig 7A, 52, including performing a first etching process using a first etchant Fig 9-10 ¶0037-0039 and subsequently performing a second etching process using a second etchant ¶0039-0042, the first etchant being different from the second etchant in composition ¶0037-0042; forming source/drain features adjacent the dummy gate structure Fig 18B; and replacing the dummy gate structure with a metal gate structure that is interposed between the source/drain features Fig 23B.
Claims 21 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al (US Publication No. 2022/0415716).
Regarding claim 21, Jang discloses a method, comprising: forming a first semiconductor fin Fig 4, 404 and a dielectric fin Fig 6, 600 over a substrate; forming an isolation structure Fig 7, 700 to separate the first semiconductor fin from the dielectric fin Fig 7; depositing a gate layer Fig 10, 1004 over the first semiconductor fin, the dielectric fin, and the isolation structure Fig 10; etching the gate layer into a dummy gate structure via a plurality of trimming processes Fig 10-18, the plurality of trimming processes including a first trimming process with a first oxygen content ¶0065 and a second trimming process with a second oxygen content, wherein the second oxygen content is greater than the first oxygen content ¶0070-0071; performing a first nitrogen treatment between the first trimming process ¶0065-0066 and the second trimming process¶0070-0071; forming source/drain features adjacent the dummy gate structure; and replacing the dummy gate structure with a metal gate structure interposed between the source/drain features.
Regarding claim 24, Jang discloses wherein the first trimming process includes a first etchant including CF4, HBr, and 02 ¶0065-0071 and the second trimming process includes a second etchant including Cl2HBr, and 02¶0065-0071.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-13, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US Publication No. 2022/0415716) in view of Wang et al (US Publication No. 2019/0288084).
Regarding claim 1, Jang discloses a method, comprising: forming a semiconductor fin Fig 4, 404 over a substrate Fig 4, 302; forming an isolation region Fig 7, 700 around the semiconductor fin Fig 7, 404; forming a dummy gate structure Fig 10, 1000 over the semiconductor fin Fig 10, 404, including performing a first etching process using a first etchant ¶0065-0066 and subsequently performing a second etching process using a second etchant ¶0068-0070, forming source/drain features adjacent the dummy gate structure Fig 12; and replacing the dummy gate structure with a metal gate structure that is interposed between the source/drain features Fig 18. Jang discloses all the limitations except for having different etchant. Whereas Wang discloses the first etchant being different from the second etchant in composition ¶0023-0024 and 0027-0030. Jang and Wang are analogous art because they are directed to semiconductor devices having dummy gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the etchant of Jang and incorporate the teachings of Wang to have better control of the etchant and shape of the dummy gate.
Regarding claim 2, Jang discloses wherein the forming of the dummy gate structure further includes depositing a gate layer over the semiconductor fin and the isolation region Fig 8A-8B, such that the performing of the first etching process removes a first portion of the gate layer above a top surface of the semiconductor fin Fig 11A-11B; While Wang discloses performing of the second etching process removes a second portion of the gate layer below the top surface of the semiconductor fin Fig 2.
Regarding claim 3, Wang discloses wherein the forming of the dummy gate structure further includes performing a first nitrogen treatment after performing the first etching process ¶0023 and performing a second nitrogen treatment after performing the second etching process ¶0026-0030.
Regarding claim 4, Jang discloses wherein the first etchant includes a fluorine- containing etching gas and the second etchant includes a chlorine-containing etching gas¶0065-0070.
Regarding claim 5, Jang discloses wherein both the first etchant and the second etchant include 02, and wherein an amount of 02 in the second etchant is greater than an amount of 02 in the first etchant ¶0065, 0070-0071.
Regarding claim 6, Wang discloses wherein the semiconductor fin includes silicon germanium ¶0017, and wherein a portion of the dummy gate structure formed adjacent the semiconductor fin has a first width along a bottom surface of the dummy gate structure and a second width near a top surface of the semiconductor fin, the first width being less than the second width Fig 2.
Regarding claim 10, Jang discloses a method, comprising: forming a semiconductor fin Fig 4, 404 over a substrate Fig 4, 302; forming a dielectric fin Fig 6, 600 over the substrate and adjacent the semiconductor fin; forming an isolation structure Fig 7, 700 to separate the semiconductor fin from the dielectric fin Fig 7; forming a dummy gate structure Fig 10, 1000 over the semiconductor fin and the dielectric fin Fig 10, including implementing a first etching process using a first etchant ¶0065-0066 and subsequently implementing a second etching process using a second etchant ¶0068-0070, forming source/drain features adjacent the dummy gate structure Fig 12; and replacing the dummy gate structure with a metal gate structure that is interposed between the source/drain features Fig 18. Jang discloses all the limitations except for having different etchant. Whereas Wang discloses the first etchant being different from the second etchant in composition ¶0023-0024 and 0027-0030. Jang and Wang are analogous art because they are directed to semiconductor devices having dummy gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the etchant of Jang and incorporate the teachings of Wang to have better control of the etchant and shape of the dummy gate.
Regarding claim 11, Jang discloses wherein the first etchant includes CF4, HBr, and 02 and the second etchant includes Cl2, HBr, and 02 ¶0065 and 0070.
Regarding claim 12, Jang discloses wherein the first etching process is implemented with a lower flux of 02 than the second etching process ¶0065, 0070-0071.
Regarding claim 13, Wang discloses wherein the forming of the dummy gate structure further includes implementing a lateral trimming process to reduce a width of the dummy gate structure at a bottom surface thereof Fig 2.
Regarding claim 25, Wang wherein etching the gate layer into the dummy gate structure further includes implementing a lateral trimming process to reduce a width of the dummy gate structure at a bottom surface thereof Fig 2.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US Publication No. 2022/0415716) in view of Wang et al (US Publication No. 2019/0288084) and in further view of Chen et al (US Publication No. 2022/0406913).
Regarding claim 7, Wang discloses wherein the semiconductor fin includes silicon and is free from germanium ¶0017. Wang discloses all the limitations except for the third etching. Whereas Chen discloses wherein the forming of the dummy gate structure further includes performing a third etching process after performing the second etching process, the third etching process being performed to etch laterally along a width of the dummy gate structure along a bottom surface of the dummy gate structure Fig 9-12. Jang and Chen are analogous art because they are directed to semiconductor devices having dummy gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the etching frequency of Jang and incorporate the teachings of Chen to have better control of the etchant and shape of the dummy gate.
Regarding claim 8, Chen discloses wherein the performing of the third etching process is implemented using a third etchant that is different from the first etchant and the second etchant in composition ¶0036-0042.
Claims 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US Publication No. 2022/0415716) in view of Wang et al (US Publication No. 2019/0288084) and in further view of Cheng et al (US Publication No. 2022/0254776).
Regarding claims 9 and 14, Jang discloses a dielectric fin over the substrate and adjacent the semiconductor fin Fig 10. Jang discloses all the limitations but silent on the height of the isolation structure. Whereas Cheng discloses a first portion of the isolation region having a first step height is formed adjacent a first sidewall of the fin and a second portion of the isolation region having a second step height is formed adjacent a second sidewall of the fin, the first step height being different from the second step height Fig 31. Jang and Cheng are analogous art because they are directed to semiconductor devices having dummy gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the isolation heights of Jang and incorporate the teachings of Cheng to control and adjust device performance characteristics ¶0003-0004.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US Publication No. 2022/0415716) in view of Wang et al (US Publication No. 2019/0288084) and Cheng et al (US Publication No. 2022/0254776) and in further view of Ching et al (US Publication No. 2021/0234036).
Regarding claim 15, Jang discloses wherein the first portion of the isolation structure is disposed between the first semiconductor fin and the dielectric fin and the second portion of the isolation structure is disposed between the dielectric fin and the second semiconductor fin Fig 10. Jang discloses all the limitations but silent on the material used for the fins. Whereas Ching discloses wherein the semiconductor fin is a first semiconductor fin formed from silicon, the method further comprising forming a second semiconductor fin from silicon germanium Fig 2D Claim 8. Jang and Cheng are analogous art because they are directed to semiconductor devices having fin structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the fin material of Jang and incorporate the teachings of Ching since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US Publication No. 2022/0415716) in view of Cheng et al (US Publication No. 2022/0254776).
Regarding claim 22, Jang discloses all the limitations but silent on the height of the isolation structure. Whereas Cheng discloses a first portion of the isolation region having a first step height is formed adjacent a first sidewall of the fin and a second portion of the isolation region having a second step height is formed adjacent a second sidewall of the fin, the first step height being different from the second step height Fig 31. Jang and Cheng are analogous art because they are directed to semiconductor devices having dummy gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the isolation heights of Jang and incorporate the teachings of Cheng to control and adjust device performance characteristics ¶0003-0004.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US Publication No. 2022/0415716) in view of Cheng et al (US Publication No. 2022/0254776) and in further view of Ching et al (US Publication No. 2021/0234036).
Regarding claim 23, Jang discloses wherein the first portion of the isolation structure is disposed between the first semiconductor fin and the dielectric fin and the second portion of the isolation structure is disposed between the dielectric fin and the second semiconductor fin Fig 10. Jang discloses all the limitations but silent on the material used for the fins. Whereas Ching discloses wherein the semiconductor fin is a first semiconductor fin formed from silicon, the method further comprising forming a second semiconductor fin from silicon germanium Fig 2D Claim 8. Jang and Cheng are analogous art because they are directed to semiconductor devices having fin structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the fin material of Jang and incorporate the teachings of Ching since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811