Prosecution Insights
Last updated: July 17, 2026
Application No. 18/165,669

ETCHING PROCESS WITH PROTECTED REGION

Non-Final OA §102§103
Filed
Feb 07, 2023
Priority
Nov 09, 2022 — provisional 63/383,016
Examiner
MCCUTCHEON, COLIN RUSSELL
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
43 granted / 50 resolved
+18.0% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
23 currently pending
Career history
67
Total Applications
across all art units

Statute-Specific Performance

§103
85.9%
+45.9% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 50 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/9/2026 has been entered. Claims’ Status & Response to Amendment Claims 1-7, 10-17, and 19-23 are currently pending and being examined. Claims 1, 12, and 17 have been amended. Claims 8-9 and 18 have been cancelled. Claims 21-23 have been newly added. The amendment to Claim 12 has overcome the objection to Claim 12 of the last Office Action (filed 12/29/2025), and therefore said objection is withdrawn. Withdrawal of Allowable Subject Matter The indicated allowable subject matter of Claim 9 (now fully incorporated into Claim 1) in the 12/29/2025 Final Rejection is withdrawn in view of further consideration and reinterpretation of the previously presented prior art Gaul et al (US 2024/0072041 A1). The new rejection of Claim 1, based on the reinterpretation of Gaul et al, follows. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 4-5, 7, 10, and 21-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gaul et al (US 2024/0072041 A1, of record, hereafter Gaul). Re Claim 1, Gaul discloses a method for manufacturing a semiconductor device (FIG. 2A-17B; [0053]-[0097]), comprising: forming a first structure (206, 304, 306, 308, left portion in FIG. 4B, hereafter just 206, 304, 306, 308, left portion; [0062]) and a second structure (206, 304, 306, 308, right portion in FIG. 4B, hereafter just 206, 304, 306, 308, right portion; [0062]), wherein each structure comprises alternately stacked first and second layers (306, 308; [0062]); forming an isolation material (406; [0064]) between the first structure (206, 304, 306, 308, left portion) and the second structure (206, 304, 306, 308, right portion; [0064]); forming a spacer layer (408; [0062]) over the first structure (206, 304, 306, 308, left portion), the isolation material (406), and the second structure (206, 304, 306, 308, right portion; [0062]), wherein the spacer layer (408) includes an upper portion (408, top horizontal portions; [0062]) located over the first structure (206, 304, 306, 308, left portion) and the second structure (206, 304, 306, 308, right portion; [0062]), and a lower portion (408, sidewall portions facing each other) over the isolation material (406) and between the first structure (206, 304, 306, 308, left portion) and the second structure (206, 304, 306, 308, right portion; [0062]); and while the spacer layer (408) remains over the isolation material (406), performing an etch process to remove the alternately stacked first and second layers (306, 308, at least partially; [0074]), wherein removing the alternately stacked first and second layers (306, 308) comprises forming a first cavity (902, left portion in FIG. 9B, hereafter just 902, left portion; [0074]) and forming a second cavity (902, right portion in FIG. 9B, hereafter just 902, right portion; [0074]); selectively growing epitaxial material in the first cavity (902, left portion) and in the second cavity (902, right portion) to form source/drain regions (1302; [0084]); and removing the spacer layer (408) after selectively growing the epitaxial material to form the source/drain regions (1302; [0088]). Re Claim 4, Gaul discloses the method according to Claim 1, while further disclosing wherein the lower portion of the spacer layer (408, sidewall portions facing each other) has a thickness of from 1 to 15 nanometers (nm) ([0065]). Re Claim 5, Gaul discloses the method according to Claim 1, while further disclosing wherein, before performing the etch process to remove the alternately stacked first and second layers (306, 308, at least partially; [0074]), the alternately stacked first and second layers (306, 308) have a combined height of from 30 to 70 nanometers (nm) ([0058]). Re Claim 7, Gaul discloses the method according to Claim 1, while further disclosing wherein the spacer layer (408) is SiN, SiOCN, SiOC, SiO2 ([0065]), or SiC. Re Claim 10, Gaul discloses the method according to Claim 1, while further disclosing wherein: after forming the first structure (206, 304, 306, 308, left portion) and the second structure (206, 304, 306, 308, right portion), each structure comprises an interface between a lowest second layer (306a) and an underlying substrate (304; [0062]); and after forming the isolation material (406) between the first structure (206, 304, 306, 308, left portion) and the second structure (206, 304, 306, 308, right portion), the isolation material (406) has an uppermost surface that is lower than each interface (interface is between 306a and 304; [0062]). Re Claim 21, Gaul discloses the method according to Claim 1, while further disclosing wherein the spacer layer (408) and the isolation material (406) prevent the epitaxial material from growing between the first structure (206, 304, 306, 308, left portion) and the second structure (206, 304, 306, 308, right portion) during the selectively growing of the epitaxial material ([0085]). Re Claim 22, Gaul discloses the method according to Claim 1, while further disclosing wherein the method comprises maintaining the spacer layer (408) over the isolation material (406) during the selectively growing of the epitaxial material ([0085]), wherein the spacer layer (408) and the isolation material (406) block epitaxial nucleation between the first structure (206, 304, 306, 308, left portion) and the second structure (206, 304, 306, 308, right portion; [0085]). Re Claim 23, Gaul discloses the method according to Claim 1, while further disclosing wherein the method comprises, after removing the spacer layer (408), selectively removing the first layers (306) with respect to the second layers (308; [0088]) to form channel regions (308; [0088]), and forming a gate structure (1602; [0089]) around the channel regions (308; [0089]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gaul, as applied to Claim 1, further in view of Chouksey et al (US 2022/0199771 A1, hereafter Chouksey). Re Claim 6, Gaul discloses the method according to Claim 1, but does not explicitly disclose wherein the spacer layer (408) includes a first sidewall portion laterally adjacent to the first structure (206, 304, 306, 308, left portion) and a second sidewall portion laterally adjacent to the second structure (206, 304, 306, 308, right portion), and wherein each sidewall portion of the spacer layer (408) forms an internal angle with the lower portion of the spacer layer (408, sidewall portions facing each other) of from 80 to 90 degrees. However, Chouksey discloses a method wherein the spacer layer (614; [0060]) includes a first sidewall portion laterally adjacent to the first structure and a second sidewall portion laterally adjacent to the second structure ([0060], see obviousness statement), and wherein each sidewall portion of the spacer layer (614, sides touching gate stack) forms an internal angle with the lower portion of the spacer layer (614, bottom horizontal portion in contact with insulating 602B) of from 80 to 90 degrees ([0060]). Thus, it would have been obvious to modify the method according to Claim 1 with the limitations taught by Chouksey to blanket deposit the spacer layer (Gaul: 408) followed by etching as a functionally equivalent method of forming the spacer layer (Gaul: 408) as taught by Chouksey ([0060]), such that (for a moment) there would be lower and sidewall portions forming 90-degree angles over the isolation material (Gaul: 406). Allowable Subject Matter Claims 12-17 and 19-20 are allowed. Claims 2-3 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Re Claim 2, the prior art cannot anticipate, or render obvious, the limitations of: while performing the etch process to remove the alternately stacked first and second layers, a first sidewall portion and a second sidewall portion of the spacer layer are reduced in height, in combination with the additionally claimed features of Claim 2. Re Claim 3, the prior art cannot anticipate, or render obvious, the limitations of: after performing the etch process to remove the alternately stacked first and second layers, a first sidewall portion and a second sidewall portion of the spacer layer terminate at upper surfaces distanced from the lower portion by distances of from 10 to 30 nanometers (nm), in combination with the additionally claimed features of Claim 3. Re Claim 11, the prior art cannot anticipate, or render obvious, the limitations of: removing the upper portion of the blocking layer to uncover the upper portion of the spacer layer, in combination with the additionally claimed features of Claim 11. Re Claim 12, the prior art cannot anticipate, or render obvious, the limitations of: wherein performing the etch process to recess the structure comprises removing the lower portion of the blocking layer, in combination with the additionally claimed features of Claim 12. Re Claim 17, the prior art cannot anticipate, or render obvious, the limitations of: planarizing an upper surface of the upper portion of the blocking layer […] removing the upper blocking layer, in combination with the additionally claimed features of Claim 17. In Re Claims 13-16 and Claims 19-20, they are allowable due to their dependence from Claims 12 and 17, respectively. Response to Arguments Applicant’s arguments, see Remarks pg. 2, filed 3/9/2026, with respect to Claims 12 and 17 have been fully considered and are persuasive. The objection of Claim 12 and the rejection of Claim 17 have been withdrawn. As previously stated, the previously indicated allowable subject material of Claim 9 (now included in Claim 1) is no longer deemed allowable in light of the further consideration and reinterpretation of Gaul (see rejection above). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Show 3 earlier events
Oct 07, 2025
Examiner Interview Summary
Oct 07, 2025
Applicant Interview (Telephonic)
Nov 21, 2025
Response Filed
Dec 29, 2025
Final Rejection mailed — §102, §103
Feb 25, 2026
Response after Non-Final Action
Mar 09, 2026
Request for Continued Examination
Mar 16, 2026
Response after Non-Final Action
Jun 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+21.9%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 50 resolved cases by this examiner. Grant probability derived from career allowance rate.

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