Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-4, 7, 9-10, 21-30, and 32-34 are pending in this application.
Applicants elected without traverse of Group 1, Species 1 in the reply filed on July 2, 2025 is acknowledged. All claims directed to the nonelected invention were previously cancelled.
The Examiner notes that claims 1-4, 7, 9-10, 21-30, and 32-34 are examined.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed November 12, 2025. Claims 1-3, 9, 21, 25-28, 30, and 32 are amended. Claims 8 and 31 are cancelled. The Examiner notes that claims 1-4, 7, 9-10, 21-30, and 32-34 are examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 7, 21, 23-27, 30, and 32-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ong (US 2022/0077113 A1).
With respect to claim 1, Ong teaches in Fig. 1A:
An integrated semiconductor device (stacked chip package 100) comprising:
a first semiconductor structure (layer that includes stacked chip 110A) comprising a first integrated circuit (IC) (110A);
a second semiconductor structure (layer that includes stacked chip 110C) stacked above the first semiconductor structure (layer that includes 110A) and comprising a second IC (110C),
the second semiconductor structure (layer that includes 110C) having a first surface (bottom) facing the first semiconductor structure (layer that includes 110A) and a second surface (top) facing away from the first semiconductor structure (layer that includes 110A);
and a thermal dissipation structure (conductive frames 108’, 108’’, 106’, 106’’, and thermal vias within chips (para. 41 “the at least one exposed portion comprises at least one of the plurality of thermal vias”) having a first portion partially through the first IC (110A) and a second portion (108”) fully through the second semiconductor structure and exposed at the second surface of the second semiconductor structure (exposed at interface with 106”),
and a third portion (106’) having a first end (bottom right end) connected to the first portion (thermal vias within 110a) and a second end (top left end) connected to the second portion (108’), the first end and the second end being laterally offset from one another (see Fig. 1A), and
the second portion being outside of the second IC (106’ does not go through 110c).
With respect to claim 3, Ong further teaches:
an interposer (layer that includes 106’ and 110b) stacked between the first semiconductor structure (layer including 110a) and the second semiconductor structure (layer including 110c),
wherein the third portion (106’) is embedded in the interposer (layer that includes 106’and 110b, see annotated Fig. 1A below)
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With respect to claim 7, Ong further teaches:
The integrated semiconductor device of claim 1,
wherein the first portion includes a first via (thermal via within 110a on the right, see annotated Fig. 1A) and the second portion includes a second via (108”).
With respect to claim 21, Ong teaches in Fig. 1a:
An integrated semiconductor device (stacked chip package 100), comprising:
a first semiconductor structure (layer including stacked chip 110a);
a second semiconductor structure (layer including stacked chip 110c) stacked above the first semiconductor structure (layer including 110a) and comprising an integrated circuit (IC) (110c),
the second semiconductor structure (layer including 110c) having a first surface (bottom) facing the first semiconductor structure (layer including 110a) and a second surface (top) facing away from the first semiconductor structure (layer including 110a);
and a thermal dissipation structure (includes 106’, 106”, 108’, 108” and thermal vias within 110a) having a bottom portion partially extending into the first semiconductor structure (thermal vias within 110a) and a top portion fully extending through the second semiconductor structure (108”) and along a sidewall of the IC (110c)
and a routing structure (106’) having a first portion (portion of 106’ in contact with 108”) directly interfacing with the top portion (108”) and a second portion (portion of 106’ in contact with thermal vias within 110a) directly interfacing with the bottom portion (thermal vias within 110a), the first portion and the second portion being separated along a lateral direction (106’ is horizontal), and
a surface of the top portion (top surface of 108”) being coplanar with the second surface (top of layer including 110c) of the second semiconductor structure (layer including 110c).
With respect to claim 23, Ong further teaches:
further comprising an intermediate structure (layer including 106’ and 110b labeled as interposer in annotated Fig. 1a above) coupling the first semiconductor structure (layer including 110a) to the second semiconductor structure (layer including 110c).
With respect to claim 24, Ong further teaches:
wherein the intermediate structure (layer including 106’and 110b labeled as interposer in annotated Fig. 1a above) comprises an interposer (an “interposer” is understood to mean layer that connects between two integrated circuits the layer labeled as interposer has connections to both 110a and 110c and therefore can be considered an interposer).
With respect to claim 25, Ong further teaches:
wherein the routing structure (106’) is fully embedded in the intermediate structure (layer labeled as “interposer” in annotated Fig. 1A above)
With respect to claim 26, Ong further teaches:
wherein the first portion (thermal vias within 110a) and the second portion (108”) are disposed at opposite ends of the routing structure (106’)
With respect to claim 27, Ong teaches:
An integrated semiconductor device (stacked chip package 100), comprising:
a first semiconductor structure (layer including stacked chip 110a, see annotated Fig. 1a above) comprising a first integrated circuit (IC) (110a);
a second semiconductor structure (layer including stacked chip 110c) stacked above the first semiconductor structure (layer including stacked chip 110a) and comprising a second IC (110c),
the second semiconductor structure (layer including 110c) having a bottom surface bonded (bonded through 110b) to the first semiconductor structure (layer including 110a) and a top surface opposite the bottom surface;
and a thermal dissipation structure (106’, 106”, 108’, 108”, and thermal vias within 110a) having a bottom portion partially embedded in the first IC (thermal vias within 110a), a top portion fully extending through the second semiconductor structure (108” that fully extends through the layer including 110c),
and an interconnect routing structure (106’) including a first end (left) and a second end (right) that are in contact with the top portion and the bottom portion, respectively
the top portion being outside of the second IC (108” is within the molding structure of the layer, not 110c) and exposed at the top surface of the second semiconductor structure (exposed at top surface of 108” at interface with 106”),
and the interconnect routing structure (106’) extending horizontally between the top (108”) portion and the bottom portion (thermal vias within 110a) (see Fig. 1A)
With respect to claim 30, Ong further teaches:
the bottom portion includes a first via (thermal via within 110a on the right, see annotated Fig. 1A) in direct contact with the first (right) end of the interconnect routing structure (106’); and
the top portion includes a second via (108”) in direct contact with the second (left) end of the interconnect routing structure (106’);
With respect to claim 32, Ong further teaches:
further comprising an interposer (layer labeled as “interposer” in annotated Fig. 1A above) disposed between the first semiconductor structure (layer including 110a) and the second semiconductor structure (layer including 110c);
wherein the interconnect routing structure (106’) is encapsulated in the interposer (encapsulated within molding material 116 of interposer)
With respect to claim 33, Ong further teaches:
wherein the first portion (thermal vias within 110a) further includes a third via (see annotated Fig. 1A above) connected to the third portion (106’) at a position between the first end and the second end.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4, 9-10, 22, 28-29, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Ong (US 2022/0077113 A1) in view of Yu (US 2019/0333893 A1).
With respect to claim 2, Ong teaches all limitations of claim 1 upon which claim 2 depends, Ong fails to teach:
a cooling structure disposed on the second surface of the second semiconductor structure,
wherein the second portion of the thermal dissipation structure is thermally coupled with the cooling structure.
Yu further teaches in Fig. 11A:
a cooling structure (thermal interface material TIM 128 and heat dissipation lid 130) disposed on the second surface (top) of the second semiconductor structure (fan out tier 101B),
wherein the second portion of the thermal dissipation (vias 126 within 101B) structure is thermally coupled with the cooling structure (coupled to 128 and 130 through redistribution layer 108B).
Ong discloses the claimed invention except for the cooling structure. Yu teaches that it is known to include a cooling structure attached to the heat dissipation structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ong as taught by Yu to include a cooling structure, since Yu states at para. 55 that such a modification would improve thermal performance. See MPEP 2144.
With respect to claim 10, Yu further teaches:
wherein the cooling structure (128 and 130) comprises at least one of a cooling medium (para. 40 “Heat dissipation lid 130 may further have a high thermal conductivity, for example, between about 200 W/m.Math.K to about 400 W/m.Math.K or more, and may be formed using a metal, a metal alloy, grapheme, carbon nanotubes (CNT), and the like.”) or a carrier wafer.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Ong in view of Yu as explained above.
With respect to claim 4, Ong teaches all limitations of claim 1 upon which claim 4 depends, Ong further teaches:
the second semiconductor structure (layer including 110c) comprises a molding layer (molding material 116) around the second IC (110c);
and the second portion (108”) is completely through the molding layer (116).
Ong does not teach that the molding layer is epoxy.
Yu teaches:
an epoxy molding material (para. 47 “Molding compound 124 may include any suitable material such as an epoxy resin,”)
It would have been obvious to the ordinary artisan before the effective filing date of the invention to modify Ong as taught by Yu to use epoxy for a molding material because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 9, Ong teaches all limitations of claim 7 upon which claim 9 depends. Ong does not teach what material the first and second vias are made of and fails to teach:
wherein the first via and the second via each comprise copper.
Yu teaches:
wherein the first via (pillar bump 110) and the second via (126B) each comprise copper (para. 45 “TIVs can also be formed using copper wire stud by copper wire bond processes”).
Yu does not state what material is used to make pillar bump 110. However, the use of copper for metal interconnects is well known in the art. It would be obvious to the ordinary artisan to select copper as the material for the vias of Ong in order to control the thermal and electrical properties of the conductive parts of the device and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 22, Ong teaches all limitations of claim 21 upon which claim 22 depends. Ong fails to teach:
further comprising a cooling medium coupled to the second surface of the second semiconductor structure.
Yu teaches:
further comprising a cooling medium (para. 40 “Heat dissipation lid 130 may further have a high thermal conductivity, for example, between about 200 W/m.Math.K to about 400 W/m.Math.K or more, and may be formed using a metal, a metal alloy, grapheme, carbon nanotubes (CNT), and the like.”) coupled to the second surface (top) of the second semiconductor structure (101B) (coupled through redistribution layer 108B and thermal interface material 128).
Ong discloses the claimed invention except for the cooling medium. Yu teaches that it is known to include a cooling medium attached to the heat dissipation structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ong as taught by Yu to include a cooling medium, since Yu states at para. 55 that such a modification would improve thermal performance. See MPEP 2144.
With respect to claim 28, Ong teaches all limitations of claim 27 upon which claim 28 depends. Ong fails to teach:
further comprising a cooling structure thermally coupled to the top portion of the thermal dissipation structure.
Yu teaches:
further comprising a cooling structure (heat dissipation lid 130 and thermal interface material 128) thermally coupled to the top portion of the thermal dissipation structure (126B).
Ong discloses the claimed invention except for the cooling structure. Yu teaches that it is known to include a cooling structure attached to the heat dissipation structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ong as taught by Yu to include a cooling structure, since Yu states at para. 55 that such a modification would improve thermal performance. See MPEP 2144.
With respect to claim 29, Yu further teaches:
wherein the cooling structure (128 and 130) comprises at least one of a cooling medium (para. 40 “Heat dissipation lid 130 may further have a high thermal conductivity, for example, between about 200 W/m.Math.K to about 400 W/m.Math.K or more, and may be formed using a metal, a metal alloy, grapheme, carbon nanotubes (CNT), and the like.”) or a carrier wafer.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Ong in view of Yu as explained above.
With respect to claim 34, Ong teaches all limitations of claim 30 upon which claim 34 depends. Ong fails to teach:
wherein the top portion further includes a third via in contact with a portion of the interconnect routing structure between the first via and the second via.
Yu teaches in Fig. 13A:
wherein the top portion (101B) further includes a third via in contact with a portion of the interconnect routing structure(108A) between the first via and the second via (see annotated Fig. 13A).
Ong discloses the claimed invention except for the third via. Yu discloses that it is known in the art to provide a third via in the top portion between the first and second via. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Ong with the layout of Yu for the purpose of optimizing the heat dissipation properties and layout of the fanout structure. See MPEP 2144.
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Response to Arguments
Applicant’s arguments with respect to claims 1, 21, and 27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897