DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Prior objection to drawings are withdrawn in view of cancelled claim 12 and amendments to claim 17.
Claim Rejections - 35 USC § 112
Prior rejection of Claims 6, 12 and 20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of applicant’s amendments to claims 6 and 20, and cancellation of claim 12.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-9, 13 and 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), and further in view of Wu et al. (US 2021/0193453 A1, newly cited) and Wang et al. (US 2021/0313292 A1, newly cited).
Re Claim 1, Kim teaches a method for forming a semiconductor package, comprising:
forming a first bonding structure (40, Fig. 4, para [0070]) over the first substrate (20, Fig. 4, para [0070]);
forming a second bonding structure (110, Figs. 2 and 5, para [0062]) over a second substrate of a second wafer (10, Fig. 2, para [0062]);
trimming the second substrate (see Fig. 6), so that a first width of the first substrate is greater than a second width of the second substrate (width of substrate 20 is greater than width of substrate 10, after the trimming process, see Fig. 6);
attaching the second wafer to the first wafer (see Figs. 5 and 6) via the first bonding structure (40) and the second bonding structure (110);
thinning the second wafer (10) until a through-substrate via (120, Fig. 7, para [0062], the via can be considered only the opening or a combination of the opening and the metallization filling the opening) in the second substrate is exposed (see Fig. 7);
performing a process on the second wafer (patterning the passivation layer 150 to form a gap in the layer 150, where pads 134 will be formed, paras [0097] – [0098], Fig. 8).
Kim does not disclose the following:
forming a first alignment mark in a first substrate of a first wafer;
wherein the first alignment mark is laterally offset from an edge of the second bonding structure;
Relater art, Wu teaches an embodiment where there are first alignment marks (106, Fig. 1B, para [0022]) in a first substrate of a first wafer (first wafer 102, Fig. 1B, para [0022]), wherein the first alignment mark (102) is laterally offset from an edge of the second bonding structure (second wafer 104, see Fig. 1B). Wu teaches that the alignment marks are used for patterning equipment accurately over the first wafer (para [0022]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Wu and implement the alignment marks into the first substrate of Kim, because the alignment marks will help in aligning the second wafer of Kim on to the first wafer and also help in patterning components accurately on the second wafer, for example patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8.
Additionally, Kim does not disclose performing a photolithography process on the second wafer using the first alignment mark. However, Kim modified by Wu discloses a patterning step on the second wafer using the alignment marks (patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8, see above). Kim modified by Wu does not disclose how the patterning step was performed.
Related art, Wang discloses that photolithography can be performed to pattern the insulating layer (131a, Figs. 1a-1b, para [0023]) so that conductive elements could be formed (Figs. 1a-1b, para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to perform the patterning step of Kim modified by Wu, using the photolithography process, as taught by Wang. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 2, Kim modified by Wu and Wang teaches the method as claimed in claim 1, wherein the first substrate (20, Kim) comprises a central portion (CR, Fig. 8, Kim) and a peripheral portion (ER, Fig. 8, Kim) surrounding the central portion (CR, Fig. 8, Kim), the second substrate (10, Kim) is attached to the central portion of the first substrate (see Fig. 8, Kim) and the first alignment mark (106, Fig. 1B, Wu) is formed in the peripheral portion of the first substrate (106 is formed in peripheral region, see Fig. 1B of Wu, which is equivalent to the ER region of Kim).
Re Claim 6, Kim modified by Wu and Wang teaches the method as claimed in claim 1, wherein a thickness of the thinned second wafer (10, Kim) is in a range from about 3 μm to about 60 μm (substrate 10 can have a thickness of several tens of μm after thinning, para [0093]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the thickness and arrive at the claimed range. With respect to the limitations of claim 6, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Re Claim 7, Kim modified by Wu and Wang teaches the method as claimed in claim 1, wherein the first substrate (20, Kim) comprises a central portion (CR, Fig. 8, Kim) and a peripheral portion (ER, Fig. 8, Kim) surrounding the central portion (see Fig. 1, Kim), and the second substrate (10, Kim) overlaps the central portion of the first substrate (CR, Fig. 8, Kim) vertically without overlapping the first alignment mark vertically (see Fig. 8 of Kim in view of Fig. 1B of Wu, where the alignment mark 106 does not overlap with the second wafer 104 in Fig. 1B of Wu, and they will be placed in the corresponding peripheral ER region of Kim and not overlapping with the CR region vertically).
Re Claim 8, Kim modified by Wu and Wang teaches the method as claimed in claim 1, further comprising forming a second alignment mark in a peripheral portion of the first substrate, and the first alignment mark and the second alignment mark are symmetrically formed relative to a central axis of the first substrate (see Fig. 1B of Wu, where the 1st and 2nd alignment marks 106 are symmetrically formed relative to a central axis of the 1st wafer 102).
Re Claim 9, Kim modified by Wu and Wang teaches the method as claimed in claim 8, wherein a distance between the first alignment mark and the second alignment mark is greater than the second width of the second substrate (since the 1st and 2nd alignment marks will be placed in a diametrically opposite peripheral regions, which is equivalent to the ER regions of Kim, the distance between the two alignment marks will be greater than the width of the second substrate 10 of Kim, since the width of second substrate 10 is equal to the width of the CR region, see Fig. 8 of Kim).
Re Claim 13, Kim teaches a method for forming a semiconductor package, comprising:
a peripheral portion (ER, Fig. 5) of a first substrate of a first wafer (20, Fig. 5, para [0070]);
bonding a second wafer (10, Fig. 2, para [0062]) to a central portion of the first substrate (CR, Fig. 5), wherein the central portion is surrounded by the peripheral portion (see 5 and para [0056]);
depositing a passivation structure (150, Fig. 8, para [0097]) over a second substrate of the second wafer (10, Kim);
performing a process on the second wafer to form a gap in the passivation structure (patterning the passivation layer 150 to form a gap in the layer 150, where pads 134 will be formed, paras [0097] – [0098], Fig. 8);
filling a conductive material in the gap to form a first-side contact feature (pads 134, Fig. 8, para [0098]);
wherein the first-side contact feature (134) is in contact with a through-substrate via in the second substrate (120, para [0062], Fig. 8).
Kim does not disclose the following:
forming an alignment mark in a peripheral portion of a first substrate of a first wafer;
wherein, in a top-view, the alignment mark is located outside a periphery of the second wafer;
Relater art, Wu teaches an embodiment where there are first alignment marks (106, Fig. 1B, para [0022]) in a first substrate of a first wafer (first wafer 102, Fig. 1B, para [0022]), wherein in a top-view, the alignment mark (106) is located outside a periphery of the second wafer (second wafer 104, see Fig. 1B). Wu teaches that the alignment marks are used for patterning equipment accurately over the first wafer (para [0022]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Wu and implement the alignment marks into the first substrate of Kim, because the alignment marks will help in aligning the second wafer of Kim on to the first wafer and also help in patterning components accurately on the second wafer, for example patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8.
Additionally, Kim does not disclose performing a photolithography process on the second wafer using the first alignment mark. However, Kim modified by Wu discloses a patterning step on the second wafer using the alignment marks (patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8, see above). Kim modified by Wu does not disclose how the patterning step was performed.
Related art, Wang discloses that photolithography can be performed to pattern the insulating layer (131a, Figs. 1a-1b, para [0023]) so that conductive elements could be formed (Figs. 1a-1b, para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to perform the patterning step of Kim modified by Wu, using the photolithography process, as taught by Wang. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 17, Kim teaches a method for forming a semiconductor package, comprising:
a peripheral portion (ER, Fig. 5) of a first substrate of a first wafer (20, Fig. 5, para [0070]), wherein the peripheral portion surrounds a central portion (CR, Fig. 5) of the first substrate (see Fig. 5 and para [0056]);
attaching a second wafer (10, Fig. 2, para [0062]) to the central portion of the first substrate (see Fig. 5); and
performing a process on the second wafer (patterning the passivation layer 150 to form a gap in the layer 150, where pads 134 will be formed, paras [0097] – [0098], Fig. 8).
Kim does not disclose the following:
forming at least two alignment marks in a peripheral portion of a first substrate of a first wafer;
such that in atop-view, the at least two alignment marks are positioned radially outward of the second wafer;
Relater art, Wu teaches an embodiment where there are at least two alignment marks (106, Fig. 1B, para [0022]) in a peripheral portion of a first substrate of a first wafer (first wafer 102, Fig. 1B, para [0022]), wherein in a top-view, the two alignment marks (106) are positioned radially outward of the second wafer (second wafer 104, see Fig. 1B). Wu teaches that the alignment marks are used for patterning equipment accurately over the first wafer (para [0022]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Wu and implement the alignment marks into the first substrate of Kim, because the alignment marks will help in aligning the second wafer of Kim on to the first wafer and also help in patterning components accurately on the second wafer, for example patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8.
Additionally, Kim does not disclose performing a photolithography process on the second wafer using the first alignment mark. However, Kim modified by Wu discloses a patterning step on the second wafer using the alignment marks (patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8, see above). Kim modified by Wu does not disclose how the patterning step was performed.
Related art, Wang discloses that photolithography can be performed to pattern the insulating layer (131a, Figs. 1a-1b, para [0023]) so that conductive elements could be formed (Figs. 1a-1b, para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to perform the patterning step of Kim modified by Wu, using the photolithography process, as taught by Wang. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 18, Kim modified by Wu and Wang teaches the method as claimed in claim 17, wherein the first wafer further comprises a first bonding structure (40, Fig. 7, para [0070], Kim), the second wafer further comprises a second bonding structure (110, Figs. 7, para [0062], Kim) in contact with the first bonding structure (see Fig. 8, Kim), and a width of the first bonding structure is different from a width of the second bonding structure (width of 40 is greater than width of 110, see Fig. 7, Kim).
Re Claim 19, Kim modified by Wu and Wang teaches the method as claimed in claim 18, wherein the at least two alignment marks overlap the first bonding structure (40, Fig. 7, Kim) vertically without overlapping the second bonding structure (110, Fig. 7, Kim) vertically (the alignment marks as disclosed by Wu are formed in the peripheral portion as explained above, which is equivalent to the ER region of Fig. 7 of Kim, which overlaps with 40 of Kim but does not overlap with the 110 of Kim, vertically).
Re Claim 20, Kim modified by Wu and Wang teaches the method as claimed in claim 17, further comprising thinning the second wafer (10, Figs. 6-7, Kim), wherein a thickness of the thinned second wafer (10, Kim) is greater than 20 μm (substrate 10 can have a thickness of several tens of μm after thinning, para [0093]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the thickness and arrive at the claimed range. With respect to the limitations of claim 20, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Re Claim 21, Kim modified by Wu and Wang teaches the method as claimed in claim 17, wherein an imaginary straight line drawn between two of the at least two alignment marks (106, Fig. 1B, Wu) passes through a center point of the second wafer (second wafer 104, see Fig. 1B of Wu, similar to second wafer 10 of Kim).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, newly cited) and Wang et al. (US 2021/0313292 A1, newly cited), and further in view of Hellig et al. (US 6673635 B1, of record).
Re Claim 3, Kim modified by Wu and Wang teaches the method as claimed in claim 1, but does not disclose that the height of the first alignment mark is in a range from about 50 nm to about 5000 nm.
However, in a similar semiconductor art, Hellig teaches that an optimal height of an alignment mark can be 120 nm (Col. 1, lines 41-44).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the height and arrive at the claimed range. With respect to the limitations of claim 3, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, newly cited) and Wang et al. (US 2021/0313292 A1, newly cited), and further in view of Chen et al. (US 2019/0393159 A1, of record).
Re Claim 4, Kim modified by Wu and Wang teaches the method as claimed in claim 1, but does not disclose that a width of the first alignment mark is in a range from about 0.5 μm to about 10 μm.
However, in a similar semiconductor art, Chen teaches that a width of an alignment mark (AM2, Fig. 5, para [0042]) can be 2.5 μm (para [0042]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the width and arrive at the claimed range. With respect to the limitations of claim 4, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, newly cited) and Wang et al. (US 2021/0313292 A1, newly cited), and further in view of Hsu et al. (US 2007/0087467 A1, of record).
Re Claim 5, Kim modified by Wu and Wang teaches the method as claimed in claim 1, but does not disclose that a distance between an edge of the first substrate and an edge of the first alignment mark is in a range from about 0.5 mm to about 4 mm.
However, in a similar semiconductor art, Hsu teaches that an alignment mark can be disposed at a distance of about 2-3 mm from the edge of the wafer (Fig. 3A, para [0018]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the distance and arrive at the claimed range. With respect to the limitations of claim 5, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Re Claim 15, Kim modified by Wu and Wang teaches the method as claimed in claim 13, but does not disclose that a distance between an edge of the first substrate and an edge of the first alignment mark is in a range from about 0.5 mm to about 4 mm.
However, in a similar semiconductor art, Hsu teaches that an alignment mark can be disposed at a distance of about 2-3 mm from the edge of the wafer (Fig. 3A, para [0018]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the distance and arrive at the claimed range. With respect to the limitations of claim 15, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Claims 10-11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, newly cited) and Wang et al. (US 2021/0313292 A1, newly cited), and further in view of Lee et al. (US 2018/0138164 A1, of record).
Re Claim 10, Kim modified by Wu and Wang teaches the method as claimed in claim 1, further comprising forming a first-side contact feature (134, Fig. 8, para [0098], Kim) over the second substrate (10, Kim).
Kim does not disclose attaching a third wafer to the second wafer but does disclose the first-side contact feature (134), where a third substrate can be attached.
In a related art Lee teaches that a third substrate (300, Figs. 18-19, paras [0119] – [0124]) can be attached to the second substrate (200tw, Fig. 18, para [0125]), forming a stacked semiconductor device.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to attach a third substrate to the second substrate of Kim, as disclosed by Lee, which would result in a stacked architecture of a semiconductor device with multiple functionalities while reducing footprint and lowering costs.
Re Claim 11, Kim modified by Wu, Wang and Lee teaches the method as claimed in claim 10, further comprising:
removing the first wafer (see Fig. 12, para [0114], Kim) to expose the second bonding structure (110, Kim) of the second wafer (10, Kim, see paras [0114] – [0116]);
forming a second-side contact feature (metallization filling within the via 120, Figs. 8 and 12, Kim) in the second bonding structure (110, Kim), wherein the second-side contact feature (metallization filling within the via 120, Figs. 8 and 12, Kim) and the first-side contact feature (134, Kim) are located on opposite sides of the second substrate (see Figs. 8 and 12, Kim);
forming an under bump metallization feature (132, Figs. 8 and 12, para [0065], Kim) over the second-side contact feature (metallization filling within the via 120, Figs. 8 and 12, Kim); and
forming a bump feature (142, Figs. 8 and 12, para [0067], Kim) over the under bump metallization feature (132, Kim).
Re Claim 16, Kim modified by Wu and Wang teaches the method as claimed in claim 13, but does not disclose attaching a third wafer to the second wafer via the first-side contact feature. Kim does disclose the first-side contact feature (134), where a third substrate can be attached.
In a related art Lee teaches that a third substrate (300, Figs. 18-19, paras [0119] – [0124]) can be attached to the second substrate (200tw, Fig. 18, para [0125]), forming a stacked semiconductor device.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to attach a third substrate to the second substrate of Kim, as disclosed by Lee, which would result in a stacked architecture of a semiconductor device with multiple functionalities while reducing footprint and lowering costs.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, newly cited) and Wang et al. (US 2021/0313292 A1, newly cited), and further in view of Broekaart et al. (US 2011/0097874 A1, of record).
Re Claim 14, Kim modified by Wu and Wang teaches the method as claimed in claim 13, further comprising trimming an edge portion of the second substrate (10, Kim, see Figs. 5-6), a height of the edge portion is in a range from about 50 μm to about 500 μm (the height of the edge portion is equal to the original thickness of the second substrate 10 in Fig. 6 of Kim, which can be several hundreds of μm, para [0093], within the claimed range).
Kim does not disclose that a width of the edge portion is in a range from about 0.5 mm to about 20 mm.
However, in a similar semiconductor art, Broekaart teaches that a width of the edge portion or the trimming width can be in the range 2 mm to 10 mm (see Fig. 2D, para [0038]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the width and arrive at the claimed range. With respect to the limitations of claim 14, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Response to Arguments
Applicant’s arguments with respect to claims 1, 13 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claims 1, 13 and 17, applicant argued that the primary reference Kim et al. (US 2015/0221517 A1, of record), “is entirely silent regarding any alignment marks and any photolithography processes” and “since Kim fails to disclose or even contemplate an alignment mark, there is no basis or rationale to modify Kim to include one.” Examiner respectfully disagrees with the applicant. Kim teaches a patterning process on the second wafer (see rejection of claims 1, 13 and 17 above) and it is well-known in the art to accurately perform these patterning processes using alignment marks as shown by Wu et al. (US 2021/0193453 A1, newly cited). Additionally, photolithography is a well-known technique for performing these patterning processes as evidenced by Wang et al. (US 2021/0313292 A1, newly cited).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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