DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/3/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 8-9, 13 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), and further in view of Wu et al. (US 2021/0193453 A1, of record), Wang et al. (US 2021/0313292 A1, of record), and Chiang et al. (US 2019/0148130 A1, newly cited).
Re Claim 1, Kim teaches a method for forming a semiconductor package, comprising:
forming a first bonding structure (40, Fig. 4, para [0070]) over the first substrate (20, Fig. 4, para [0070]);
forming a second bonding structure (110, Figs. 2 and 5, para [0062]) over a second substrate of a second wafer (10, Fig. 2, para [0062]);
trimming the second substrate (see Fig. 6), so that a first width of the first substrate is greater than a second width of the second substrate (width of substrate 20 is greater than width of substrate 10, after the trimming process, see Fig. 6);
attaching the second wafer to the first wafer (see Figs. 5 and 6) via the first bonding structure (40) and the second bonding structure (110);
thinning the second wafer (10) until a through-substrate via (120, Fig. 7, para [0062], the via can be considered only the opening or a combination of the opening and the metallization filling the opening) in the second substrate is exposed (see Fig. 7);
performing a process on the second wafer (patterning the passivation layer 150 to form a gap in the layer 150, where pads 134 will be formed, paras [0097] – [0098], Fig. 8).
Kim does not disclose the following:
forming a first alignment mark in a first substrate of a first wafer;
wherein the first alignment mark is laterally offset from an edge of the second bonding structure;
Relater art, Wu teaches an embodiment where there are first alignment marks (106, Fig. 1B, para [0022]) in a first substrate of a first wafer (first wafer 102, Fig. 1B, para [0022]), wherein the first alignment mark (102) is laterally offset from an edge of the second bonding structure (second wafer 104, see Fig. 1B). Wu teaches that the alignment marks are used for patterning equipment accurately over the first wafer (para [0022]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Wu and implement the alignment marks into the first substrate of Kim, because the alignment marks will help in aligning the second wafer of Kim on to the first wafer and also help in patterning components accurately on the second wafer, for example patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8.
Additionally, Kim does not disclose performing a photolithography process on the second wafer using the first alignment mark. However, Kim modified by Wu discloses a patterning step on the second wafer using the alignment marks (patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8, see above). Kim modified by Wu does not disclose how the patterning step was performed.
Related art, Wang discloses that photolithography can be performed to pattern the insulating layer (131a, Figs. 1a-1b, para [0023]) so that conductive elements could be formed (Figs. 1a-1b, para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to perform the patterning step of Kim modified by Wu, using the photolithography process, as taught by Wang. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Kim also does not disclose that the second wafer is attached to the first wafer after the second substrate of the second wafer is trimmed. Kim shows that the second wafer (10) and the first wafer (20) were bonded (Figs. 5-6) before the second substrate of the second wafer was trimmed (10, Fig. 6).
However, in a related semiconductor art, Chiang discloses the formation of a similar bonded wafers (wafers 100 and 200, Fig. 1H, paras [0023], similar to the bonded device of Fig. 7 of Kim), where the second wafer 100 was trimmed (Figs. 1A-1D) before it was bonded to first wafer 200, such that a first width of the first wafer (200) is greater than a second width of the second wafer (100), satisfying the claim limitation.
One of ordinary skill in the art would realize that there are two art-recognized alternative methods of trimming the second wafer – either it can be trimmed before being bonded to the first wafer as shown by Kim, or the second wafer can be bonded after it has been trimmed as disclosed by Chiang. Therefore, a person of ordinary skill has good reason to pursue both the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Re Claim 2, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 1, wherein the first substrate (20, Kim) comprises a central portion (CR, Fig. 8, Kim) and a peripheral portion (ER, Fig. 8, Kim) surrounding the central portion (CR, Fig. 8, Kim), the second substrate (10, Kim) is attached to the central portion of the first substrate (see Fig. 8, Kim) and the first alignment mark (106, Fig. 1B, Wu) is formed in the peripheral portion of the first substrate (106 is formed in peripheral region, see Fig. 1B of Wu, which is equivalent to the ER region of Kim).
Re Claim 6, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 1, but does not explicitly state that a thickness of the thinned second wafer (10, Kim) is in a range from about 3 μm to about 60 μm.
Kim states that the substrate 10 can have a thickness of several tens of μm after thinning (para [0093]). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the thickness of each substrate such that the devices can be stacked to form a compact multi-functional device package. With respect to the limitations of claim 6, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Re Claim 8, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 1, further comprising forming a second alignment mark in a peripheral portion of the first substrate, and the first alignment mark and the second alignment mark are symmetrically formed relative to a central axis of the first substrate (see Fig. 1B of Wu, where the 1st and 2nd alignment marks 106 are symmetrically formed relative to a central axis of the 1st wafer 102).
Re Claim 9, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 8, wherein a distance between the first alignment mark and the second alignment mark is greater than the second width of the second substrate (since the 1st and 2nd alignment marks will be placed in a diametrically opposite peripheral regions, which is equivalent to the ER regions of Kim, the distance between the two alignment marks will be greater than the width of the second substrate 10 of Kim, since the width of second substrate 10 is equal to the width of the CR region, see Fig. 8 of Kim).
Re Claim 13, Kim teaches a method for forming a semiconductor package, comprising:
a peripheral portion (ER, Fig. 5) of a first substrate of a first wafer (20, Fig. 5, para [0070]);
trimming an edge portion of a second substrate of a second wafer (10, see Figs. 5-6),
bonding the second wafer (10, Fig. 2, para [0062]) to a central portion of the first substrate (CR, Fig. 5), wherein the central portion is surrounded by the peripheral portion (see 5 and para [0056]);
depositing a passivation structure (150, Fig. 8, para [0097]) over the second substrate of the second wafer (10, Kim);
performing a process on the second wafer to form a gap in the passivation structure (patterning the passivation layer 150 to form a gap in the layer 150, where pads 134 will be formed, paras [0097] – [0098], Fig. 8);
filling a conductive material in the gap to form a first-side contact feature (pads 134, Fig. 8, para [0098]);
wherein the first-side contact feature (134) is in contact with a through-substrate via in the second substrate (120, para [0062], Fig. 8).
Kim does not disclose the following:
forming an alignment mark in a peripheral portion of a first substrate of a first wafer;
wherein, in a top-view, the alignment mark is located outside a periphery of the second wafer;
Relater art, Wu teaches an embodiment where there are first alignment marks (106, Fig. 1B, para [0022]) in a first substrate of a first wafer (first wafer 102, Fig. 1B, para [0022]), wherein in a top-view, the alignment mark (106) is located outside a periphery of the second wafer (second wafer 104, see Fig. 1B). Wu teaches that the alignment marks are used for patterning equipment accurately over the first wafer (para [0022]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Wu and implement the alignment marks into the first substrate of Kim, because the alignment marks will help in aligning the second wafer of Kim on to the first wafer and also help in patterning components accurately on the second wafer, for example patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8.
Additionally, Kim does not disclose performing a photolithography process on the second wafer using the first alignment mark. However, Kim modified by Wu discloses a patterning step on the second wafer using the alignment marks (patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8, see above). Kim modified by Wu does not disclose how the patterning step was performed.
Related art, Wang discloses that photolithography can be performed to pattern the insulating layer (131a, Figs. 1a-1b, para [0023]) so that conductive elements could be formed (Figs. 1a-1b, para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to perform the patterning step of Kim modified by Wu, using the photolithography process, as taught by Wang. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Kim also does not disclose that the second wafer is bonded to the first wafer after an edge portion of the second substrate of the second wafer is trimmed. Kim shows that the second wafer (10) and the first wafer (20) were bonded (Figs. 5-6) before the second substrate of the second wafer was trimmed (10, Fig. 6).
However, in a related semiconductor art, Chiang discloses the formation of a similar bonded wafers (wafers 100 and 200, Fig. 1H, paras [0023], similar to the bonded device of Fig. 7 of Kim), wherein an edge portion of the second wafer 100 was trimmed (Figs. 1A-1D) before it was bonded to first wafer 200, such that a first width of the first wafer (200) is greater than a second width of the second wafer (100), satisfying the claim limitation.
One of ordinary skill in the art would realize that there are two art-recognized alternative methods of trimming the second wafer – either it can be trimmed before being bonded to the first wafer as shown by Kim, or the second wafer can be bonded after it has been trimmed as disclosed by Chiang. Therefore, a person of ordinary skill has good reason to pursue both the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Re Claim 17, Kim teaches a method for forming a semiconductor package, comprising:
a peripheral portion (ER, Fig. 5) of a first substrate of a first wafer (20, Fig. 5, para [0070]), wherein the peripheral portion surrounds a central portion (CR, Fig. 5) of the first substrate (see Fig. 5 and para [0056]);
trimming an edge portion of a second substrate of a second wafer (10, see Figs. 5-6),
attaching the second wafer (10, Fig. 2, para [0062]) to the central portion of the first substrate (see Fig. 5); and
performing a process on the second wafer (patterning the passivation layer 150 to form a gap in the layer 150, where pads 134 will be formed, paras [0097] – [0098], Fig. 8).
Kim does not disclose the following:
forming at least two alignment marks in a peripheral portion of a first substrate of a first wafer;
such that in atop-view, the at least two alignment marks are positioned radially outward of an inner portion of the second substrate of the second wafer;
Relater art, Wu teaches an embodiment where there are at least two alignment marks (106, Fig. 1B, para [0022]) in a peripheral portion of a first substrate of a first wafer (first wafer 102, Fig. 1B, para [0022]), wherein in a top-view, the two alignment marks (106) are positioned radially outward of an inner portion of the second substrate of the second wafer (second wafer 104, see Fig. 1B). Wu teaches that the alignment marks are used for patterning equipment accurately over the first wafer (para [0022]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Wu and implement the alignment marks into the first substrate of Kim, because the alignment marks will help in aligning the second wafer of Kim on to the first wafer and also help in patterning components accurately on the second wafer, for example patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8.
Additionally, Kim does not disclose performing a photolithography process on the second wafer using the first alignment mark. However, Kim modified by Wu discloses a patterning step on the second wafer using the alignment marks (patterning the protective layer 150 of the second wafer 10 in Fig. 8 of Kim, to expose TSVs 120 and form the surface pads 134 in the device in Fig. 8, see above). Kim modified by Wu does not disclose how the patterning step was performed.
Related art, Wang discloses that photolithography can be performed to pattern the insulating layer (131a, Figs. 1a-1b, para [0023]) so that conductive elements could be formed (Figs. 1a-1b, para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to perform the patterning step of Kim modified by Wu, using the photolithography process, as taught by Wang. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Kim also does not disclose that the second wafer is bonded to the first wafer after an edge portion of the second substrate of the second wafer is trimmed. Kim shows that the second wafer (10) and the first wafer (20) were bonded (Figs. 5-6) before the second substrate of the second wafer was trimmed (10, Fig. 6).
However, in a related semiconductor art, Chiang discloses the formation of a similar bonded wafers (wafers 100 and 200, Fig. 1H, paras [0023], similar to the bonded device of Fig. 7 of Kim), wherein an edge portion of the second wafer 100 was trimmed (Figs. 1A-1D) before it was bonded to first wafer 200, such that a first width of the first wafer (200) is greater than a second width of the second wafer (100), satisfying the claim limitation.
One of ordinary skill in the art would realize that there are two art-recognized alternative methods of trimming the second wafer – either it can be trimmed before being bonded to the first wafer as shown by Kim, or the second wafer can be bonded after it has been trimmed as disclosed by Chiang. Therefore, a person of ordinary skill has good reason to pursue both the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Re Claim 18, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 17, wherein the first wafer further comprises a first bonding structure (40, Fig. 7, para [0070], Kim), the second wafer further comprises a second bonding structure (110, Figs. 7, para [0062], Kim) in contact with the first bonding structure (see Fig. 8, Kim), and a width of the first bonding structure is different from a width of the second bonding structure (width of 40 is greater than width of 110, see Fig. 7, Kim).
Re Claim 19, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 18, wherein the at least two alignment marks overlap the first bonding structure (40, Fig. 7, Kim) vertically without overlapping the second bonding structure (110, Fig. 7, Kim) vertically (the alignment marks as disclosed by Wu are formed in the peripheral portion as explained above, which is equivalent to the ER region of Fig. 7 of Kim, which overlaps with 40 of Kim but does not overlap with the 110 of Kim, vertically).
Re Claim 20, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 17, further comprising thinning the second wafer (10, Figs. 6-7, Kim), but does not explicitly state that a thickness of the thinned second wafer (10, Kim) is greater than 20 μm.
Kim states that the substrate 10 can have a thickness of several tens of μm after thinning (para [0093]). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the thickness of each substrate such that the devices can be stacked to form a compact multi-functional device package. With respect to the limitations of claim 6, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, of record), Wang et al. (US 2021/0313292 A1, of record), and Chiang et al. (US 2019/0148130 A1, newly cited) as applied to claim 1 above, and further in view of Hellig et al. (US 6673635 B1, of record).
Re Claim 3, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 1, but does not disclose that the height of the first alignment mark is in a range from about 50 nm to about 5000 nm.
However, in a similar semiconductor art, Hellig teaches that an optimal height of an alignment mark can be 120 nm (Col. 1, lines 41-44).
It would have been obvious to one of ordinary skill in the art, at the time of invention, absent unexpected results, to modify the semiconductor device of Kim modified by Wu, Wang and Chiang, by incorporating the height of the alignment mark as disclosed by Hellig. This would have been obvious in order to simplify the manufacturing process by using a known height of the alignment mark that would aid in the alignment of the wafers, ensuring operational success. With respect to the limitations of claim 3, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, of record), Wang et al. (US 2021/0313292 A1, of record), and Chiang et al. (US 2019/0148130 A1, newly cited), as applied to claim 1 above, and further in view of Chen et al. (US 2019/0393159 A1, of record).
Re Claim 4, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 1, but does not disclose that a width of the first alignment mark is in a range from about 0.5 μm to about 10 μm.
However, in a similar semiconductor art, Chen teaches that a width of an alignment mark (AM2, Fig. 5, para [0042]) can be 2.5 μm (para [0042]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, absent unexpected results, to modify the semiconductor device of Kim modified by Wu, Wang and Chiang, by incorporating the width of the alignment mark as disclosed by Chen. This would have been obvious in order to simplify the manufacturing process by using a known width of the alignment mark that would aid in the alignment of the wafers, ensuring operational success. With respect to the limitations of claim 4, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, of record), Wang et al. (US 2021/0313292 A1, of record), and Chiang et al. (US 2019/0148130 A1, newly cited), and further in view of Hsu et al. (US 2007/0087467 A1, of record).
Re Claim 5, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 1, but does not disclose that a distance between an edge of the first substrate and an edge of the first alignment mark is in a range from about 0.5 mm to about 4 mm.
However, in a similar semiconductor art, Hsu teaches that an alignment mark can be disposed at a distance of about 2-3 mm from the edge of the wafer (Fig. 3A, para [0018]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, absent unexpected results, to modify the semiconductor device of Kim modified by Wu, Wang and Chiang, by incorporating the edge-distance of the alignment mark as disclosed by Hsu. This would have been obvious in order to simplify the manufacturing process by using a known edge-distance of the alignment mark that would aid in the alignment of the wafers, ensuring operational success. With respect to the limitations of claim 5, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Re Claim 15, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 13, but does not disclose that a distance between an edge of the first substrate and an edge of the first alignment mark is in a range from about 0.5 mm to about 4 mm.
However, in a similar semiconductor art, Hsu teaches that an alignment mark can be disposed at a distance of about 2-3 mm from the edge of the wafer (Fig. 3A, para [0018]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the distance and arrive at the claimed range. With respect to the limitations of claim 15, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Claims 10-11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, of record), Wang et al. (US 2021/0313292 A1, of record), and Chiang et al. (US 2019/0148130 A1, newly cited), and further in view of Lee et al. (US 2018/0138164 A1, of record).
Re Claim 10, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 1, further comprising forming a first-side contact feature (134, Fig. 8, para [0098], Kim) over the second substrate (10, Kim).
Kim does not disclose attaching a third wafer to the second wafer but does disclose the first-side contact feature (134), where a third substrate can be attached.
In a related art Lee teaches that a third substrate (300, Figs. 18-19, paras [0119] – [0124]) can be attached to the second substrate (200tw, Fig. 18, para [0125]), forming a stacked semiconductor device.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to attach a third substrate to the second substrate of Kim, as disclosed by Lee, which would result in a stacked architecture of a semiconductor device with multiple functionalities while reducing footprint and lowering costs.
Re Claim 11, Kim modified by Wu, Wang, Chiang and Lee teaches the method as claimed in claim 10, further comprising:
removing the first wafer (see Fig. 12, para [0114], Kim) to expose the second bonding structure (110, Kim) of the second wafer (10, Kim, see paras [0114] – [0116]);
forming a second-side contact feature (metallization filling within the via 120, Figs. 8 and 12, Kim) in the second bonding structure (110, Kim), wherein the second-side contact feature (metallization filling within the via 120, Figs. 8 and 12, Kim) and the first-side contact feature (134, Kim) are located on opposite sides of the second substrate (see Figs. 8 and 12, Kim);
forming an under bump metallization feature (132, Figs. 8 and 12, para [0065], Kim) over the second-side contact feature (metallization filling within the via 120, Figs. 8 and 12, Kim); and
forming a bump feature (142, Figs. 8 and 12, para [0067], Kim) over the under bump metallization feature (132, Kim).
Re Claim 16, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 13, but does not disclose attaching a third wafer to the second wafer via the first-side contact feature. Kim does disclose the first-side contact feature (134), where a third substrate can be attached.
In a related art Lee teaches that a third substrate (300, Figs. 18-19, paras [0119] – [0124]) can be attached to the second substrate (200tw, Fig. 18, para [0125]), forming a stacked semiconductor device.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to attach a third substrate to the second substrate of Kim, as disclosed by Lee, which would result in a stacked architecture of a semiconductor device with multiple functionalities while reducing footprint and lowering costs.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221517 A1, of record), Wu et al. (US 2021/0193453 A1, of record), Wang et al. (US 2021/0313292 A1, of record), and Chiang et al. (US 2019/0148130 A1, newly cited), and further in view of Broekaart et al. (US 2011/0097874 A1, of record).
Re Claim 14, Kim modified by Wu, Wang and Chiang teaches the method as claimed in claim 13, wherein a height of the edge portion is in a range from about 50 μm to about 500 μm (the height of the edge portion is equal to the original thickness of the second substrate 10 in Fig. 6 of Kim, which can be several hundreds of μm, para [0093], within the claimed range).
Kim does not disclose that a width of the edge portion is in a range from about 0.5 mm to about 20 mm.
However, in a similar semiconductor art, Broekaart teaches that a width of the edge portion or the trimming width can be in the range 2 mm to 10 mm (see Fig. 2D, para [0038]).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the width and arrive at the claimed range. With respect to the limitations of claim 14, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed range would have been obvious to one of ordinary skill in the art.
Rejection 2
Claim Rejections - 35 USC § 103
Claims 1 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2021/0134663 A1, newly cited), and further in view of Wu et al. (US 2021/0193453 A1, of record) and Wang et al. (US 2021/0313292 A1, of record).
Re Claim 1, Huang teaches a method for forming a semiconductor package (Fig. 15A), comprising:
forming a first bonding structure (214, Fig. 15A, para [0043]) over the first substrate (101b, Fig. 15A, paras [0043] and [0015]);
forming a second bonding structure (114, Fig. 15A, paras [0030] and [0016] – [0018], also see Fig. 11) over a second substrate of a second wafer (101a, Fig. 15A, paras [0043] and [0015], also see Fig. 11);
trimming the second substrate (see Figs. 8-9), so that a first width of the first substrate is greater than a second width of the second substrate (width of substrate 101b is greater than width of substrate 101a, after the trimming process, see Fig. 15A);
attaching the second wafer to the first wafer (see Figs. 12-14) via the first bonding structure (214) and the second bonding structure (114);
thinning the second wafer (101a) until a through-substrate in the second substrate is exposed (see Figs. 12-13);
performing a process on the second wafer (patterning the capping layer 160 to form a gap in the layer 160, so that top surfaces of the vias within wafer substrate 101a are exposed, see Fig. 15A, para [0043]).
Huang does not disclose the following:
forming a first alignment mark in a first substrate of a first wafer;
wherein the first alignment mark is laterally offset from an edge of the second bonding structure;
Relater art, Wu teaches an embodiment where there are first alignment marks (106, Fig. 1B, para [0022]) in a first substrate of a first wafer (first wafer 102, Fig. 1B, para [0022]), wherein the first alignment mark (102) is laterally offset from an edge of the second bonding structure (second wafer 104, see Fig. 1B). Wu teaches that the alignment marks are used for patterning equipment accurately over the first wafer (para [0022]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Wu and implement the alignment marks into the first substrate of Huang, because the alignment marks will help in aligning the second wafer of Huang on to the first wafer and also help in patterning components accurately on the second wafer, for example patterning the capping layer 160 of the second wafer substrate 101a in Fig. 15A of Huang, to expose TSVs for connecting semiconductor chips that will be formed on top of the second substrate.
Additionally, Huang does not disclose performing a photolithography process on the second wafer using the first alignment mark. However, Huang modified by Wu discloses a patterning step on the second wafer using the alignment marks (patterning the capping layer 160 to form a gap in the layer 160, so that top surfaces of the vias within wafer substrate 101a are exposed, so that it can form electrical connections to the semiconductor chips that will be formed on top of the second substrate). Huang modified by Wu does not disclose how the patterning step was performed.
Related art, Wang discloses that photolithography can be performed to pattern the insulating layer (131a, Figs. 1a-1b, para [0023]) so that conductive elements could be formed (Figs. 1a-1b, para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to perform the patterning step of Huang modified by Wu, using the photolithography process, as taught by Wang. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 22, Huang modified by Wu and Wang teaches the method as claimed in claim 1, further comprising forming a passivation structure (capping layer 160, Fig. 15A, para [0043]) over the second substrate of the second wafer (101a, Fig. 15A) after the second wafer is thinned (see Figs. 12-13), wherein t3he passivation structure (160) is in contact with the first bonding structure (214, see Fig. 15A) and the second bonding structure (114, see Fig. 15A).
Allowable Subject Matter
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 23 is allowable for the following reasons. Most of the limitations of claim 23 are taught by Huang et al. (US 2021/0134663 A1, newly cited). Huang teaches, “forming a passivation structure (capping layer 160, Fig. 15A, para [0043]) after the second wafer is thinned (see Figs. 12-13), wherein the passivation structure (160, Fig. 15A) comprises a second portion lining a side wall of the second substrate (sidewall of 101a), and a third portion lining a top surface of the second substrate (top surface of 101a). Huang fails to teach a passivation structure comprising “a first portion lining a top surface of the first bonding structure” such that “the first portion of the passivation structure overlaps the first bonding structure and the first alignment mark vertically without overlapping the second bonding structure vertically”. In Examiner’s opinion, the prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the entire claim 23 and in view of the independent claim 1, as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1, 13 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argued that the process shown by Kim et al. (US 2015/0221517 A1, of record) cannot be modified such that the second wafer is trimmed before being bonded to the first wafer. Applicant asserts without evidence that the changing the sequence of trimming “would render Kim inoperable for its intended purpose”. Examiner respectfully disagrees with the applicant’s argument. Kim states that a void V1 is formed when two wafers of nearly equal lengths are bonded (Fig. 5, para [0094]), and it would be effective to trim the second wafer (Fig. 6) to remove the void (para [0094]). Kim does not state nor implies that trimming the second wafer before being bonded to the first wafer would make the device inoperable. Moreover, Chiang et al. (US 2019/0148130 A1, newly cited) shows a bonded device (bonded wafers 100 and 200, Fig. 1H, paras [0023]) which is similar to the bonded device of Fig. 7 of Kim, where the second wafer was trimmed before being bonded to the first wafer, as discussed in the first rejection of claim 1 above. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.D./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights