Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 12/24/2025 has been entered. Claims 1, 4, 5 21, 23 are amended. Claims 31 – 37 are newly added. Claims 6, 11 – 20, 24, 26 – 30 are canceled. Claims 1 – 5, 7 – 10, 21 – 23, 25, 31 – 37 remain pending in the application.
Election/Restrictions
Newly submitted claims 31 – 37 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
I. Claims 1 – 5, 7 – 10, 21 – 23, 25 drawn to a method for forming a semiconductor device structure, classified in H10D 64/021.
II. Claims 31 – 35, drawn to a method for forming a semiconductor device structure, classified in H10D 30/797.
Inventions I and II are directed to related method. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions have a materially different design. Inventions I requires partially removing the dielectric layer to form a first through hole and a second through hole in the dielectric layer; forming the first contact structure and the second contact structure in the first through hole and the second through hole, respectively; forming a spacer layer over the substrate, wherein the spacer layer has a first trench, a second trench, a third trench, and a fourth trench; the etch stop layer is formed over a sidewall of the spacer layer; while invention II requires a first pitch; a second pitch; wherein the second source/drain structure is wider than the first source/drain structure; wherein the etch stop layer over the second source/drain structure has a trapezoidal shape in a cross-sectional view; wherein the top of the first source/drain structure is vertically between a top of the first gate stack and a bottom of the first gate stack; wherein the first source/drain structure is laterally spaced apart from the first gate stack; wherein the first source/drain structure is partially embedded in the substrate.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 31 – 35 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 7 – 10, 21 – 23, 25, 36 – 37 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (Pub. No. 20170200800 A1), hereinafter Liu, in view of Houston (Pub. No. 20080247221 A1), hereinafter Houston.
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Regarding Independent Claim 1 (Currently Amended), Liu teaches a method for forming a semiconductor device structure, comprising:
forming a first source/drain structure ( Liu, FIG. 1N-1, 112 under 262; [0018], doped regions 112; [0069], conductive contact structures 262 ) and a second source/drain structure ( Liu, FIG. 1N-1, 112 under 266; [0018], doped regions 112; [0069], conductive contact structures … 266 ) over and in a substrate ( Liu, FIG. 1N-1, 110; [0011], semiconductor substrate 110 );
forming a first gate stack ( Liu, FIG. 1N-1, 192; [0031], gate electrodes 192 ), a second gate stack ( Liu, FIG. 1N-1, 194; [0031], gate electrodes 194 ), a third gate stack ( Liu, FIG. 1N-1, 196; [0031], gate electrodes 196 ), and a fourth gate stack ( Liu, FIG. 1N-1, 198; [0031], gate electrodes 198 ) over the substrate ( Liu, FIG. 1N-1, 110 ) , wherein the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) is between the first gate stack ( Liu, FIG. 1N-1, 192 ) and the second gate stack ( Liu, FIG. 1N-1, 194 ), the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) is between the third gate stack ( Liu, FIG. 1N-1, 196 ) and the fourth gate stack ( Liu, FIG. 1N-1, 198 ),
the first gate stack ( Liu, FIG. 1N-1, 192 ) has a first sidewall ( Liu, FIG. 1N-1, right sidewall of 192 ) facing away from the second gate stack ( Liu, FIG. 1N-1, 194 ), the second gate stack ( Liu, FIG. 1N-1, 194 ) has a second sidewall ( Liu, FIG. 1N-1, right sidewall of 194 ) facing the first gate stack ( Liu, FIG. 1N-1, 192 ), the third gate stack ( Liu, FIG. 1N-1, 196 ) has a third sidewall ( Liu, FIG. 1N-1, left sidewall of 196 ) facing the fourth gate stack( Liu, FIG. 1N-1, 198 ), the fourth gate stack ( Liu, FIG. 1N-1, 198 ) has a fourth sidewall ( Liu, FIG. 1N-1, left sidewall of 198 ) facing away from the third gate stack( Liu, FIG. 1N-1, 196 ), and a first distance between the first sidewall ( Liu, FIG. 1N-1, right sidewall of 192 ) and the second sidewall ( Liu, FIG. 1N-1, right sidewall of 194 ) is substantially equal to a second distance between the third sidewall ( Liu, FIG. 1N-1, left sidewall of 196 ) and the fourth sidewall ( Liu, FIG. 1N-1, left sidewall of 198 );
forming a dielectric layer ( Liu, FIG. 1A-1, 160; FIG. 1J-1, 162a; [0020], dielectric layer 160 ) over the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure (Liu, FIG. 1N-1, 112 under 266);
forming a first contact structure ( Liu, FIG. 1N-1, 262; [0069], conductive contact structures 262 ) and a second contact structure ( Liu, FIG. 1N-1, 266; [0069], conductive contact structures 266 ) over the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) respectively, wherein a first average width of the first contact structure ( Liu, FIG. 1N-1, 262 ) is substantially equal to a second average width of the second contact structure ( Liu, FIG. 1N-1, 266 ); and
forming an etch stop layer ( Liu, FIG. 1N-1, 150; [0019], As shown in FIGS. 1A and 1A-1, a contact etch stop layer 150 is formed over the semiconductor substrate 110 … The contact etch stop layer 150 includes a dielectric material, such as silicon nitride ) over the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) before forming the dielectric layer The contact etch stop layer 150 has upper portions 152U ) in a cross-sectional view of the etch stop layer ( Liu, FIG. 1G-1, 150 which is not covered by 220 ).
Liu fails to disclose:
each of the first gate stack and the second gate stack is wider than each of the third gate stack and the fourth gate stack,
However, Houston teaches:
each of the first gate stack and the second gate stack is wider than each of the third gate stack and the fourth gate stack ( Houston, FIG. 7; [0096], Alternately, the read transistor gate length may be made longer than some minimum to reduce leakage to the read bit line, and to have the read driver gate length minimized in order to maximize read current. In addition, it is advantageous to have the gate lengths in the core cell to be longer than a minimum length and to have the gate length of the read driver transistor at a minimum gate length. The longer gate length generally reduces variation and reduces leakage to the core cell while the shorter gate length increases read current; [0098], In addition, the gate length (Y-axis in the Figures) of the read transistor 207 (or read driver transistor 208) is drawn shorter than the gate length of the write transistor 118, providing a greater read current for the read transistor 207 than would be provided with the write transistor 118; [0102], In accordance with the layouts illustrated and the spirit of the present invention, the increased drive current Idrive, may be accomplished using any combination of a shorter gate length, and/or a greater gate width of the read buffer transistors 207 and 208 relative to the transistors of the 6T core cell 102; [0104], However, the circuit of SRAM cell 900 still has the advantage of having an isolated and increased read current Iread capability such as by wider width, shorter gate length, or lower Vt transistors in the read circuit compared to the transistors in the core 6T cell 101, with the potentially faster read access time previously described ),
Liu and Houston are both considered to be analogous to the claimed invention because they are forming source/drain structure and gate structure in semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liu ( first and second source/drain structures; first, second, third, and fourth gate stacks ), to incorporate the teachings of Houston ( using any combination of a shorter gate length, and/or a greater gate width ), to implement that each of the first gate stack and the second gate stack is wider than each of the third gate stack and the fourth gate stack. Doing so would provide specific layouts for source/drain structure and gate structure, and therefore the better performance ( e.g. reduces variation and reduces leakage, increases read current, faster read access time ) can be implemented.
Regarding Claim 2 (Original), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 1, on which this claim is dependent, Liu and Houston further teach:
wherein the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) is narrower ( As shown above in the 103 rejection of claim 1, Liu’s uniform spacing between adjacent gates ( 192, 194, 196, 198 ) in FIG. 1N-1 are modified in view of Houston ( using any combination of a shorter gate length, and/or a greater gate width ) to make the first/second gates wider than the third/fourth gates, therefore, “ the resulting first source/drain is narrower than the second source/drain ” is an inherent consequence ) than the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ).
Regarding Claim 3 (Original), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 1, on which this claim is dependent, Liu and Houston further teach:
wherein a third distance between the first gate stack ( Liu, FIG. 1N-1, 192 ) and the second gate stack ( Liu, FIG. 1N-1, 194 ) is less ( Houston, [0102], In accordance with the layouts illustrated and the spirit of the present invention, the increased drive current Idrive, may be accomplished using any combination of a shorter gate length, and/or a greater gate width of the read buffer transistors 207 and 208 relative to the transistors of the 6T core cell 102 ) than a fourth distance between the third gate stack ( Liu, FIG. 1N-1, 196 ) and the fourth gate stack ( Liu, FIG. 1N-1, 198 ).
Regarding Claim 4 (Currently Amended), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 1, on which this claim is dependent, Liu further teaches:
wherein the forming of the first contact structure ( Liu, FIG. 1N-1, 262; [0069], conductive contact structures 262 ) and the second contact structure ( Liu, FIG. 1N-1, 262; [0069], conductive contact structures 266 ) comprises:
partially removing the dielectric layer ( Liu, FIG. 1N-1, 160; [0040], As shown in FIGS. 1F, 1F-1, 1G, and 1G-1, portions of … the dielectric layer 160 are removed ) to form a first through hole ( Liu, FIG. 1N-1, 162T; [0063] The through holes 162T … expose the doped regions 112 … The through holes 162T … are also referred to as contact holes ) and a second through hole ( Liu, FIG. 1N-1, 166T; [0063] The through holes … 166T expose the doped regions 112 … The through holes … 166T are also referred to as contact holes ) in the dielectric layer, wherein the first through hole and the second through hole expose the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) respectively; and
forming the first contact structure ( Liu, FIG. 1N-1, 262; [0069], conductive contact structures 262 ) and the second contact structure ( Liu, FIG. 1N-1, 266; [0069], conductive contact structures … 266 ) in the first through hole ( Liu, FIG. 1N-1, 162T; [0063] ) and the second through hole ( Liu, FIG. 1N-1, 166T; [0063] ) respectively.
Regarding Claim 5 (Currently Amended), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 4, on which this claim is dependent, Liu further teaches:
wherein the dielectric layer ( Liu, FIG. 1N-1, 160; [0040] ) is formed over the etch stop layer ( Liu, [0020], As shown in FIGS. 1A and 1A-1, a dielectric layer 160 is deposited over the contact etch stop layer 150 ), the partially removing of the dielectric layer ( Liu, FIG. 1N-1, 160; [0040] ) further partially removes the etch stop layer ( Liu, [0040], The opening 222 exposes portions … the contact etch stop layer 150 ), and the first through hole ( Liu, FIG. 1N-1, 162T; [0063] ) and the first contact structure ( Liu, FIG. 1N-1, 262; [0069] ) further pass through the etch stop layer ( Liu, FIG. 1N-1, 150; [0019] ).
Regarding Claim 7 (Original), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 5, on which this claim is dependent, Liu further teaches:
wherein the etch stop layer ( Liu, FIG. 1N-1, 150; [0019] ) is further formed over the second source/drain structure (Liu, FIG. 1N-1, 112 under 266), the partially removing of the dielectric layer ( Liu, FIG. 1N-1, 160; [0040] ) further partially removes the etch stop layer ( Liu, FIG. 1N-1, 150; [0019] ) over the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ), and the second through hole ( Liu, FIG. 1N-1, 166T; [0063] ) and the second contact structure ( Liu, FIG. 1N-1, 266; [0069] ) further pass through the etch stop layer ( Liu, FIG. 1N-1, 150; [0019] ).
Regarding Claim 8 (Original), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 7, on which this claim is dependent, Liu further teaches:
wherein the etch stop layer ( Liu, FIG. 1N-1, 150; [0019] ) over the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) has a trapezoidal shape ( Liu, FIG. 1J-1, trapezoidal shape of 156U and 156L; [0059], The contact etch stop layer 150 has upper portions … 156U, … The contact etch stop layer 150 has lower portions … 156L ) in a cross-sectional view of the etch stop layer ( Liu, FIG. 1N-1, 150; [0019] ).
Regarding Claim 9 (Original), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 5, on which this claim is dependent, Liu further teaches: further comprising:
before forming the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) over and in the substrate ( Liu, FIG. 1N-1, 110; [0011] ), forming a spacer layer ( Liu, FIG. 1N-1, 142, 144, 146, 148; [0016], As shown in FIGS. 1A and 1A-1, spacer layers 142, 144, 146, and 148 are formed over sidewalls of the gate stacks 130 ) over the substrate, wherein the spacer layer has a first trench, a second trench, a third trench, and a fourth trench ( Liu, [0022], openings 142a, 144a, 146a, and 148a are formed in the spacer layers 142, 144, 146, and 148 ), the first gate stack ( Liu, [0034], a gate stack G1 is formed in the opening 142a ), the second gate stack ( Liu, [0035], a gate stack G2 is formed in the opening 144a ), the third gate stack ( Liu, [0036], a gate stack G3 is formed in the opening 146a ), and the fourth gate stack ( Liu, [0037], a gate stack G4 is formed in the opening 148a ) are formed in the first trench, the second trench, the third trench, and the fourth trench ( Liu, [0022], openings 142a, 144a, 146a, and 148a ) respectively, and the etch stop layer (Liu, FIG. 1N-1, 150; [0019]) is formed over a sidewall of the spacer layer ( Liu, FIG. 1N-1, 142, 144, 146, 148 ).
Regarding Claim 10 (Original), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 9, on which this claim is dependent, Liu further teaches:
wherein the first contact structure ( Liu, FIG. 1N-1, 262, 112; [0069]; [0070], The conductive contact structures 262, 264, and 266 are electrically connected to the doped regions 112 ) is in direct contact with the spacer layer ( Liu, FIG. 1N-1, 142, 144, … ) over the second sidewall of the second gate stack ( Liu, FIG. 1N-1, 194; [0031], gate electrodes 194 ) (Liu, FIG. 1N-1, 142, 144, 146, 148; [0016], As shown in FIGS. 1A and 1A-1, spacer layers 142, 144, … are formed over sidewalls of the gate stacks 130).
Regarding Independent Claim 21 (Currently Amended), Liu teaches a method for forming a semiconductor device structure, comprising:
forming a first source/drain structure ( Liu, FIG. 1N-1, 112 under 262; [0018], doped regions 112; [0069], conductive contact structures 262 ) and a second source/drain structure ( Liu, FIG. 1N-1, 112 under 266; [0018], doped regions 112; [0069], conductive contact structures … 266 ) over and in a substrate ( Liu, FIG. 1N-1, 110; [0011], semiconductor substrate 110 );
forming a first gate stack ( Liu, FIG. 1N-1, 192; [0031], gate electrodes 192 ), a second gate stack ( Liu, FIG. 1N-1, 194; [0031], gate electrodes 194 ), a third gate stack ( Liu, FIG. 1N-1, 196; [0031], gate electrodes 196 ), and a fourth gate stack ( Liu, FIG. 1N-1, 198; [0031], gate electrodes 198 ) over the substrate ( Liu, FIG. 1N-1, 110 ), wherein the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) is between the first gate stack ( Liu, FIG. 1N-1, 192 ) and the second gate stack ( Liu, FIG. 1N-1, 194 ), the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) is between the third gate stack ( Liu, FIG. 1N-1, 196 ) and the fourth gate stack ( Liu, FIG. 1N-1, 198 ), the first gate stack ( Liu, FIG. 1N-1, 192 ) has a first sidewall ( Liu, FIG. 1N-1, right sidewall of 192 ) facing away from the second gate stack ( Liu, FIG. 1N-1, 194 ), the second gate stack ( Liu, FIG. 1N-1, 194 ) has a second sidewall ( Liu, FIG. 1N-1, right sidewall of 194 ) facing the first gate stack ( Liu, FIG. 1N-1, 192 ), the third gate stack ( Liu, FIG. 1N-1, 196 ) has a third sidewall ( Liu, FIG. 1N-1, left sidewall of 196 ) facing the fourth gate stack, the fourth gate stack ( Liu, FIG. 1N-1, 198 ) has a fourth sidewall ( Liu, FIG. 1N-1, left sidewall of 198 ) facing away from the third gate stack, and a first distance between the first sidewall ( Liu, FIG. 1N-1, right sidewall of 192 ) and the second sidewall ( Liu, FIG. 1N-1, right sidewall of 194 ) is substantially equal to a second distance between the third sidewall ( Liu, FIG. 1N-1, left sidewall of 196 ) and the fourth sidewall ( Liu, FIG. 1N-1, left sidewall of 198 );
forming a dielectric layer ( Liu, FIG. 1A-1, 160; FIG. 1J-1, 162a; [0020], dielectric layer 160 ) over the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure (Liu, FIG. 1N-1, 112 under 266);
forming an etch stop layer ( Liu, FIG. 1N-1, 150; [0019], As shown in FIGS. 1A and 1A-1, a contact etch stop layer 150 is formed over the semiconductor substrate 110 … The contact etch stop layer 150 includes a dielectric material, such as silicon nitride ) over the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) before forming the dielectric layer (Liu, [0020], As shown in FIGS. 1A and 1A-1, a dielectric layer 160 is deposited over the contact etch stop layer 150), wherein the etch stop layer has a portion ( Liu, FIG. 1G-1, 150 which is not covered by 220 ) extending upward from a top of the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ), and across-sectional view the portion of the etch stop layer is triangular ( Liu, FIG. 1G-1, when the ratio T1 / T2 is very small, for instance, 0.01, then the shape of 150 which is not covered by 220 is triangle; FIG. 1J-1, triangular shape above 152U; [0059], The contact etch stop layer 150 has upper portions 152U ); and
forming a first contact structure ( Liu, FIG. 1N-1, 262; [0069], conductive contact structures 262 ) and a second contact structure ( Liu, FIG. 1N-1, 266; [0069], conductive contact structures 266 ) over the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure ( Liu, FIG. 1N-1, 112 under 266 ) respectively, wherein a first average width of the first contact structure ( Liu, FIG. 1N-1, 262 ) is substantially equal to a second average width of the second contact structure ( Liu, FIG. 1N-1, 266 ).
Liu fails to disclose:
each of the first gate stack and the second gate stack has a different width from each of the third gate stack and the fourth gate stack,
However, Houston teaches:
each of the first gate stack and the second gate stack has a different width from each of the third gate stack and the fourth gate stack ( Houston, FIG. 7; [0096], Alternately, the read transistor gate length may be made longer than some minimum to reduce leakage to the read bit line, and to have the read driver gate length minimized in order to maximize read current. In addition, it is advantageous to have the gate lengths in the core cell to be longer than a minimum length and to have the gate length of the read driver transistor at a minimum gate length. The longer gate length generally reduces variation and reduces leakage to the core cell while the shorter gate length increases read current; [0098], In addition, the gate length (Y-axis in the Figures) of the read transistor 207 (or read driver transistor 208) is drawn shorter than the gate length of the write transistor 118, providing a greater read current for the read transistor 207 than would be provided with the write transistor 118; [0102], In accordance with the layouts illustrated and the spirit of the present invention, the increased drive current Idrive, may be accomplished using any combination of a shorter gate length, and/or a greater gate width of the read buffer transistors 207 and 208 relative to the transistors of the 6T core cell 102; [0104], However, the circuit of SRAM cell 900 still has the advantage of having an isolated and increased read current Iread capability such as by wider width, shorter gate length, or lower Vt transistors in the read circuit compared to the transistors in the core 6T cell 101, with the potentially faster read access time previously described ),
Liu and Houston are both considered to be analogous to the claimed invention because they are forming source/drain structure and gate structure in semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liu ( first and second source/drain structures; first, second, third, and fourth gate stacks ), to incorporate the teachings of Houston ( using any combination of a shorter gate length, and/or a greater gate width ), to implement that each of the first gate stack and the second gate stack has a different width from each of the third gate stack and the fourth gate stack. Doing so would provide specific layouts for source/drain structure and gate structure, and therefore the better performance ( e.g. reduces variation and reduces leakage, increases read current, faster read access time ) can be implemented.
Regarding Claim 22 ( Previously Presented ), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 21, on which this claim is dependent, Liu and Houston further teach:
wherein the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) and the second source/drain structure have different widths ( As shown above in the 103 rejection of claim 21, Liu’s uniform spacing between adjacent gates ( 192, 194, 196, 198 ) in FIG. 1N-1 are modified in view of Houston (using any combination of a shorter gate length, and/or a greater gate width ) to make the first/second gates wider than the third/fourth gates, therefore, “ the resulting first source/drain have different width from the second source/drain ” is an inherent consequence).
Regarding Claim 23 (Currently Amended), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 21, on which this claim is dependent, Liu further teaches:
wherein
the forming of the first contact structure ( Liu, FIG. 1N-1, 262; [0069], conductive contact structures 262 ) and the second contact structure ( Liu, FIG. 1N-1, 262; [0069], conductive contact structures 266 ) comprises:
partially removing the dielectric layer ( Liu, FIG. 1N-1, 160; [0040], As shown in FIGS. 1F, 1F-1, 1G, and 1G-1, portions of … the dielectric layer 160 are removed ) to form a first through hole and a second through hole in the dielectric layer, wherein the first through hole and the second through hole expose the first source/drain structure and the second source/drain structure, respectively; and
forming the first contact structure and the second contact structure in the first through hole and the second through hole, respectively.
Regarding Claim 25 (Currently Amended), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 21, on which this claim is dependent, Liu further teaches:
wherein the etch stop layer ( Liu, FIG. 1N-1, 150; [0019] ) over the second source/drain ( Liu, FIG. 1N-1, 112 under 266 ) structure has a trapezoidal shape ( Liu, FIG. 1J-1, trapezoidal shape of 156U and 156L; [0059], The contact etch stop layer 150 has upper portions … 156U, … The contact etch stop layer 150 has lower portions … 156L ) in a cross-sectional view.
Regarding Claim 36 (New), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 1, on which this claim is dependent, Liu further teaches:
wherein the top of the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) is vertically between a top of the first gate stack (Liu, FIG. 1N-1, 192) and a bottom of the first gate stack (Liu, FIG. 1N-1, 192), and the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) is laterally spaced apart from the first gate stack (Liu, FIG. 1N-1, 192).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create “ the top of the first source/drain structure is vertically between a top of the first gate stack and a bottom of the first gate stack ”, for instance, Gate-All-Around, in which the top of source/drain is vertically higher than the bottom of gate, since this is within the skill level of one in the art.
Regarding Claim 37 (New), Liu and Houston teach the method for forming the semiconductor device structure as claimed in claim 21, on which this claim is dependent, Liu further teaches:
wherein the top of the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) is vertically between a top of the first gate stack (Liu, FIG. 1N-1, 192) and a bottom of the first gate stack (Liu, FIG. 1N-1, 192), and the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) is partially embedded in the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create “ the top of the first source/drain structure is vertically between a top of the first gate stack and a bottom of the first gate stack ”, for instance, Gate-All-Around, in which the top of source/drain is vertically higher than the bottom of gate, since this is within the skill level of one in the art.
Response to Arguments
Applicant's remarks filed 12/24/2025 have been fully considered but they are not persuasive.
Applicant’s remarks regarding ( Currently Amended ) Claims 1: on page 11, line 7, cited “ However, the Examiner has not provided any evidence showing that Liu discloses the alleged etch stop layer 150 having a portion that extends from the top of the alleged first source/drain structure 112 toward the top of the alleged etch stop layer 150, nor that the cross- sectional shape of that portion of the alleged etch stop layer 150 is triangular. Therefore, the Examiner has not provided any evidence showing that Liu discloses "the etch stop layer has a portion extending from a top of the first source/drain structure toward a top of the etch stop layer, and a cross-sectional view the portion of the etch stop layer is triangular" as recited in amended claim 1. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ wherein the etch stop layer has a portion ( Liu, FIG. 1G-1, 150 which is not covered by 220 ) extending from a top of the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ) toward a top of the etch stop layer ( Liu, FIG. 1G-1, 150 ), and across-sectional view the portion of the etch stop layer ( Liu, FIG. 1G-1, 150 which are not covered by 220 ) is triangular ( Liu, FIG. 1G-1, when the ratio T1 / T2 is very small, for instance, 0.01, then the shape of 150 which is not covered by 220 is triangle; FIG. 1J-1, triangular shape above 152U; [0059], The contact etch stop layer 150 has upper portions 152U ) in a cross-sectional view of the etch stop layer ( Liu, FIG. 1G-1, 150 which is not covered by 220 ). ”.
Applicant’s remarks regarding ( Currently Amended ) Claims 21: on page 12, line 13, cited “ However, the Examiner has not provided any evidence showing that Liu discloses the alleged etch stop layer 150 having a portion that extends upward from the top of the alleged first source/drain structure 112, nor that the cross-sectional shape of that portion of the alleged etch stop layer 150 is triangular. Therefore, the Examiner has not provided any evidence showing that Liu discloses "the etch stop layer has a portion extending upward from a top of the first source/drain structure, and a cross-sectional view the portion of the etch stop layer is triangular" as recited in amended claim 21. ”.
Examiner’s response: please refer to claim 21 in Claim Rejections - 35 USC § 103 of this office action, cited “ wherein the etch stop layer has a portion ( Liu, FIG. 1G-1, 150 which is not covered by 220 ) extending upward from a top of the first source/drain structure ( Liu, FIG. 1N-1, 112 under 262 ), and across-sectional view the portion of the etch stop layer is triangular ( Liu, FIG. 1G-1, when the ratio T1 / T2 is very small, for instance, 0.01, then the shape of 150 which is not covered by 220 is triangle; FIG. 1J-1, triangular shape above 152U; [0059], The contact etch stop layer 150 has upper portions 152U ) ”.
Applicant’s remarks regarding ( New ) Claims 31 – 37: on page 13, line 6, cited “ Claims 31-37 have been added for the Examiner's consideration. Support for new claims 31-37 can be found in FIGs.lA-1K and the corresponding disclosure of the specification as originally filed. Similar to the reasoning provided for independent claims 1 and 21, it is believed that independent claim 31 and dependent claims 32-35 are also allowable. ”.
Examiner’s response: please refer to Election/Restrictions of this office action, to see the reasons for claims 31 – 35 withdrawn from consideration as being directed to a non-elected invention. Please refer to claims 36 – 37 in Claim Rejections - 35 USC § 103 of this office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached Monday thru Friday E.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817