`DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 12/11/2025 is acknowledged. Claims 1, 3-5, 10-12, 21 have been amended.
Response to Arguments
Applicant’s arguments with respect to claims 1-15, 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seliskar (US 7211864 B2).
Regarding claim 11, Seliskar teaches a method for forming a semiconductor device structure (method for forming the device in Fig. 29, which is a modification of the method in Figs. 3-28A. The two embodiments differ in the material of the etch stop 23/75 and in how the isolation structures 54-56 come in contact with buried oxide 75), comprising:
providing a substrate (21) having a base (portion of substrate bellow the fins 22), a first fin (leftmost fin of the group of fins to the right), and a second fin (a fin in the left group of fins) over the base, wherein the base has a bottom portion (carrier substrate below the buried oxide 75 in Fig. 29), an insulating layer (buried oxide 75), and an upper layer (portion of substrate connecting the fins together), and the insulating layer is between the bottom portion and the upper layer (as shown in Fig. 29);
forming a trench (trench of isolation structure 54/56 in Fig. 29) in the upper layer and between the first fin and the second fin, wherein: the trench exposes a portion of the insulating layer (as implied by the description in column 15 lines 32-35 of Seliskar), and a bottom of the trench is defined by a top surface of the insulating layer (as shown in Fig. 29 of Seliskar);
forming an isolation layer (54 and 116 in Fig. 29) over the base and in the trench, wherein the first fin and the second fin are partially in the isolation layer;
forming a first gate stack (32 of the group of fins to the right) over the first fin and the isolation layer; and
forming a second gate (32 of the group of fins to the left) stack over the second fin and the isolation layer.
Regarding claim 12, Seliskar teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, and also teaches wherein the isolation layer is in direct contact with the top surface of the insulating layer (as shown in Fig. 29 of Seliskar).
Regarding claim 13, Seliskar teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, and also teaches wherein a first bottom surface of the isolation layer is substantially level with a second bottom surface of the upper layer (as shown in Fig. 29 of Seliskar).
Regarding claim 14, Seliskar teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, and also teaches wherein the first fin is electrically insulated from the second fin after the trench is formed in the upper layer and between the first fin and the second fin (as shown in Fig. 29 of Seliskar).
Regarding claim 15, Seliskar teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 11, and also teaches wherein the isolation layer passes through the upper layer of the base of the substrate (as shown in Fig. 29 of Seliskar).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 21-22, 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Seliskar (US 7211864 B2) in view of Frank et al. (US 7666723 B2).
Regarding claim 1, Seliskar teaches a method for forming a semiconductor device structure (method for forming the device in Fig. 29, which is a modification of the method in Figs. 3-28A. The two embodiments differ in the material of the etch stop 23/75 and in how the isolation structures 54-56 come in contact with buried oxide 75), comprising:
providing a substrate (21) having a base (portion of substrate bellow the fins 22), a first fin (leftmost fin of the group of fins to the right), and a second fin (a fin in the left group of fins), and a third fin (rightmost fin the group of fins to the right) over the base;
forming a first trench (trench of the STI 54 between the right group of fins and the left group of fins in Fig. 29) in the base and between the first fin and the second fin;
forming an isolation layer (54 and 116 in Fig. 29) over the base and in the first trench, wherein the first fin, and the second fin, and the third fin are partially in the isolation layer (as shown in Fig. 29);
forming a first gate stack (32 of the group of fins to the right) over the first fin, the third fin, and the isolation layer;
forming a second gate stack (32 of the group of fins to the left) over the second fin and the isolation layer.
But Seliskar does not teach that the method comprising: removing a bottom portion of the base while maintaining a first top portion of the base coupled to the first fin and the third fin and a second top portion of the base coupled to the second fin, wherein the isolation layer passes between the first top portion and the second top portion through the base after the bottom portion of the base is removed.
Frank teaches a method of forming a transistor (method in Figs. 1A-1B, 2-3 and 7 of Frank). The method comprises: forming a plurality of transistors (100A-100C in Fig. 1A) on a SOI substrate (102); removing a bottom portion of the substrate while maintaining a top portion of the substrate coupled to the channel regions of the transistors (as shown in Figs. 2-3, the carrier substrate of the SOI substrate 102 is removed) exposing the buried oxide layer (112 in Fig. 3); and forming frontside and backside electrical contacts to the transistors (see Fig. 7 of Frank).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have removed the bottom portion of the base and to have formed the front and back-side electrical contracts to the transistors of Seliskar in order to have reduced the interconnection density (therefore reduced the interference of interconnections).
As incorporated, the first and second top portion are defined as portion of the base connecting the fins 22 in the same group of fins together, as shown in Fig. 29 of Seliskar. As such the isolation layer (54) of Seliskar passes between the first top portion and the second top portion.
Regarding claim 2, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein removing the bottom portion of the base comprises: thinning the base from a bottom surface of the base (as shown in Figs. 2-3 of Frank).
Regarding claim 3, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein the first top portion and the second top portion are separated from each other by the isolation layer after the bottom portion of the base is removed (as shown in Fig. 29 of Seliskar).
Regarding claim 4, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein a first bottom surface of the first top portion of the base is substantially level with a second bottom surface of the isolation layer (as shown in Fig. 29 of Seliskar) after the bottom portion of the base is removed.
Regarding claim 5, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein the base is divided into the first top portion and the second top portion by the first trench (see Fig. 29 of Seliskar), and the first top portion and the second top portion are electrically insulated from each other by the isolation layer after the bottom portion of the base is removed (see Fig. 29 of Seliskar).
Regarding claim 6, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein the substrate has a first well region (portion of substrate below the fins 22 in the right group) and a second well region (portion of substrate below the fins 22 in the left group), the first fin and a first portion (portion of substrate directly underneath the first fin) of the base is in the first well region (as defined above), the second fin and a second portion (portion of substrate directly underneath the first fin) of the base is in the second well region, and forming the first trench comprises: partially removing the first portion and the second portion of the base to form the first trench between the first well region and the second well region (as combined in claim 1 above), wherein the first trench separates the first well region from the second well region (as shown in Fig. 29).
Regarding claim 7, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 6, and also teaches wherein the first well region has a first type conductivity, the second well region has a second type conductivity, and the first type conductivity is different from the second type conductivity (as described in column 12 lines 51-63 of Seliskar, the device is a CMOS, so the first group can be a p-type, the second group can be n-type, or vice versa).
Regarding claim 8, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 6, and also teaches wherein the bottom portion of the base of the substrate is under the first well region and the second well region (as taught in claims 1 and 6).
Regarding claim 9, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and also teaches wherein a width of the first trench of the base is less than a distance between the first fin and the second fin (as shown in Fig. 29 of Seliskar).
Regarding claim 10, Seliskar in view of Frank teaches all limitations of the method for forming the semiconductor device structure as claimed in claim 1, and further comprising:
before forming the first gate stack over the first fin, the third fin, and the isolation layer, forming a dielectric layer (ILD described in column 6 lines 40-52 of Seliskar) over the first fin, the second fin, the third fin, and the isolation layer, wherein the dielectric layer has a second trench (the gate trench over the first fin when the dummy gate over the first fin is removed, as described in column 6 lines 40-52 of Seliskar) and a third trench (the gate trench over the first fin when the dummy gate over the second fin is removed, as described in column 6 lines 40-52 of Seliskar), the second trench partially exposes the first fin and the isolation layer (as defined), the third trench partially exposes the second fin and the isolation layer (as defined), and the first gate stack and the second gate stack are formed in the second trench and the third trench respectively (as described in column 6 lines 40-52 of Seliskar).
Regarding claim 21, Seliskar teaches a method for forming a semiconductor device structure (method for forming the device in Fig. 29, which is a modification of the method in Figs. 3-28A. The two embodiments differ in the material of the etch stop 23/75 and in how the isolation structures 54-56 come in contact with buried oxide 75), comprising:
forming an isolation layer (54, 116, and buried oxide layer 75 in Fig. 29) between a first fin (leftmost fin of the group of fins to the right) and a second fin (a fin in the left group of fins);
forming a dielectric layer (ILD described in column 6 lines 40-52 of Seliskar) between the first fin and the second fin and overlying the isolation layer;
forming a first gate stack (32 of the group of fins to the right) over first fin;
forming a second gate stack (32 of the group of fins to the left) over the second fin and spaced apart from the first gate stack by the dielectric layer (as shown in Fig. 29 of Seliskar).
But Seliskar does not teach the method comprising: removing at least a portion of a base underlying the first fin and the second fin after forming the second gate stack to expose a surface of the isolation layer facing away from the dielectric layer, wherein the first fin and the second fin remain concealed by a remaining portion of the base after removing the portion of the base.
Frank teaches a method of forming a transistor (method in Figs. 1A-1B, 2-3 and 7 of Frank). The method comprises: forming a plurality of transistors (100A-100C in Fig. 1A) on a SOI substrate (102); removing a bottom portion of the substrate while maintaining a top portion of the substrate coupled to the channel regions of the transistors (as shown in Figs. 2-3, the carrier substrate of the SOI substrate 102 is removed) exposing the buried oxide layer (112 in Fig. 3); and forming frontside and backside electrical contacts to the transistors (see Fig. 7 of Frank).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have removed the bottom portion of the base and to have formed the front and back-side electrical contracts to the transistors of Seliskar in order to have reduced the interconnection density (therefore reduced the interference of interconnections).
As incorporated, the base structure of the substrate is defined as the portion of the SOI substrate below the fins 22 of Seliskar. The first and second top portion are defined as portion of the base connecting the fins 22 in the same group of fins together, as shown in Fig. 29 of Seliskar. As such the isolation layer (54) of Seliskar passes between the first top portion and the second top portion. As a result, the first fin and the second fin remain concealed by a remaining portion of the base after removing the portion of the base.
Regarding claim 22, Seliskar in view of Frank teaches all limitations of the method of claim 21, and also teaches wherein the base comprises a substrate (21 in Fig. 29 of Seliskar), and removing at least the portion of the base comprises removing at least a portion of the substrate (as shown in Figs. 2-3 of Seliskar).
Regarding claim 24, Seliskar in view of Frank teaches all limitations of the method of claim 21, and also teaches wherein forming the isolation layer comprises forming the isolation layer between the first fin and a third fin (rightmost fin the group of fins to the right), wherein a thickness (thickness of isolation layer 54/56 in Fig. 29 of Seliskar) of the isolation layer between the first fin and the second fin is different than a thickness (thickness of isolation layer 116 in Fig. 29 of Seliskar) of the isolation layer between the first fin and the third fin (as shown in Fig. 29 of Seliskar).
Regarding claim 25, Seliskar in view of Frank teaches all limitations of the method of claim 24, and also teaches wherein forming the isolation layer comprises forming the isolation layer such that the thickness of the isolation layer between the first fin and the second fin is greater than the thickness of the isolation layer between the first fin and the third fin (as shown in Fig. 29 of Seliskar).
Allowable Subject Matter
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 23, the prior art of record does not disclose or fairly suggest a method satisfying “wherein the base comprises a bottom portion, an insulating layer, and an upper layer separated from the bottom portion by the insulating layer, and removing at least the portion of the base comprises removing the bottom portion and the insulating layer” along with other limitations of claim 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898