Prosecution Insights
Last updated: October 04, 2026
Application No. 18/167,093

PHOTOMASK STRUCTURE, SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Final Rejection §102§103
Filed
Feb 10, 2023
Priority
Nov 14, 2022 — CN 202211419165.3
Examiner
ANGEBRANNDT, MARTIN J
Art Unit
1737
Tech Center
1700 — Chemical & Materials Engineering
Assignee
United Microelectronics Corp.
OA Round
4 (Final)
56%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 56% of resolved cases
56%
Career Allowance Rate
767 granted / 1381 resolved
-9.5% vs TC avg
Strong +34% interview lift
Without
With
+34.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
68 currently pending
Career history
1448
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
44.7%
+4.7% vs TC avg
§102
20.9%
-19.1% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1381 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The response of the applicant has been read and given careful consideration. Rejection(s) of the previous action not repeated below are withdrawn based upon the amendment and arguments of the applicant. Responses to the arguments of the applicant are presented after the first rejection they are directed to. In the response of 7/13/2026, the applicant argues that the recitation of “preventing deformation of a patterned resist layer” is sufficient to establish a functional relationship between the layout patterns on the mask substrate. The examiner agrees with this position, noting that the deformations disclosed include e.g., necking, line end shortening, or line end shrinkage (prepub at [0046,0065-0066]) which are known problems in the lithography art solved by optical proximity and/or dummy patterns In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Oh KR 20080001439. Oh KR 20080001439 (machine translation attached) exemplifies the prior mask of figure 1 and the improved mask of figure 4. PNG media_image1.png 321 451 media_image1.png Greyscale PNG media_image2.png 500 601 media_image2.png Greyscale The improved mask has added “dummy” areas which even out the density of the features (see the few black areas in the mask of figure 4). PNG media_image3.png 648 779 media_image3.png Greyscale A detail of the left portion of the photomask of figure 4 is below. PNG media_image4.png 465 526 media_image4.png Greyscale The present invention relates to a method of manufacturing a photomask used in a photolithography manufacturing process, and more particularly, to a method of manufacturing a photomask that can prevent a defect of a photomask pattern by modifying a pattern layout design<10>. In order to achieve the above object, the present invention provides a method of manufacturing a photomask, comprising the steps of comparing the pattern density in the layout pattern data of the photomask, determining whether there is a low density pattern space in the layout pattern data, and determining As a result, when the low density pattern space exists, modifying the layout pattern data by adding dummy pattern data to the low density pattern space region, and manufacturing a photomask on the substrate using the modified layout pattern data <20>. As a result of the determination in S30, when the preset low density space region exists in the layout pattern data, the dummy pattern (10e of FIG. 4) is added to the low density pattern space region in the layout pattern data to correct the layout pattern data of the photomask. To modify layout pattern data using a dummy pattern, add a dummy pattern to the layout pattern data using a general rule file (Hercules, Caliber) or a manual. For example, the low density pattern space region may be formed in the core region or the peripheral circuit region. The dummy pattern may be added between the word line, the bit line, the isolation region, and the metal wiring<27>. The patterns taught are light shielding and the protrusions are not aligned. Claims 1-2 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Setsuda JP 2007065246. Setsuda JP 2007065246 teaches with respect to figure 23, a photomask layout pattern which includes logic patterns and auxiliary features. In this case, as an auxiliary pattern for the memory pattern, a rectangular pattern whose length opposite to the side of each memory pattern is equal to or shorter than the length of the side of the memory pattern is a high-density pattern layout. It is suitable for widening the depth of focus. On the other hand, as an auxiliary pattern for patterns other than the memory pattern, a fine linear pattern having a ratio of the long side to the short side of 5 or more is suitable for increasing the depth of focus of the low-density pattern layout [0053-0054]. PNG media_image5.png 436 737 media_image5.png Greyscale Then, in the exposure pattern forming process of step 5, using the design data D .sub.3 which was corrected by operating an electron beam drawing apparatus, as shown in FIG. 3, Cr or on the quartz glass substrate 11 A resist pattern 15 is formed by drawing and developing a pattern with an electron beam 14 on an electron beam resist film 13 provided via a metal thin film 12 such as MoSi .sub.2 [0067]. Each of the above embodiments is based on the premise that a binary mask is used in a KrF light source exposure apparatus that has been frequently used in recent years. However, in the ArF light source exposure apparatus that will start to be frequently used in the future, and further in the immersion type ArF exposure apparatus, the phase shift is performed. Even when a mold mask, for example, a halftone mask is used, the effect is sufficiently exhibited, which is more preferable [0097]. The patterns taught are light shielding (Cr) or phase shifting (MoSi) and the protrusions are not aligned. Claims 1-2 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Toyama JP 2001077114 Toyama JP 2001077114 (machine translation attached) teaches with respect to figure 7, a photomask showing the light transmitting and light shielding portions corresponding the components 13,15,17 and the intervening dummy pattern 21 [0023] PNG media_image6.png 527 537 media_image6.png Greyscale The patterns taught are light shielding on a light transmitting field and the protrusions are not aligned. Claims 1-2 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Setsuda JP 2007065246, in view of Kleitman et al. 3669666 Kleitman et al. 3669666 describes the use of tape on a transparent substrate to form integrated circuit patterns. Among the mask patterns illustrated the patterns of figures 41,43,44 and 45 (reproduced below), where the white portions are transparent and the dark portions are opaque. PNG media_image7.png 95 197 media_image7.png Greyscale PNG media_image8.png 199 407 media_image8.png Greyscale It would have been obvious to modify the photomasks taught by Setsuda JP 2007065246 by forming masks where the patterns are openings as in figure 45 of Kleitman et al. 3669666 based upon masks of both polarities (light blocking patterns on transparent field and patterned light transmitting openings in light shielding layer) being old and well known in the art as evidenced in Kleitman et al. 3669666 in figures 41, and 43-45 with a reasonable expectation of forming a useful photomask. Claims 1-2 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Oh KR 20080001439, in view of Setsuda JP 2007065246 and Kleitman et al. 3669666 It would have been obvious to modify the photomasks taught by Oh KR 20080001439 by forming masks where the patterns are openings as in figure 45 of Kleitman et al. 3669666 based upon masks of both polarities (light blocking patterns on transparent field and patterned light transmitting openings in light shielding layer) being old and well known in the art as evidenced in Kleitman et al. 3669666 in figures 41, and 43-45 using Cr as the light shielding materials based upon the teachings of Setsuda JP 2007065246 or to replace the light shielding patterns with phase shifting patterns of MoSi as taught in Setsuda JP 2007065246 with a reasonable expectation of forming a useful photomask. Claims 1,2 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kleitman et al. 3669666, in view of Mizumura 20120218537, Ohmi et al. 20060104413 and Oh KR 20080001439 Mizumura 20120218537 in figure 3 illustrates a mask where identical patterns (31a,31b,31c,31d) are offset relative to each other [0023,0033,0057]. PNG media_image9.png 436 383 media_image9.png Greyscale The use of chrome to block the light is disclosed [0032]. Ohmi et al. 20060104413 teaches the pattern portion 2709a in the master mask 2703 has a relatively small area of 32 mm.times.40 mm. That is, considering that the writing area of the general quadruple mask has the size of 132 mm.times.104 mm at maximum, it is 1/9 or less in terms of the area. Therefore, at least nine identical patterns of the pattern portion 2709a can be transferred and exposed onto the mask 2706 by step and repeat in a very short time (although depending on resist sensitivity, one pattern can be exposed in about one second) so that, as shown in FIG. 27, (c), nine pattern portions 2709b are formed on the mask 2706 in a short time. PNG media_image10.png 412 446 media_image10.png Greyscale Kleitman et al. 3669666 exemplifies a mask meeting the limitations for the first and second layout patterns, but does not exemplify a mask with third and fourth layout meeting the claim limitations.. It would have been obvious to one skilled in the art to modify the masks illustrated in any of figures 41,43,44 and 45 of Kleitman et al. 3669666 by forming the patterns sufficiently close to each other to ensure the accuracy of the image formed in the resist as taught in Oh KR 20080001439 and forming an array of multiple patterns staggered as in figure 3 of Mizumura 20120218537 so that they can be transferred at the same time and increase the throughput of the exposure process as taught by Ohmi et al. 20060104413 to reduce the time required to desired number of patterns/devices. An example array would have patterns PNG media_image11.png 469 650 media_image11.png Greyscale PNG media_image12.png 436 610 media_image12.png Greyscale Alternatively , it would have been obvious to modify the processes of forming the masks of figures 41,43,44 and 45 of Kleitman et al. 3669666 by forming a staggered array of these patterns in an arrangement similar to that of figure 3 of Mizumura 20120218537 using the same tape and techniques as used to form the first mask pattern.so that they can be transferred at the same time and increase the throughput of the exposure process as taught by Nakagawa JP 2017044721 and Ohmi et al. 20060104413 to reduce the time required to desired number of patterns/devices with a reasonable expectation of forming useful photomasks. In the modified rejection, the protrusions are not aligned. Claims 1,2 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kleitman et al. 3669666, in view of Mizumura 20120218537, Ohmi et al. 20060104413 and Oh KR 20080001439, further in view of Setsuda JP 2007065246 In addition to the basis above, it would have been obvious to one skilled in the art to modify the masks having staggered patterns rendered obvious by the combination of over Kleitman et al. 3669666, in view of Mizumura 20120218537, Ohmi et al. 20060104413 and Oh KR 20080001439 by forming a phase mask with phase shifting patterns of MoSi as taught in Setsuda JP 2007065246 with a reasonable expectation of forming a useful photomask. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tanaka 20100285409 teaches the mask having patterns PNG media_image13.png 440 577 media_image13.png Greyscale Itoh KR 20020015941 (machine translation attached) teaches a layout pattern including wiring (13) and dummy patterns (4a, 14a, 14b) PNG media_image14.png 538 595 media_image14.png Greyscale Setsuda JP 2010048860 (machine translation attached) teaches in figure 11 a photomask with staggered identical patterns. PNG media_image15.png 291 230 media_image15.png Greyscale Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Martin J Angebranndt whose telephone number is (571)272-1378. The examiner can normally be reached 7-3:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ching-Yu (Coris) Fung can be reached at 571-270-5713. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARTIN J ANGEBRANNDT/Primary Examiner, Art Unit 1737 August 6, 2026
Read full office action

Prosecution Timeline

Show 2 earlier events
Oct 21, 2025
Response Filed
Nov 13, 2025
Final Rejection mailed — §102, §103
Feb 12, 2026
Request for Continued Examination
Feb 15, 2026
Response after Non-Final Action
Apr 24, 2026
Non-Final Rejection mailed — §102, §103
Jul 13, 2026
Response Filed
Aug 10, 2026
Final Rejection mailed — §102, §103
Sep 30, 2026
Interview Requested

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
56%
Grant Probability
90%
With Interview (+34.0%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1381 resolved cases by this examiner. Grant probability derived from career allowance rate.

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