Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election of claims 9 – 20 without traverse, in the reply filed on 10/27/2025 is acknowledged. Applicant newly added claims 21 – 27. Claims 1 – 8 are canceled.
Newly submitted claims 21-27 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Claims 9-20, drawn to a semiconductor structure classified in H10D 62/121. Claims 21-27 drawn to a semiconductor structure classified in H10D 30/6757. They are distinct in that they are classified in two different areas. The inventions have a materially different design. Claims 9-20 require a dielectric fin, the first gate isolation feature has a bow-tie shape in a top view, the second length is at least about 1.2 times the first length, a dielectric material forming spacers on sidewalls of each of the first, second and third gate segments, and the first gate isolation feature includes a first composition of a high dielectric constant material. Claims 21-27 require a bottommost surface of the first isolation structure is higher than a bottommost surface of the second isolation structure, the first segment of the gate stack interfaces an upper surface of each of the plurality of channel layers.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21 – 27 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Greene ( Pub. No. US 20200135575 A1 ), hereinafter Greene; in view of Peng ( Pub. No. US 20210083091 A1 ), hereinafter Peng; in view of Chen ( Pub. No. US 20210313181 A1 ), hereinafter Chen.
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Regarding Independent Claim 9 (Currently Amended), Greene teaches a semiconductor structure, comprising:
a dielectric fin (Greene, FIG. 7, 110 on the left; [0034], interlayer dielectric 110) extending in a first direction;
a first stack of a plurality of nanostructures (Greene, FIG. 1, under gate 102 on the left, [0028], sacrificial gates 102) disposed adjacent a first sidewall of the dielectric fin (Greene, FIG. 7, 110 on the left; [0034]);
a second stack of a plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center, [0028], sacrificial gates 102) disposed adjacent a second sidewall of the dielectric fin (Greene, FIG. 7, 110 on the left; [0034]), the second sidewall opposing the first sidewall;
a third stack of a plurality of nanostructures (Greene, FIG. 7, under gate 702 on the right, under active gate 304; [0028], sacrificial gates 102; [0043], active gate 304) spaced a distance from the second stack of the plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center), wherein a shallow trench isolation (STI) (Greene, FIG. 7, STI 104 under the right ILD 110; [0028], shallow trench isolation (STI) 104) is between the second stack of the plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center) and the third stack of the plurality of nanostructures (Greene, FIG. 7, under gate 702 on the right, under active gate 304);
a first gate segment (Greene, FIG. 1, gate 102 on the left, [0028], sacrificial gates 102) disposed over and between the first stack of the plurality of nanostructures (Greene, FIG. 1, under gate 102 on the left), a second gate segment (Greene, FIG. 1, gate 102 at the center, [0028], sacrificial gates 102) disposed over and between the second stack of the plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center), and a third gate segment (Greene, FIG. 7, gate 702 on the right, active gate 304) disposed over and between the third stack of the plurality of nanostructures (Greene, FIG. 7, under gate 702 on the right, under active gate 304), wherein each of the first, second and third gate segments extend in a second direction, perpendicular to the first direction;
a second gate isolation feature (Greene, FIG. 7, 110 on the right; [0034], interlayer dielectric 110) between the second gate segment (Greene, FIG. 1, gate 102 at the center) and the third gate segment (Greene, FIG. 7, gate 702 on the right, active gate 304), wherein the second gate isolation feature (Greene, FIG. 7, 110 on the right) extends to interface an upper surface of the STI (Greene, FIG. 7, STI 104 under the right ILD 110; [0028], shallow trench isolation (STI) 104); and
Greene fails to disclose:
a first gate isolation feature between the first gate segment and the second gate segment, wherein the first gate isolation feature extends to interface an upper surface the dielectric fin;
However, Peng teaches:
a first gate isolation feature (Peng, [0021], Although not shown, in some embodiments, dielectric fins may be formed at block 102 of method 100. In those embodiments, after the dielectric material is deposited to form the dielectric layer, the dielectric layer is patterned to form slits that extend in parallel with the fin elements 210 … The dielectric fins may also be referred to as dummy fins or hybrid fins. In some alternative embodiments, an upper portion of the dielectric fins may be removed during a gate cut process and replaced by a dielectric material that may be different or similar to that of the dielectric fins ) between the first gate segment and the second gate segment, wherein the first gate isolation feature extends to interface an upper surface the dielectric fin;
Greene and Peng are both considered to be analogous to the claimed invention because they are forming gate cut structures and dielectric fins for transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Greene ( first gate segment and the second gate segment ), to incorporate the teachings of Peng ( an upper portion of the dielectric fins ), to implement that the first gate isolation feature between the first gate segment and the second gate segment, wherein the first gate isolation feature extends to interface an upper surface the dielectric fin. Doing so would provide specific gate cut structures and dielectric fins for transistors, and therefore the performance of gates isolation can be improved.
Greene and Peng fail to disclose:
wherein in a top view the first gate isolation feature has a first length measured at a center line of the first gate segment and a second length at a line collinear with an edge of the first gate segment, wherein the second length is at least about 1.2 times the first length.
However, Chen teaches:
wherein in a top view the first gate isolation feature ( Chen, FIG. 26D, 74; [0049], trench 74; FIG. 33, center area of 85A or 82; [0066], boxes marked 85A and 85B are each a gate cut region of the FinFETs; [0057], FIGS. 27A, 27B, and 27C illustrate the formation of dielectric (or isolation) region 82 ) has a first length ( Chen, FIG. 26D, W8 ) measured at a center line of the first gate segment ( Chen, FIG. 26D, 60; [0042], gate stack 60 ) and a second length ( Chen, FIG. 26D, the length which is along the edge of 60, and between W7 and W8, approximately equal to W7 ) at a line collinear with an edge of the first gate segment ( Chen, FIG. 26D, 60; [0042], gate stack 60 ), wherein the second length is at least about 1.2 times ( Chen, [0055], Each of the openings 70A, 70B, and 70C may merge together to form a bow-tie shaped opening, a dog-bone shaped opening, or a peanut shaped opening. … In some embodiments, the openings 70C may have a width W8 between about 60% and 90% of the width W7, though other values are contemplated and may be used ) the first length.
Greene, Peng and Chen are all considered to be analogous to the claimed invention because they are forming gate cut structures and dielectric fins for transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Greene and Peng ( first gate segment and the second gate segment, an upper portion of the dielectric fins ), to incorporate the teachings of Chen ( shape design for trenches / dielectric isolation regions, FIG. 26D, FIG. 33, [0055], openings 70A, 70B, and 70C … a bow-tie shaped opening … W8 between about 60% and 90% of the width W7), to implement that wherein in a top view the first gate isolation feature has a first length measured at a center line of the first gate segment and a second length at a line collinear with an edge of the first gate segment, wherein the second length is at least about 1.2 times the first length. Doing so would provide specific gate cut structures and dielectric fins for transistors, and therefore the performance of gates isolation can be improved.
Regarding Claim 10 (Original), Greene, Peng and Chen teach the semiconductor structure as claimed in claim 9, on which this claim is dependent, Chen further teaches:
wherein the first length ( Chen, FIG. 26D, W8 ) and the second length ( Chen, FIG. 26D, the length which is along the edge of 60, and between W7 and W8, approximately equal to W7 ) are measured from a gate dielectric layer of the first gate segment ( Chen, FIG. 26D, 60 above W7 ) to a gate dielectric layer of the second gate segment ( Chen, FIG. 26D, 60 below W7 ).
Regarding Claim 11 (Original), Greene, Peng and Chen teach the semiconductor structure as claimed in claim 9, on which this claim is dependent, Greene and Peng further teach:
wherein the first gate isolation feature ( Greene, FIG. 7, 110 on the left; Peng, [0021], an upper portion of the dielectric fins; Chen, FIG. 26D, 74; FIG. 33, center area of 85A or 82 ) interfaces a gate dielectric layer ( Peng, [0044], high-K gate dielectric layer 242 ) of the first gate segment ( Greene, FIG. 1, gate 102 on the left ) and a gate dielectric layer ( Peng, [0044], high-K gate dielectric layer 242 ) of the second gate segment ( Greene, FIG. 1, gate 102 at the center ), and wherein the second gate isolation feature ( Greene, FIG. 7, 110 on the right ) interfaces a gate electrode layer ( Peng, [0044], gate electrode layer 244 ) of the second gate segment ( Greene, FIG. 1, gate 102 at the center ).
Regarding Claim 12 (Original), Greene, Peng and Chen teach the semiconductor structure as claimed in claim 9, on which this claim is dependent, Greene further teaches:
wherein a dielectric material ( Greene, [0034], The interlayer dielectric 110 can be made of any suitable dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials ) of the first gate isolation feature ( Greene, FIG. 7, 110 on the left ) is different than a dielectric material ( Greene, [0034], The interlayer dielectric 110 can be made of any suitable dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials ) of the second gate isolation feature ( Greene, FIG. 7, 110 on the right ).
Peng also further teaches:
wherein a dielectric material of the first gate isolation feature ( Peng, [0021], an upper portion of the dielectric fins; Chen, FIG. 26D, 74; FIG. 33, center area of 85A or 82 ) is different (Peng, [0021], an upper portion of the dielectric fins may be removed during a gate cut process and replaced by a dielectric material that may be different or similar to that of the dielectric fins) than a dielectric material of the second gate isolation feature.
Regarding Claim 13 (Original), Greene, Peng and Chen teach the semiconductor structure as claimed in claim 9, on which this claim is dependent, Greene further teaches:
wherein a dielectric material ( Greene, [0034], The interlayer dielectric 110 can be made of any suitable dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials ) of the first gate isolation feature ( Greene, FIG. 7, 110 on the left ) is a same composition as a dielectric material forming spacers on sidewalls ( Greene, FIG. 1, 108; [0033], The dielectric liner 108 can be made of any suitable material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ) of each of the first, second and third gate segments ( Greene, FIG. 1, gate 102 on the left, Greene, FIG. 1, gate 102 at the center, Greene, FIG. 1, gate 102 on the right ).
Regarding Claim 14 (Original), Greene, Peng and Chen teach the semiconductor structure as claimed in claim 9, on which this claim is dependent, Peng further teaches:
wherein the first gate isolation feature (Peng, [0021], an upper portion of the dielectric fins ) includes a first region of a first dielectric composition, a second region of a second dielectric composition, and a third region of a third dielectric composition ( Peng, FIG. 11, 222, 232, 234; [0025], In some implementations when the gate spacers 222 are formed of silicon nitride or silicon carbonitride; [0041], In some examples, the CESL 232 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. … In some embodiments, the ILD layer 234 includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials).
Claims 15 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Greene, in view of Peng.
Regarding Independent Claim 15 (Original), Greene teaches a semiconductor structure, comprising:
a dielectric fin (Greene, FIG. 7, 110 on the left; [0034], interlayer dielectric 110) extending vertically above a substrate;
a first plurality of nanostructures (Greene, FIG. 1, under gate 102 on the left, [0028], sacrificial gates 102) and a second plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center, [0028], sacrificial gates 102) extending substantially horizontally, the dielectric fin (Greene, FIG. 7, 110 on the left) disposed between the first plurality of nanostructures (Greene, FIG. 1, under gate 102 on the left) and the second plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center);
a first gate segment (Greene, FIG. 1, gate 102 on the left, [0028], sacrificial gates 102) disposed over and between the first plurality of nanostructures (Greene, FIG. 1, under gate 102 on the left) and
a second gate segment (Greene, FIG. 1, gate 102 at the center, [0028], sacrificial gates 102) disposed over and between the second plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center);
a second gate isolation feature (Greene, FIG. 7, 110 on the right; [0034], interlayer dielectric 110) disposed on a shallow trench isolation (STI) (Greene, FIG. 7, STI 104 under the right ILD 110; [0028], shallow trench isolation (STI) 104) had spaced a distance from the second plurality of nanostructures (Greene, FIG. 1, under gate 102 at the center).
Greene fails to disclose:
a first gate isolation feature disposed between the first gate segment and the second gate segment and on the dielectric fin;
wherein the first gate isolation feature has a different composition than the second gate isolation feature.
However, Peng teaches:
a first gate isolation feature (Peng, [0021], Although not shown, in some embodiments, dielectric fins may be formed at block 102 of method 100. In those embodiments, after the dielectric material is deposited to form the dielectric layer, the dielectric layer is patterned to form slits that extend in parallel with the fin elements 210 … The dielectric fins may also be referred to as dummy fins or hybrid fins. In some alternative embodiments, an upper portion of the dielectric fins may be removed during a gate cut process and replaced by a dielectric material that may be different or similar to that of the dielectric fins ) disposed between the first gate segment and the second gate segment and on the dielectric fin;
wherein the first gate isolation feature has a different ( Peng, [0021], an upper portion of the dielectric fins may be removed during a gate cut process and replaced by a dielectric material that may be different or similar to that of the dielectric fins )composition than the second gate isolation feature ( Greene, [0034], The interlayer dielectric 110 can be made of any suitable dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials ).
Greene and Peng are both considered to be analogous to the claimed invention because they are forming gate cut structures and dielectric fins for transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Greene ( first gate segment and the second gate segment ), to incorporate the teachings of Peng ( an upper portion of the dielectric fins ), to implement that a first gate isolation feature disposed between the first gate segment and the second gate segment and on the dielectric fin; wherein the first gate isolation feature has a different composition than the second gate isolation feature. Doing so would provide specific gate cut structures and dielectric fins for transistors, and therefore the performance of gates isolation can be improved.
Regarding Claim 16 (Original), Greene and Peng teach the semiconductor structure as claimed in claim 15, on which this claim is dependent, Greene further teaches:
wherein the first gate isolation feature ( Greene, FIG. 7, 110 on the left ) includes a first composition ( Greene, [0034], The interlayer dielectric 110 can be made of any suitable dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials ) and wherein gate spacers abutting sidewalls ( Greene, FIG. 1, 108; [0033], The dielectric liner 108 can be made of any suitable material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN ) of the first gate segment and the second gate segment comprise the first composition ( e.g. carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides ).Regarding Claim 17 (Original), Greene and Peng teach the semiconductor structure as claimed in claim 16, on which this claim is dependent, Peng further teaches:
wherein the first gate isolation feature (Peng, [0021], an upper portion of the dielectric fins ) further includes a second composition ( Peng, FIG. 11, 222, 232, 234; [0025] ), wherein a contact etch stop layer ( Peng, FIG. 11, 232; [0041], In some examples, the CESL 232 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art ) formed adjacent the gate spacers ( Peng, FIG. 11, 222; [0025], gate spacers 222 ) has the second composition.Regarding Claim 18 (Original), Greene and Peng teach the semiconductor structure as claimed in claim 15, on which this claim is dependent, Greene further teaches:
wherein the first gate isolation feature ( Greene, FIG. 7, 110 on the left ) includes a first composition of a high dielectric constant material ( Greene, [0034], The interlayer dielectric 110 can be made of any suitable dielectric material, such as, for example, … silicon nitrides … ).
Regarding Claim 19 (Original), Greene and Peng teach the semiconductor structure as claimed in claim 15, on which this claim is dependent, Greene and Peng further teach:
wherein the second gate isolation feature ( Greene, FIG. 7, 110 on the right ) has a direct interface with a gate electrode ( Peng, [0044], gate electrode layer 244 ) of the second gate segment ( Greene, FIG. 1, gate 102 at the center ).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Greene, in view of Peng, as applied to claim 15 above, and further in view of Chen.
Regarding Claim 20 (Original), Greene and Peng teach the semiconductor structure as claimed in claim 15, on which this claim is dependent,
Greene and Peng fail to disclose:
wherein the first gate isolation feature has a bow-tie shape in a top view, wherein the bow-tie shape has a first width in a center portion and a second width at a first edge and a second edge, the second width greater than the first width.
However, Chen teaches:
wherein the first gate isolation feature ( Chen, FIG. 26D, 74; [0049], trench 74; FIG. 33, center area of 85A or 82; [0066], boxes marked 85A and 85B are each a gate cut region of the FinFETs; [0057], FIGS. 27A, 27B, and 27C illustrate the formation of dielectric (or isolation) region 82 ) has a bow-tie shape ( Chen, [0055], Each of the openings 70A, 70B, and 70C may merge together to form a bow-tie shaped opening ) in a top view, wherein the bow-tie shape has a first width in a center portion and a second width at a first edge and a second edge, the second width greater than the first width ( Chen, [0055], In some embodiments, the openings 70C may have a width W8 between about 60% and 90% of the width W7, though other values are contemplated and may be used ).
Greene, Peng and Chen are all considered to be analogous to the claimed invention because they are forming gate cut structures and dielectric fins for transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Greene and Peng ( first gate segment and the second gate segment, an upper portion of the dielectric fins ), to incorporate the teachings of Chen ( shape design for trenches / dielectric isolation regions, FIG. 26D, FIG. 33, [0055], openings 70A, 70B, and 70C … a bow-tie shaped opening … W8 between about 60% and 90% of the width W7), to implement that the first gate isolation feature has a bow-tie shape in a top view, the bow-tie shape has a first width in a center portion and a second width at a first edge and a second edge, the second width greater than the first width. Doing so would provide specific gate cut structures and dielectric fins for transistors, and therefore the performance of gates isolation can be improved.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817