DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 & 7 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2011/0049575) by Tanaka et al (“Tanaka”) in view of (US-5,742,099) by Debnath et al (“Debnath”) and further in view of (US-2023/0092184) by Schultz et al (“Schultz”).
Regarding claim 1, Tanaka discloses in FIGs. 7, 11 & 13 and related text, e.g., a layout structure (FIG. 11 shows layout structure; so do other cited figures) of a high-drive-multiple standard cell (each one of FIGs. 7, 11 & 13 are “high-drive-multiple” standard cells, as can be seen simply by comparing the size of their PMOS transistors to those in the figures NOT cited; such as FIG. 8, which shows much smaller PMOS transistors; hence, meeting limitations) library (standard cells come in libraries; this is notoriously well-known), wherein the layout structure of the high-drive-multiple standard cell library at least comprises:
a power line track (FIG. 11, VDD) disposed in the middle of a standard cell along a length direction thereof (see FIG. 11), a length of the power line track being in flush with a width of the standard cell (see FIG. 11);
ground wires (VSS) located at topmost and bottommost positions of the standard cell, the ground wires being connected to the first-layer metal wires (39S1 & 39S2; both “1M”);
PMOS transistors (see 13P; multiple transistors shown, as evidenced by the gates 25/26) located directly below the power line track (see FIG. 11); and
NMOS transistors (11N & 12N) located at upper and lower ends of the standard cell (see FIG. 11) and adjacent to the ground wires (see FIG. 11),
wherein the first-layer metal wires are connected to top-layer metal wires (2M is the top layer being shown in FIG. 11; thus meeting the limitations of “top-layer”).
Tanaka does not disclose “an intermediate wiring of the power line track is routed through a transverse metal wire above the first-layer metal wires”.
However, the above features – related to arrangement of layers in order - are notoriously well-known and well-understood. Below, Debnath provides the necessary illustration.
Tanaka also does not disclose “two ends of the power line track being respectively provided with first-layer metal wires, a length direction of the first-layer metal wires being along the length direction of the standard cell”.
However, such an arrangement is known in the prior art, and Schultz illustrates it below.
Debnath discloses in FIG. 2 and related text, e.g., an intermediate wiring (in the instant case, Vcc(M3) wiring 231/237 is a power wiring, that is intermediate between Vcc(M2) and Vcc(M4)) of the power line track (Vcc) is routed through a transverse metal wire (Vcc(M3) is transverse to both Vcc(M2) - which Tanaka showed – and transverse to Vcc(M4)) above the first-layer metal wires (M3 is above first-layer metal wires).
Schultz discloses in FIG. 3 and related text, e.g., “two ends of the power line track (Metal 2, 160) being respectively provided with first-layer metal wires (Metal 1, 150), a length direction of the first-layer metal wires being along the length direction of the standard cell (see direction of 150; it is the same as Applicant’s own M1 example)”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Tanaka with “an intermediate wiring of the power line track is routed through a transverse metal wire above the first-layer metal wires” as taught by Debnath,
and with “two ends of the power line track being respectively provided with first-layer metal wires, a length direction of the first-layer metal wires being along the length direction of the standard cell” as taught by Schultz,
in order to simplify the processing steps of designing a standard cell, by arranging power and ground wiring in a notoriously well-known way, and interconnecting various wirings by notoriously well-understood methods (the Debnath reference was originally filed back in 1994; semiconductor industry is known to have a new generation of transistors every year or two; therefore there have been more than 10 generations of semiconductor products between Debnath and instant application; therefore, the teachings of Debnath are notoriously well-known, and notoriously well-understood [Wingdings font/0xE0] meaning: each layer, in order, being transverse to the one below, is a notoriously well-known and understood concept; Debnath shows an example of 4 layers; such arrangements of course can be extended to an arbitrary large number of layers; therefore, transverse wirings are a notoriously well-known and understood concept),
and in order to provide for local interconnect in vertical direction (par. 22 of Schultz), respectively.
Regarding claim 2, the combined device of Tanaka, Debnath and Schultz disclose in cited figures and related text, e.g., wherein the first-layer metal wires are further used for splicing with other cells (par. 33, “This placement allows on-die area for neighboring cells to be placed”).
Regarding claim 4, the combined device of Tanaka, Debnath and Schultz disclose in cited figures and related text, e.g., wherein the intermediate wiring of the power line track is realized through the transverse metal wire above the first-layer metal wires (as discussed in claim 1) so that PMOS and NMOS are connected above and below the first-layer metal wires (by definition [Wingdings font/0xE0] wiring has to connect from the very top metal power connection (whatever metal level that happens to be in particular design) to all the way down to the transistor itself, in order for power connection to be formed; Tanaka shows direct connection from M1 to the PMOS; that is the connection “below the first-layer metal wires”, the connection that goes down to transistor itself; Debnath shows that M1 power wires can go at least to M4; that is the connection “above … the first-layer metal wires”; hence, both types of connections – which are both necessary to have functional device – are shown).
Regarding claim 7, the combined device of Tanaka, Debnath and Schultz disclose in cited figures and related text, e.g., wherein an area of the standard cell is (2*N*Track) * (X*Wpmos / (2*Wpmos+Spmos) * Pitch), where Wpmos is a width of the PMOS transistors, Spmos is a spacing between the PMOS transistors, Pitch is a minimum distance between the first-layer metal wires along a transverse direction, Track is a minimum distance between the first-layer metal wires along a longitudinal direction, N is an integral multiple of 0.5, and X is a drive multiple of the standard cell (if Applicant’s own FIG. 1 (the embodiment of invention), then the FIG. 11 of Tanaka meets the limitations also; please note that in his own Specification, Applicant admits in par. 3 that the normal way to measure area of standard cell is “(N* track)* (X*pitch); then, he goes on to specify in the same paragraph, that his standard cell area can be calculated differently, by using the formula present in par. 3, and the instant claim; please note that this end is achieved through specific placement of PMOS and NMOS transistors (par. 10 & 11 of Applicant’s specification); please not that Tanaka does the same thing; hence, Tanaka also meets the claimed requirements; Tanaka has the top-to-bottom dimension that can be expressed as “2*N*Track”, per Applicant’s own definitions of terms, and as shown in his FIG. 1; Tanaka does same thing; furthermore, Tanaka’s left-to-right dimension can be expressed as “(X*Wpmos / (2*Wpmos+Spmos) * Pitch)”, since he has the same arrangement of transistors as Applicant in his own FIG. 1; thus Tanaka meets the same limitations as Applicant).
Response to Arguments
Applicant’s arguments with respect to above claims have been considered but are moot because the arguments do not apply to the current rejection.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
05/30/26
/Mounir S Amer/Primary Examiner, Art Unit 2818
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