DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-15, and embodiment b in Figs. 4A-4C, in the reply filed on 8/13/2025 is acknowledged. Claims 16-20 have been canceled. Claims 21-24 are added.
Applicant's election with traverse of group I, claims 1-15, and embodiment b in Figs. 4A-4C, in the reply filed on 8/13/2025 is acknowledged. The traversal is on the ground(s) that the Examiner has not established a serious search burden would be placed on the Examiner if the election was not required. This is not found persuasive because the Requirement of Election/Restriction has established this already.
To repeat what was stated in the Requirement of Election/Restriction, there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
the inventions have acquired a separate status in the art in view of their different classifications as listed above;
the inventions require a different field of search (for example, searching for structural elements required searching different classes/subclasses, or employing different search queries than searching for method steps).
searching for one of the inventions is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries, a different field of search is shown, even though the two may be classified together.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “wherein a third dimension of the first gate stack in the first direction is shorter than a fourth dimension of the second gate stack in the first direction” in claims 6-7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
None of the embodiments in the specification discloses a first gate stack is shorter than the second gate stack in the fin direction (first direction).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7, 21-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “wherein a third dimension of the first gate stack in the first direction is shorter than a fourth dimension of the second gate stack in the first direction”. Since this specification does not disclose that these gate stacks have different gate lengths, while implies they do have the same channel length. On the other hand, the total length of the gate and the source/drain region would be different between the first and second gate stacks. So it is unclear how the dimension of the gate stacks are defined in claims 6-7. For the purpose of examination, it is interpreted that the dimension of the gate stacks are defined arbitrarily.
Claim 21 recites “a first instance of a second gate stack, a second instance of the second gate stack” in lines 3-4 of the claim. The use of the term “instance” in this context is not common English and thus makes the scope of the claim unclear. The standard definition of the word “instance” is a step, a stage or a situation in a series of events, and carries a sense of time or a moment in time. The term does not involve a physical meaning (such as portion, part, segments…). So it is confusing and unclear what the Applicant means by “a first/second instance” of a “second gate stack”.
For the purpose of examination and to be consistent with the specification, the Examiner has interpreted “a second gate stack” as “a plurality of second gate stacks” and that the “first instance of a second gate stack” as a “first of the plurality of second gate stacks” and the “second instance of the second gate stack” as “a second of the plurality of second gate stacks”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2019/0109045 A1).
Regarding claim 1, Xie teaches a method (Figs. 3-12 of Xie, in particular view x-x of Figs. 9-10) for forming a semiconductor structure (structure in Fig. 10), comprising:
forming a fin structure (103 in Fig. 3) over a substrate in a first direction (x-direction);
forming a first gate stack (3), a second gate stack (6) and a third gate stack (2) across the fin structure;
removing the first gate stack to form a trench (gate 3 is removed to form opening 134 in Fig. 6), wherein the fin structure is cut into two segments by the trench (as shown in Fig. 6 and described in [0030] of Xie, the opening 134 extends through the fin 103 into the substrate 102 as trench 140 in the substrate 102);
depositing a cutting structure (as shown in Fig. 7 and [0031] of Xie, an insulating material is filled into the opening 134 and planarized to form an SDB structure 142) in the trench; and
forming a first contact plug (130B and 156B in Fig. 10) between the cutting structure and the second gate stack (as shown in Fig. 10, 130B and 156B extend between positions of 142 and the gate 6) and a second contact plug (150A and 156A) between the second gate stack and the third gate stack (as shown in Fig. 10, 150A and 156A extend between positions of gates 6 and 2), wherein a first dimension (length of 156B in x direction) of the first contact plug in the first direction is greater than a second dimension (length of 156A in x direction) of the second contact plug in the first direction.
Regarding claim 2, Xie teaches all limitations of the method for forming the semiconductor structure as claimed in claim 1, and also teaches wherein a first distance (distance between 130B and 142 in Fig. 10 of Xie) between the first contact plug and the cutting structure is shorter than a second distance (the distance between 130B and gate 6) between the first contact plug and the second gate stack.
Regarding claim 3, Xie teaches all limitations of the method for forming the semiconductor structure as claimed in claim 1, and also teaches wherein the first contact plug is in contact with the cutting structure (as shown in Fig. 10 of Xie).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Xie, as applied in claim 1 above, and further in view of Zhao et al. (US 9653583 B1).
Regarding claim 5, Xie teaches all limitations of the method for forming the semiconductor structure as claimed in claim 1, and further comprising: forming an isolation structure (104 in Fig. 3) surrounding a lower portion of the fin structure, wherein the first gate stack, the second gate stack and the third gate stack are formed over the isolation structure (as shown in Fig. 3 of Xie), but does not teach where a bottom surface of the cutting structure is lower than a bottom surface of the isolation structure.
Zhao teaches a gate cutting structure (123 in Fig. 2A-2O of Zhao). The gate cutting structure is formed by etching a trench (122 in Fig. 2J) through a gate structure (110) and the fin structure (106) into the substrate (102) such that the bottom surface of the trench is lower than a bottom surface of the isolation structure (108 in Fig. 2J) and then filling the trench with an insulating material.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the cutting structure of Xie so that the bottom surface of the cutting structure is lower than the bottom surface of the isolation structure, as according to Zhao, in order to better isolate the two transistors.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Xie.
Regarding claim 9, Xie teaches all limitations of the method for forming the semiconductor structure as claimed in claim 1, but does not explicitly teach wherein a ratio of the first dimension to the second dimension is in a range from about 1.05 to about 4.
However, it is implied from the Fig. 10 of Xie that the first dimension of the first contact plug (length of 156B) is at least twice the second dimension of the second contact plug.
Since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have made ratio of the first dimension to the second dimension is in a range from about 1.05 to about 4 in order to enable the signal to route to the proper location. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Allowable Subject Matter
Claims 4 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 10-15 are allowed.
Claims 21-25 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art of record does not disclose or fairly suggest a method for forming a semiconductor structure satisfying “wherein a first distance between the first gate stack and the second gate stack is greater than a second distance between the second gate stack and the third gate stack” along with other limitations of the claim 1.
Regarding claim 6, the prior art of record does not disclose or fairly suggest a method satisfying “wherein a third dimension of the first gate stack in the first direction is shorter than a fourth dimension of the second gate stack in the first direction” along with other limitations of claim 1.
Regarding claim 8, the prior art of record does not disclose or fairly suggest a method including a step of “forming a via directly over the cutting structure, the first contact plug and the second gate stack and the third gate stack, wherein the via is electrically connected to the first contact plug and electrically isolated from the second contact plug” along with other limitations of claim 1.
Regarding claim 10, the prior art of record does not disclose or fairly suggest a method for forming a semiconductor structure, comprising: “forming a first gate stack, a second gate stack and a third gate stack that are arranged consecutively in a first direction over the first fin structure, wherein the first source/drain feature is located between the first and second gate stacks, the second source feature is located between the second and third gate stacks, and a first distance between the first gate stack and the second gate stack is shorter than a second distance between the second gate stack and the third gate stack; replacing the first gate stack and the second gate stack with a first cutting structure and a second cutting structure, respectively” along with other limitations of the claim.
Regarding claim 21, the prior art of record does not disclose or fairly suggest a method for forming a semiconductor structure, comprising: “forming a first cutting structure in the first trench and a second cutting structure in the second trench; forming a first contact plug between the first cutting structure and the first instance of the second gate stack; forming a second contact plug between the second instance of the second gate stack and the second cutting structure; and forming a third contact plug between the first instance of the second gate stack and the second instance of the second gate stack, wherein a first dimension of the first contact plug in the first direction is different than a second dimension of the third contact plug in the first direction” along with other limitations of the claim.
The closest prior art are Xie et al. (US 2019/0109045 A1) and Wang et al. (US 2020/0044070 A1).
Regarding claim 1, Xie teaches a method (Figs. 3-12 of Xie, in particular view x-x of Figs. 9-10) for forming a semiconductor structure (structure in Fig. 10), comprising: forming a fin structure (103 in Fig. 3) over a substrate in a first direction (x-direction); forming a first gate stack (3), a second gate stack (6) and a third gate stack (2) across the fin structure; removing the first gate stack to form a trench (gate 3 is removed to form opening 134 in Fig. 6), wherein the fin structure is cut into two segments by the trench (as shown in Fig. 6 and described in [0030] of Xie, the opening 134 extends through the fin 103 into the substrate 102 as trench 140 in the substrate 102); depositing a cutting structure (as shown in Fig. 7 and [0031] of Xie, an insulating material is filled into the opening 134 and planarized to form an SDB structure 142) in the trench; and forming a first contact plug (130B and 156B in Fig. 10) between the cutting structure and the second gate stack (as shown in Fig. 10, 130B and 156B extend between positions of 142 and the gate 6) and a second contact plug (150A and 156A) between the second gate stack and the third gate stack (as shown in Fig. 10, 150A and 156A extend between positions of gates 6 and 2), wherein a first dimension (length of 156B in x direction) of the first contact plug in the first direction is greater than a second dimension (length of 156A in x direction) of the second contact plug in the first direction. However, Xie does not teach a second cutting structure or the dimension of the contact plugs that satisfy the recited claim limitations.
Wang teaches a semiconductor structure with multiple gate cutting structures (76 in Fig. 18 of Wang). However, Wang does not teach the difference in dimensions of the contact plugs or in the distances between the first and second gate stacks and between second to third gate stacks, or the difference in dimensions of the contact plugs. Wang does not provide a reasonable motivation to modify the structure as recited by the claims either.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898