DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Applicant’s IDS submitted on 11/22/23 and 2/13/23 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DYNAMIC RANDOM ACCESS MEMORY SEMICONDUCTOR DEVICE WITH PATTERNED CONDUCTIVE LAYER ARRANGED ON CAPACITOR
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 11, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, 10, 16, and 18 of U.S. Patent No. 11393821 B1 in view of Ozaki et al. US 5414655 A, hereafter Ozaki.
Regarding claim 1, Claims 1 and 7 of U.S. Patent No. 11393821 B1 claim the following:
A semiconductor device, comprising:
a substrate, comprising an array region (US 11393821 B1, claim 1, line 1, “memory array region”) and a peripheral region (US 11393821 B1, claim 7, line 2-3, “peripheral circuit region”), wherein and a conductive device is disposed in the substrate in the peripheral region (US 11393821 B1, claim 7, line 8, “second contact”);
a capacitor (US 11393821 B1, claim 1, line 3, “capacitor”);
a patterned conductive layer (US 11393821 B1, claim 1, line 9, “metal layer” and lines 11-12 “has openings”), disposed on the capacitor and comprising a pattern portion (US 11393821 B1, claim 1, line 9, lines 11-12 “has openings”) and a connection portion connected to the pattern portion (US 11393821 B1, claim 7, line 3, “interconnect structure”), wherein the pattern portion is located in the array region and exposes a part of the capacitor (US 11393821 B1, claim 1, line 9, lines 12-13 “openings expose the portion of the first conductive layer”), and the connection portion is extended into the peripheral region (US 11393821 B1, claim 7, line 8-9, the interconnect structure is connected to a second contact located in the peripheral circuit region); and
a contact, disposed on the substrate in the peripheral region and connecting the connection portion and the conductive device (US 11393821 B1, claim 7, line 6-9, the interconnect structure connects a first contact is located in the memory array region and a second contact is located in the peripheral circuit region).
Regarding claim 1, U.S. Patent No. 11393821 B1 claims 1 and 7 of do not claim the following:
a transistor is disposed in the substrate in the array region
disposed on the substrate and electrically connected to the transistor
Ozaki discloses in a DRAM device:
a transistor is disposed in the substrate in the array region (Ozalo, Figure col 2, lines 19-30, discloses a capacitor consisting of and upper and lower electrode with an insulator in between and a MOS transistor on the semiconductor substrate, and a peripheral circuit section formed on the semiconductor circuit in an area other than an area of the memory cell).
disposed on the substrate and electrically connected to the transistor (Ozaki, Figure 7, left hand side)
U.S. Patent No. 11393821 B1 claims the limitations of the instant claims failing only to claim a transistor in the substrate in the memory cell region and connected to the capacitor in the memory cell region. Ozaki, discloses a DRAM with an array region and a peripheral circuit region where the capacitors in the array region are on a substrate that contains switching transistors. It would have been obvious to one of ordinary skill in the art include transistors in the substrate that contains the capacitors since such transistors are necessary to the operation of a DRAM device and stacking the capacitors and transistors saves space on the wafer and increases memory density allowing for higher capacity memories.
Regarding claim 2, U.S. Patent No. 11393821 B1 claim 1 claims the following:
The semiconductor device of claim 1, wherein the capacitor comprises:
a first electrode, disposed on the substrate (US 11393821 B1, claim 1, line 5, “a first electrode located on the substrate”);
a second electrode, disposed on the first electrode (US 11393821 B1, claim 1, line 6, “a electrode”); and
an insulating layer, disposed between the first electrode and the second electrode (US 11393821 B1, claim 1, line 15-16, “an insulating layer located between the first electrode and the second electrode”).
Regarding claim 11, U.S. Patent No. 11393821 B1 claim 10, claims the following:
A manufacturing method of a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an array region (US 11393821 B1, claim 10, lines 3-4, “substrate comprises a memory array region”) and a peripheral region (US 11393821 B1, claim 16, lines 2-3, “substrate further comprises a peripheral circuit region”), and a conductive device is formed in the substrate in the peripheral region (US 11393821 B1, claim 16, lines 15, “second contact”);
forming a capacitor on the substrate in the array region (US 11393821 B1, claim 10, line 5, “forming a capacitor in the memory array region”),
forming a contact on the substrate in the peripheral region, wherein the contact is connected to the conductive device (US 11393821 B1, claim 16, lines 14-17, “second contact electrically connected to the interconnect structure”); and
forming a patterned conductive layer on the capacitor (US 11393821 B1, claim 10, lines 15-20, “metal layer has openings, the openings”), wherein the patterned conductive layer comprises a pattern portion (US 11393821 B1, claim 10, lines 15-20, “metal layer has openings, the openings”) and a connection portion connected to the pattern portion (US 11393821 B1, claim 16, lines 14-15, “first contact electrically connected to the metal layer”), the pattern portion is located in the array region and exposes a part of the capacitor (US 11393821 B1, claim 10, lines 18-19, “the openings expose the portion of the first conductive layer”), and the connection portion is extended into the peripheral region to connect to the contact (US 11393821 B1, claim 16, lines 15-20, interconnect structure is connected to the first contact in the array region and second contact in the peripheral region).
Regarding claim 11, U.S. Patent No. 11393821 B1 claim 10 does not claim the following:
a transistor is formed in the substrate in the array region,
wherein the capacitor is electrically connected to the transistor;
Ozaki discloses in a DRAM device:
a transistor is formed in the substrate in the array region (Ozalo, Figure col 2, lines 19-30, discloses a capacitor consisting of and upper and lower electrode with an insulator in between and a MOS transistor on the semiconductor substrate, and a peripheral circuit section formed on the semiconductor circuit in an area other than an area of the memory cell).
Wherein the capacitor is electrically connected to the transistor (Ozaki, Figure 7, left hand side)
U.S. Patent No. 11393821 B1 claims the limitations of the instant claims failing only to claim forming a transistor in the substrate in the memory cell region and connected to the capacitor in the memory cell region. Ozaki, discloses a DRAM with an array region and a peripheral circuit region where the capacitors in the array region are formed on a substrate that has switching transistors formed in it. It would have been obvious to one of ordinary skill in the art to have formed transistors in the substrate that contains the capacitors since such transistors are necessary to the operation of a DRAM device and stacking the capacitors and transistors saves space on the wafer and increases memory density thereby allowing for higher capacity memories.
Regarding claim 17, U.S. Patent No. 11393821 B1, claim 18, which depends from claim 10, claims the following:
The method of claim 11, further comprising performing an H2 sintering process after the patterned conductive layer is formed (US 11393821 B1, claim 18, line 3, “performing hydrogen sintering”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 11, and 17 are rejected under 35 U.S.C. 103 as being obvious over Manabe et al., US 11393821 B1, hereafter Manabe in view of Ozaki et al., US 5414655 A, hereafter Ozaki.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Regarding claim 1, Manabe discloses the following:
A semiconductor device, comprising:
a substrate, comprising an array region, and a peripheral region (Manabe, Figure 7E substrate 100, and col 9, lines 46-47, “substrate 100 may include the memory array region R1 and the peripheral circuit region R2”), wherein and a conductive device is disposed in the substrate in the peripheral region (Manabe, Figure 7E, “interconnect structure 102 in the peripheral circuit region R2”);
a capacitor (Manabe, Figure 7E, capacitor 316 is located in the memory array region R1),
a patterned conductive layer (Manabe, Figure 7E, metal layer 304b and contact 326), disposed on the capacitor and comprising a pattern portion (Manabe, shown Figure 7E, metal layer 304b) and a connection portion connected to the pattern portion (Manabe, Figure 7E, contact 326), wherein the pattern portion is located in the array region and exposes a part of the capacitor (Manabe, Figure 7E, opening 312 exposes a portion of the conductive layer 114a), and the connection portion is extended into the peripheral region (Manabe, Figure 7E, contact 326); and
a contact, disposed on the substrate in the peripheral region and connecting the connection portion and the conductive device (Manabe, Figure 7E, contact 330 electrically connected to the interconnect structure 102).
Regarding claim 1, Manabe fails to disclose the following:
a transistor is disposed in the substrate in the array region
disposed on the substrate and electrically connected to the transistor
connecting the connection portion and the conductive device
Ozaki discloses in a DRAM device:
a transistor is disposed in the substrate in the array region (Ozalo, Figure col 2, lines 19-30, discloses a capacitor consisting of and upper and lower electrode with an insulator in between and a MOS transistor on the semiconductor substrate, and a peripheral circuit section formed on the semiconductor circuit in an area other than an area of the memory cell).
disposed on the substrate and electrically connected to the transistor (Ozaki, Figure 7, left hand side)
Manabe claims the limitations of the instant claims failing only to claim a transistor in the substrate in the memory cell region and connected to the capacitor in the memory cell region. Ozaki, discloses a DRAM with an array region and a peripheral circuit region where the capacitors in the array region are on a substrate that contains switching transistors. It would have been obvious to one of ordinary skill in the art include transistors in the substrate that contains the capacitors since such transistors are necessary to the operation of a DRAM device and stacking the capacitors and transistors saves space on the wafer and increases memory density allowing for higher capacity memories.
Regarding claim 2, Manabe further discloses the following:
The semiconductor device of claim 1, wherein the capacitor comprises:
a first electrode, disposed on the substrate (Manabe, col. 1, line 66- col. 2, line 6, discloses forming a first electrode on the substrate);
a second electrode, disposed on the first electrode (Manabe, col. 1, line 66- col. 2, line 6, discloses forming a second electrode on the substrate); and
an insulating layer, disposed between the first electrode and the second electrode (Manabe, col. 1, line 66- col. 2, line 6, discloses forming an insulating layer on the first electrode).
Regarding claim 11, Manabe discloses the following:
A manufacturing method of a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an array region and a peripheral region (Manabe, Figure 7E substrate 100, and col 9, lines 46-47, “substrate 100 may include the memory array region R1 and the peripheral circuit region R2”), and a conductive device is formed in the substrate in the peripheral region (Manabe, Figure 7E, “interconnect structure 102 in the peripheral circuit region R2”);
forming a capacitor on the substrate in the array region (Manabe, Figure 7E, capacitor 316 is located in the memory array region R1),
forming a contact on the substrate in the peripheral region, wherein the contact is connected to the conductive device (Manabe, Figure 7E, contact 330 electrically connected to the interconnect structure 102; and
forming a patterned conductive layer on the capacitor (Manabe, Figure 7E, metal layer 304b and opening 312 exposes a portion of the conductive layer 114a), wherein the patterned conductive layer comprises a pattern portion (Manabe, Figure 7E, metal layer 304b) and a connection portion connected to the pattern portion (Manabe, Figure 7E, contact 326), the pattern portion is located in the array region and exposes a part of the capacitor(Manabe, Figure 7E, metal layer 304b and opening 312 exposes a portion of the conductive layer 114a), and the connection portion is extended into the peripheral region to connect to the contact (Manabe, Figure 7E, contact 320 and 330).
Regarding claim 11, Manabe does not disclose the following:
a transistor is formed in the substrate in the array region,
wherein the capacitor is electrically connected to the transistor;
Ozaki discloses in a DRAM device:
a transistor is formed in the substrate in the array region (Ozalo, Figure col 2, lines 19-30, discloses a capacitor consisting of and upper and lower electrode with an insulator in between and a MOS transistor on the semiconductor substrate, and a peripheral circuit section formed on the semiconductor circuit in an area other than an area of the memory cell).
Wherein the capacitor is electrically connected to the transistor (Ozaki, Figure 7, left hand side)
Manabe claims the limitations of the instant claims failing only to claim forming a transistor in the substrate in the memory cell region and connected to the capacitor in the memory cell region. Ozaki, discloses a DRAM with an array region and a peripheral circuit region where the capacitors in the array region are formed on a substrate that has switching transistors formed in it. It would have been obvious to one of ordinary skill in the art to have formed transistors in the substrate that contains the capacitors since such transistors are necessary to the operation of a DRAM device and stacking the capacitors and transistors saves space on the wafer and increases memory density thereby allowing for higher capacity memories.
Regarding claim 17, Manabe further discloses the following:
The method of claim 11, further comprising performing an H2 sintering process after the patterned conductive layer is formed (Manabe, claim 18, line 3, “performing hydrogen sintering”).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claims 1-4, 10, 11, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sills, US 20200219886 A1, hereafter Sills in view of Ozaki et al., US 5414655 A, hereafter Ozaki
Regarding claim 1, Sills discloses the following limitations:
A semiconductor device (Sills, Figures 2-20, construction 12), comprising:
a substrate (Sills, Figure 19, and [0030] base substrate 13), comprising an array region (Sills, 19, region containing second transistors 20 array of 2T-1C memory cells) wherein a transistor is disposed in the substrate in the array region (Sills, Figure 19, transistors 20)
a capacitor (Sills, Figure 11, first capacitor node 42, capacitor dielectric material 44, and second capacitor node 46), disposed on the substrate and electrically connected to the transistor (Sills, the series of first current node 26 across Figure 21 alternate between connecting first capacitor node 43 to channel region 28 and second capacitor node 46 to channel region 28);
a patterned conductive layer (Sills, Figure 21, conductive material 64), disposed on the capacitor and comprising a pattern portion (Sills, Figure 21, show conductive material 64 has a pattern) and wherein the pattern portion is located in the array region and exposes a part of the capacitor (Sills, Shown, Figure 21, conductive material 64),
Sils fails to disclose:
a peripheral region
a conductive device is disposed in the substrate in the peripheral region
a connection portion connected to the pattern portion,
the connection portion is extended into the peripheral region
a contact, disposed on the substrate in the peripheral region and connecting the connection portion and the conductive device.
Ozaki discloses the following limitations:
a peripheral region (Ozaki, Figure 13, right hand side, and col. 7, lines 21-23, which discloses that contact holes 28 are in the peripheral circuit section)
a conductive device is disposed in the substrate in the peripheral region (Ozaki, Figure 22, 29 right hand side)
a connection portion connected to the pattern portion (Ozaki, Figure 22, first metal layers 55),
the connection portion is extended into the peripheral region (Ozaki, Figure 22, first metal layer 55 extends from the array to the peripheral region)
a contact, disposed on the substrate in the peripheral region and connecting the connection portion and the conductive device (Ozaki, Figure 22, portion of 55 in the contact hole 28).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Ozaki to the device of Sils, and to therefore have combined the memory cell of Sills with a peripheral circuit as taught by Ozaki. Doing so would produce a desirable memory cell containing the circuitry necessary for the memory device to function using the memory cell of Sills.
Regarding claim 2, Sills discloses the following limitations:
The semiconductor device of claim 1, wherein the capacitor comprises:
a first electrode (Sills, Figure 21, first capacitor node 42), disposed on the substrate;
a second electrode (Sills, Figure 21, second capacitor node 46), disposed on the first electrode;
an insulating layer (Sills, Figure 21, capacitor dielectric 44), disposed between the first electrode and the second electrode.
Regarding claim 3, Sills discloses the following limitations:
The semiconductor device of claim 2, wherein the top surface of the contact and the top surface of the second electrode are located at the same level (Sills, Figure 21, the top of capacitor dielectric 44 it the top of the capacitor).
Regarding claim 4, Sills and Ozaki disclose the following limitations:
The semiconductor device of claim 2, wherein the top surface of the contact is lower than the top surface of the second electrode (In the combination of Sills and Ozaki, the top surface of the capacitor is lower than the top surface of second electrode 55 of Ozaki).
Regarding claim 10, Sills discloses the following limitations:
The semiconductor device of claim 1, wherein the pattern portion of the patterned conductive layer has a uniform width from the top surface to the bottom surface (Sills, Figure 21, conductive material 64 has a uniform width).
Regarding claim 11, Sills discloses the following limitations:
A manufacturing method of a semiconductor device (Sills, Figures 2-20, construction 12), comprising:
providing a substrate (Sills, Figure 19, and [0030] base substrate 13), wherein the substrate comprises an array region (Sills, 19, region containing second transistors 20 array of 2T-1C memory cells), a transistor is formed in the substrate in the array region (Figure 19, transistors 20)
forming a capacitor (Sills, Figure 11, first capacitor node 42, capacitor dielectric material 44, and second capacitor node 46) on the substrate in the array region, wherein the capacitor is electrically connected to the transistor (Sills, the series of first current node 26 across Figure 21 alternate between connecting first capacitor node 43 to channel region 28 and second capacitor node 46 to channel region 28);
forming a contact on the substrate in the peripheral region, wherein the contact is connected to the conductive device; and
forming a patterned conductive layer on the capacitor (Sills, Figure 21, conductive material 64), wherein the patterned conductive layer comprises a pattern portion (Sills, Figure 21, show conductive material 64 has a pattern) , the pattern portion is located in the array region and exposes a part of the capacitor (Sills, Shown, Figure 21, conductive material 64),
Sils fails to disclose:
a peripheral region,
a conductive device is formed in the substrate in the peripheral region;
a connection portion connected to the pattern portion
the connection portion is extended into the peripheral region to connect to the contact.
Ozaki discloses the following limitations:
a peripheral region (Ozaki, Figure 13, right hand side, and col. 7, lines 21-23, which discloses that contact holes 28 are in the peripheral circuit section)
a conductive device is formed in the substrate in the peripheral region (Ozaki, Figure 22, 29 right hand side)
a connection portion connected to the pattern portion (Ozaki, Figure 22, first metal layers 55),
the connection portion is extended into the peripheral region to connect to the contact (Ozaki, Figure 22, first metal layer 55 extends from the array to the peripheral region)
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Ozaki to the method of Sils, and to therefore have combined the method of making a memory cell of Sills with a peripheral circuit as taught by Ozaki. Doing so would produce a desirable method of making a memory cell containing the circuitry necessary for the memory device to function using the memory cell of Sills.
Regarding claim 15, Sills discloses the following limitations:
The method of claim 11, wherein a forming method of the patterned conductive layer comprises:
forming a conductive material layer on the capacitor (Sills, [0045] conductive material 64 is deposited) after forming the contact; and
performing a patterning process on the conductive material layer (Sills, [0045] patterning conductive material 64).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sills and Ozaki as applied to claim 2 above, and further in view of Kugimiya et al., 20170207223 A1, hereafter Kugimiya.
Regarding claim 5, Sills and Ozaki fail to disclose the following limitations:
The semiconductor device of claim 2, wherein a material of the second electrode comprises a doped semiconductor material.
Lou discloses the following limitations:
The semiconductor device of claim 2, wherein a material of the second electrode comprises a doped semiconductor material (Lou, col. 5 lines 25-32, discloses polysilicon electrodes for capacitor).
Sills and Ozaki teach all of the limitations of the claimed invention except for the use of polysilicon for the electrode of the capacitor. Lou teaches that the use of polysilicon for electrodes of capacitors. It would have been obvious to one of ordinary skill in the art to substitute one known electrode material for another known electrode material resulting in the predictable result of forming an electrode for a capacitor.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sills and Ozaki as applied to claim 1 above, and further in view of LaRoche et al., US 9478508 B1, hereafter LaRoche.
Regarding claim 6, Sills and Ozaki fail to disclose the following limitations:
The semiconductor device of claim 1, further comprising a first dielectric layer, wherein the capacitor and the contact are located in the first dielectric layer, and the top surface of the capacitor, the top surface of the contact and the top surface of the first dielectric layer are located at the same level.
LaRoche discloses the following limitations:
further comprising a first dielectric layer (Figure 2, dielectric structure 22, not including the top layer), wherein the capacitor (Figure 2, capacitor 24 and via V2, second metal layer M2, and strip conductor 19, bottom two layers, over V2) and the contact (Figure 2, strip conductor 19, bottom two layers, not over V2) are located in the first dielectric layer, and the top surface of the capacitor, the top surface of the contact and the top surface of the first dielectric layer are located at the same level (Figure 2, shows a flat top surface, in the layer before the top layer).
It would have been obvious one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of LaRoche to the device of Sills and Ozaki and to therefore have formed the capacitor with a flat top surface, doing so is taught by LaRoche and would desirably seal the electrodes and capacitor protecting them from damage.
Regarding claim 7, the combination of Sills, Ozaki, and LaRoche disclose the following limitations:
The semiconductor device of claim 6, further comprising a second dielectric layer (La Roche, Figure 2, top layer of dielectric structure 22) disposed on the capacitor and the first dielectric layer (LaRoche, Shown Figure 2), wherein the patterned conductive layer is located in the second dielectric layer (LaRoche, Figure 2, top layer of 19), and the top surface of the patterned conductive layer and the top surface of the second dielectric layer are located at the same level (Figure 2, top surface containing all layers is flat).
Claim 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sills and Ozaki as applied to claim 11 above, and further in view of LaRoche et al., US 9478508 B1, hereafter LaRoche.
Regarding claim 12, Sills and Ozaki fail to disclose the following limitations:
The method of claim 11, wherein after forming the capacitor and before forming the patterned conductive layer, the method further comprises:
forming a first dielectric layer on the substrate to cover the capacitor; and
performing a chemical mechanical polishing process to remove a part of the first dielectric layer until the top surface of the capacitor is exposed.
LaRoche discloses the following limitations:
wherein after forming the capacitor and before forming the patterned conductive layer, the method further comprises:
forming a first dielectric layer on the substrate to cover the capacitor (LaRoche, dielectric layer 22a); and
performing a chemical mechanical polishing process to remove a part of the first dielectric layer until the top surface of the capacitor is exposed (Figure 2, and col. 7 lines 20-40 discloses that the Damascene process using CMP is used to form the layers).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to have applied the teachings of LaRoche to the process of Sills and Ozaki and to therefore have used the chemical mechanical polishing (CMP) to form the metal layer in the dielectric layer such a process is known in the art and produces desirably flat surfaces.
Regarding claim 14, Sills, Ozaki and LaRoche discloses the following limitations:
The method of claim 12, wherein a forming method of the contact comprises:
forming a hole in the first dielectric layer in the peripheral region after the chemical mechanical polishing process, wherein the hole exposes a part of the conductive device; and
filling a conductive material in the hole (Figure 2, and col. 8 lines 8-21 discloses the steps of the Damascene which include opening a hole, depositing metal in the hole, and using chemical mechanical polishing to flatten the surface).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sills and Ozaki as applied to claim 11 above, and further in view of Kugimiya et al., 20170207223 A1, hereafter Kugimiya.
Regarding claim 17, Sills and Ozaki fails to disclose the following limitations:
The method of claim 11, further comprising performing an H2 sintering process after the patterned conductive layer is formed.
Kugimiya fails to discloses the following limitations:
The method of claim 11, further comprising performing an H2 sintering process after the patterned conductive layer is formed (Kugimiya, [0004] discloses the step of sintering is performed after the capacitor is formed).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to have applied the method of Kugimiya to the method of Sills and Ozaki and to therefore have hydrogen sintered the capacitor because Kugimiya teaches that doing so reduces the number of times of the refresh operation per unit time by improving the retention characteristic.
Allowable Subject Matter
Claims 8, 9, 13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, the prior art of record alone or in combination fails to teach a device with a the contact that is located in the first dielectric layer, the top surface of the first dielectric layer is lower than the top surface of the capacitor, and the top surface of the contact and the top surface of the first dielectric layer are located at the same level.
Regarding claim 9, claim 9 depends form claim 8 and therefore contains all of the limitations of claim 8, and is therefore allowable for the same reasons.
Regarding claim 13, the prior art of record fails to disclose the use of an etch back process after the chemical mechanical polishing so that the top surface of the dielectric layer is below the top surface of the capacitor.
Regarding claim 16, the prior art of record fails to teach forming a second dielectric layer on the capacitor and the contact after forming the contact and forming a contact in the hole in the dielectric layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Peng et al., US 20220068930 A1, discloses a capacitor with a patterned contact.
Kuroki, US 20110194276 A1, discloses a capacitor with an electrode that extends to the peripheral region.
Nakamura, US 20010044181 A1, discloses a device with a memory cell region and a peripheral circuit region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 10-2 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LINDA J. FLECK/ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
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