DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 3/20/2026. Claims 10-29 are pending in this application. Claims 1-9 are canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 10-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 10,157,790) in view of Cheng et al. (US 10,236,364).
Re claim 10, You teaches, under BRI, Figs. 22-23, cols. 7 & 10-14, a semiconductor device structure, comprising:
-a gate structure (110A, 128A) formed over a substrate (102), wherein the gate structure (110A, 128A) comprises a gate dielectric layer (110A) and a gate electrode (128A);
-a conductive layer (134A or 166) formed over the gate electrode (128A);
-a gate spacer (120A, B) formed adjacent to the gate structure (110A, 128A);
-a source/drain (S/D) contact structure (140A-B, 154A) formed adjacent to the gate spacer (120A, B);
-a conductive via structure (170B) formed over the S/D contact structure (140A-B, 154A), wherein the conducive via structure (170B) is over the gate spacer (120A, B); and
-an insulating layer (156A) formed over the S/D contact structure (140A-B, 154A), wherein a top surface of the S/D contact structure (140A-B, 154A) is covered by the conductive via structure (170B) and the insulating layer (156A).
Note: conductive material is either thermally or electrically conductive material.
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You does not teach wherein a portion of the conductive layer is a lower than a top surface of the gate dielectric layer.
Cheng teaches, Fig. 9, cols. 9-10, a portion of the conductive layer (lower portion of gate cap 60G) is a lower than a top surface of the gate dielectric layer (56).
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As taught by Cheng, one of ordinary skill in the art would utilize & modify the above teaching into You to obtain a portion of the conductive layer is a lower than a top surface of the gate dielectric layer as claimed, because it aids in achieving a desired TFET with enhanced gate protection and improved performance. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cheng in combination You due to above reason.
Re claims 11-13, You teaches, Fig. 23, an insulating capping layer (134A and/or 158) formed over the gate structure (110A, 128A), wherein the conductive via (170B) is in direct contact with a top surface and a sidewall surface of the insulating capping layer (134A and/or 158); wherein the insulating capping layer has a T-shaped structure (Fig. 18); and wherein a sidewall of the gate spacer (120A-B) is substantially aligned to a sidewall of the insulating capping layer (left side of 120A, 158 or 120A-B aligned with 134A).
Re claim 14, You teaches, Fig. 23, a gate cut structure (128B, 134B) formed adjacent to the gate structure (128A), wherein a top surface of the gate cut structure (128B, 134B) is higher than a top surface of a gate electrode layer (132A) of the gate structure (128A).
Re claim 15, You teaches, Fig. 22, the conductive via structure (formed by 168) has a step-shaped structure.
Re claim 16, You teaches, Fig. 23, a top surface of the gate spacer (124B) is higher than a top surface of the S/D contact structure (140A-B, 154A).
Re claim 17, You teaches, under BRI, Figs. 22-23, cols. 7-14, a semiconductor device structure, comprising
-a gate structure (110A, 128A) formed over a substrate (102), wherein the gate structure comprises a gate dielectric layer (110A) and a gate electrode (128A);
-an S/D structure (122) formed adjacent to the gate structure;
-a conductive layer (166) formed on and electrically connected to the gate electrode (128A);
-a gate spacer (120A-B) formed adjacent to the gate structure;
-a source/drain (S/D) contact structure (140A, B, 154A) formed on the S/D structure, wherein a top surface of the S/D contact structure is lower than a top surface of the gate spacer (120A-B); and
-a first insulating layer (158, 160 with 134A) formed over the conductive layer (166), the gate spacer (120A-B) and the gate structure (110A, 128A), wherein a top surface of the first insulating layer (158 with 134A, B) is higher than the top surface of the gate spacer (120A-B), and a portion of the first insulating layer (158, 160 with 134A) is lower than the top surface of the gate spacer (120A-B), and the first insulating layer (158, 160 with 134A) covers a portion of a top surface of the conductive layer (166).
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You does not teach wherein a portion of the conductive layer is a lower than a top surface of the gate dielectric layer.
Cheng teaches, Fig. 9, cols. 9-10, a portion of the conductive layer (lower portion of gate cap 60G) is a lower than a top surface of the gate dielectric layer (56).
As taught by Cheng, one of ordinary skill in the art would utilize & modify the above teaching into You to obtain a portion of the conductive layer is a lower than a top surface of the gate dielectric layer as claimed, because it aids in achieving a desired TFET with enhanced gate protection and improved performance. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cheng in combination You due to above reason.
Re claim 18, You teaches, Fig. 23, an interface (part between 134A & 166) between the conductive layer (166) and the first insulating layer (158, 160 with 134A) is lower than the top surface of the gate spacer (120A-B).
Re claim 20, You teaches, under BRI, Fig. 23, col. 10, 3rd par., a second insulating layer (156A, middle portion of 158) formed over the S/D contact structure (140A-B, 154A) and the first insulating layer (134A), wherein a portion of the second insulating layer (156A) is lower than the top surface of the gate spacer (120A-B).
Allowable Subject Matter
3. Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-29 are allowed. The allowable subject matter includes “a conductive layer formed over the gate electrode layer, wherein a bottom surface of the conductive layer is lower than a top surface of the first gate spacer, the conductive layer has a width along a first direction and a thickness along a second direction perpendicular to the first direction, and the width is greater than the thickness;
a first insulating layer formed over the gate electrode layer and over the conductive layer;
wherein a conductive via structure formed through the first insulating layer, wherein the conductive via structure has a portion between the first gate spacer and the second gate spacer, and a bottom of the conductive via structure is lower than a top surface of the first gate spacer, wherein an interface between the conductive via structure and the conductive layer is lower than a top surface of the gate dielectric layer” (claim 21).
Response to Arguments
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/30/26