Office Action Predictor
Last updated: April 15, 2026
Application No. 18/168,434

DIE PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Final Rejection §103
Filed
Feb 13, 2023
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Winbond Electronics CORP.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 2m
To Grant
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
537 granted / 635 resolved
+16.6% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
43 currently pending
Career history
678
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
38.6%
-1.4% vs TC avg
§102
32.3%
-7.7% vs TC avg
§112
25.7%
-14.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 635 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 12/30/2025. Claims 1-19 and 21 are pending. Claims 1-10 are withdrawn. Claim 20 is cancelled. Claim 21 is new. Claim 11 is currently amended. Claim 11 is independent. Response to Arguments Applicants’ arguments and amendments, filed 12/30/2025, with respect to 112 Rejections, as indicated in line number 2 of the office action mailed 10/3/2025, have been fully considered and are persuasive. The rejections have been withdrawn. Applicants' arguments and amendments, filed 12/30/2025, with respect to independent claim 11, although substantive and pertinent to expediting the prosecution of the current application, are considered not persuasive, respectfully, for the reasons that follow. Regarding independent claim 11, the claim has been amended to recite “a first insulating layer disposed on the supporting dielectric layer and exposing a top surface of the vertical wires, wherein a thermal expansion coefficient of the supporting dielectric layer is greater than a thermal expansion coefficient of the first insulating layer” and “a plurality of redistribution traces formed on the first insulating layer”, which applicants contend is not disclosed or taught by the prior art, including Um and Inuoe (Remarks 8-10). Applicants’ contentions are fully considered, however are not found persuasive, since as noted below in the rejection of independent claim 11 the claimed “first insulating layer” is interpreted as the protection layer described in paragraph [0079] of Um which is formed on mold layer 30 before forming the photoresist film, and thereby there would be openings in the protection layer corresponding to the openings in the photoresist film for the connection points to vertical wires VW1. It is further disclosed in paragraph [0081] of Um that the protective layer comprises polyimide. Inoue discloses a package structure comprising a supporting dielectric layer 70 (“protective layer”- ¶0034) comprised of epoxy resin with a thermal expansion coefficient of 62 x 10-6/K (¶0039), and wherein polyimide has a thermal expansion coefficient of 54 x 10-6/K (¶0039). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Um such that the supporting dielectric layer comprises epoxy resin as taught by Inoue for the purpose of utilizing a suitable and well-known material composition for a supporting dielectric layer, which is a preferrable insulating material with protective capabilities (Inoue ¶0034). It is in the combined teachings of Um and Inoue in which the limitation “wherein a thermal expansion coefficient of the supporting dielectric layer is greater than a thermal expansion coefficient of the first insulating layer” is taught, because the composition of the supporting dielectric layer 30 in Um has been modified by Inoue to be epoxy resin, which has a thermal expansion coefficient of 62 x 10-6/K (Inoue ¶0039) and the first insulating layer in Um comprises polyimide, which has a thermal expansion coefficient of 54 x 10-6/K (Inoue ¶0039). Thus, the thermal expansion coefficient of the supporting dielectric layer is greater than the thermal expansion coefficient of the first insulating layer. The claimed relationship between the respective thermal expansion coefficients of the supporting dielectric layer and first insulating layer is taught given the material compositions and the associated material properties (i.e., thermal expansion coefficients) disclosed in the combined teachings of Um and Inoue. Thus, for the aforementioned reasons the rejection is deemed proper. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US 2024/0038720 A1, hereinafter “Um”) in view of Inoue (US 2020/0313644 A1). Regarding independent claim 11, Figures 2-3 and 7 of Um disclose a die package structure, comprising: a die 210 (“semiconductor chips”- ¶0027) with a plurality of signal junctions 211 (“chip pads”- ¶0034; see Fig. 3 for multiple pads 211) on a top surface of the die 210; a plurality of vertical wires VW1 (“vertical wires”- ¶0043 including portion BB, which would be formed on each of the pads 211) formed over the signal junctions 211 of the die 210, respectively; a supporting dielectric layer 30 (“mold layer”- ¶0058, which has to be formed of an electrically insulating material to prevent short circuiting) covering the die 210 and burying the vertical wires VW1 into the supporting dielectric layer 30, and exposing a top of the vertical wires VW1; a first insulating layer (i.e., “protection layer… insulation material”- ¶0081, which can be formed on mold layer 30 before forming the photoresist film- ¶0079, and thereby there would be openings in the protection layer corresponding to the openings in the photoresist film for the connection points to vertical wires VW1) disposed on the supporting dielectric layer 30 and exposing a top surface of the vertical wires VW1, and wherein the first insulating layer comprises polyimide (¶0081); a plurality of redistribution traces 40 (“RDL pattern”, specifically the metal forming RDL pattern 40- ¶0077) formed on the first insulating layer, since the protection layer is formed before the photoresist film (¶0079) and thereby the traces 40, which are formed on the photoresist film (¶¶0076-0077) would also be formed on the protection layer, and electrically connected to the vertical wires VW1, respectively; and a plurality of bumps 50 (“external terminals”- ¶0071) formed at a bonding site of each of the redistribution traces 40, respectively. Um does not expressly disclose wherein a thermal expansion coefficient of the supporting dielectric layer is greater than a thermal expansion coefficient of the first insulating layer. Inoue discloses a package structure comprising a supporting dielectric layer 70 (“protective layer”- ¶0034) comprised of epoxy resin with a thermal expansion coefficient of 62 x 10-6/K (¶0039), and wherein polyimide has a thermal expansion coefficient of 54 x 10-6/K (¶0039). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Um such that the supporting dielectric layer comprises epoxy resin as taught by Inoue for the purpose of utilizing a suitable and well-known material composition for a supporting dielectric layer, which is a preferable insulating material with protective capabilities (Inoue ¶0034). Thus, the combined teachings of Um and Inoue discloses wherein a thermal expansion coefficient of the supporting dielectric layer (comprised of epoxy resin with a thermal expansion coefficient of 62 x 10-6/K- Inoue ¶0039) is greater than a thermal expansion coefficient of the first insulating layer (comprised of polyimide (taught by Um ¶0081) with a thermal expansion coefficient of 54 x 10-6/K- Inoue ¶0039). Regarding claim 12, Figures 2-3 and 7 of Um disclose wherein the vertical wires VW1 each has a ball-shaped portion BB (“bonding ball”- ¶0045) in direct contact with each of the signal junctions 211 and an elongated portion (i.e., vertical portion of VW1) extending vertically upward away from the die 210. Regarding claim 13, Figures 2-3 and 7 of Um disclose wherein a cross-sectional area of the ball-shaped portion BB is greater than a cross-sectional area of the elongated portion. Regarding claim 14, Figures 2-3 and 7 of Um disclose wherein a bottom area of the ball-shaped portion BB is smaller than a top area of the signal junctions 211. Regarding claim 15, Figures 2-3 and 7 of Um disclose wherein a material of the bumps 50 comprises Sn, Pb, Ni, Au, Ag, Cu, Bi, and an alloy thereof (¶0085). Regarding claim 16, Figures 2-3 and 7 of Um disclose a height of the vertical wires. Um does not expressly disclose wherein the height of the vertical wires is between 30 µm to 50 µm. However, it would have been obvious to form the height of the vertical wires within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claim 17, Figures 2-3 and 7 of Um disclose wherein a material of the supporting dielectric layer 30 comprises molding compound (¶0067). Regarding claim 18, Figures 2-3 and 7 of Um disclose wherein a material of the vertical wires VW1 comprises copper, silver, gold, or a combination thereof (¶0044). Regarding claim 19, Figures 2-3 and 7 of Um disclose wherein a top surface of the vertical wires VW1 is level with a top surface of the supporting dielectric layer 30. Allowable Subject Matter Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 21, the prior art of record including Um and/or Inoue, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] die package structure further comprising: a patterned dielectric layer disposed on the first insulating layer, wherein the redistribution traces are embedded in the patterned dielectric layer; and a second insulating layer disposed on the patterned dielectric layer and exposing the bonding sites of the redistribution traces, wherein the die comprises at least two signal junctions, at least two vertical wires, at least two redistribution traces, and at least two bumps”. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Feb 13, 2023
Application Filed
Oct 02, 2025
Non-Final Rejection — §103
Dec 30, 2025
Response Filed
Jan 15, 2026
Final Rejection — §103
Mar 31, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.3%)
2y 2m
Median Time to Grant
Moderate
PTA Risk
Based on 635 resolved cases by this examiner. Grant probability derived from career allow rate.

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