DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20190229198 A1, hereinafter Huang‘198).
Regarding independent claim 7, Huang‘198 teaches, “A metal oxide semiconductor (MOS) transistor (fig. 1-12; ¶ [0014] - ¶ [0057]), comprising:
a semiconductor body (120, fig. 7) having a first and a second side (top and bottom) opposite to one another and a first type of conductivity (N);
a trench (104) in the semiconductor body (120) at the first side (top),
the trench (104) having a first and a second side opposite to one another, the first and second sides of the trench being transverse to the first side (top) of the semiconductor body (120) and extending toward the second side (bottom) of the semiconductor body (120);
a first oxide region (114, 110) in the trench (104) on the first and second (left and right) sides of said trench (104);
a conductive gate region (108) in said trench (104) on the first oxide region (114, 110), the conductive gate region (108) being electrically isolated from the semiconductor body (120) by said first oxide region (114, 110), the conductive gate region (108) having a first surface (top) opposite a second surface, the first surface of the conductive gate (108) is substantially coplanar with the first side (top) of the semiconductor body (120);
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a second oxide region (110, 128) in the trench (104) on the conductive gate region (108), the conductive gate region (108) being between the first and second oxide regions along a first direction (see fig. 11G, 11M along with fig. 7);
a first and a second body region (118) having a second type of conductivity (P) adjacent to the respective first and second sides of the trench (104), the first and second body region (118) are closer to the first side (top) than the second side of the semiconductor body (120);
a first and a second source region (116, 202) having the first type of conductivity in the respective first and second body region (118); and
a drain electrode (122) at the second side of the semiconductor body (120);
wherein portions of the first and second oxide regions (110, 114, 128) protrude from the first side of the semiconductor body (120);
first and second spacers (part of element 128) adjacent to the portions of the first and second oxide regions (110, 114, 128) protruding from the first side of the semiconductor body (120), the first and second spacers being on the first and the second source region (116), respectively;
a first recess (accommodating element 136, 128, 132) in the semiconductor body (120) extending through said first source region (116) and said first body region (118) adjacent to said first spacer (128);
a second recess (similar to first recess, see fig. 12, two recesses on the left and right side of gate 108) in the semiconductor body (120) extending through said second source region and said second body region adjacent to said second spacer;
a first and a second enriched region (136, fig. 7 with 136) of the second type of conductivity (P+) with a different doping concentration than the first and second body regions (118), the first and second enriched region (136) in the respective first and second recess, and in electrical contact (by conductor 132) with the respective first and second body regions (118), the first and the second enriched region (136) are closer to the second side of the semiconductor body (120) than the first and the second body region (118); and
a metal contact layer (132) in the first and second recesses in electrical contact with the first and the second source region (116)”.
Regarding claim 8, Huang‘198 further teaches, “The MOS transistor of claim 7, wherein the first and second spacers (128) are of insulating material”.
Regarding claim 9, Huang‘198 further teaches, “The MOS transistor of claim 7, comprising a field plate of electrically conductive material (112) in the trench buried in said first oxide region (114, 110)”.
Regarding claim 10, Huang‘198 further teaches, “The MOS transistor of claim 8, wherein the first and second spacers (128) cover a same respective amount of surface region of the first side of the semiconductor body (120)”.
Claims 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Burke et al. (US 20130323921 A1, hereinafter Burke‘921).
Regarding independent claim 18, Burke‘921 teaches, “A device, comprising:
a substrate (11) having a first surface (18) opposite a second surface (bottom surface);
a first trench (22) in the substrate (11);
a first dielectric layer (134, 126) in the first trench (22);
a first gate portion (28) in the first dielectric layer (134) and having a third surface (top surface) that is substantially coplanar with the first surface of the substrate (18); Note: ‘substantially’ is a broad and indefinite limitation in absence of any definition in the specification.
a second dielectric layer (41) on the first gate portion (28), the second dielectric layer (41) extending past the first surface of the substrate (11), the second dielectric layer (41) having a fourth surface opposite a fifth surface, the fourth surface contacting (indirect contact) the first gate portion (28);
a combined spacer (26, 134) on the first surface of the substrate (11) and adjacent to the second dielectric layer (41), the combined spacer (26, 134) having a silicon dioxide portion (134) and a first silicon nitride portion (26), the first silicon nitride portion (26) being spaced from the second dielectric layer (41) by the silicon dioxide portion (134), portions of the fifth surface of the second dielectric layer (41) being exposed from the first silicon nitride portion (26);
a second trench (422) in the substrate (11); and
a third trench (422) in the substrate (11), the first trench (22) being between the second trench and the third trench (422 and 422)”.
Note: Prior art Tai; Sung-Shan et al. US 20130049104 A1 can also be used to reject claim 18 under 35 U.S.C. 102(a)(1).
Regarding claim 19, Burke‘921 further teaches, “The device of claim 18, wherein a second gate portion (21) in the first dielectric layer (126), the second gate portion (21) between the first gate portion (28) and the substrate (11)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Burke‘921 as applied to claim 18 as above, and further in view of YANG et al. (CN 106129114 A, hereinafter Yang‘114) of record.
Regarding claim 20, Burke‘921 teaches all the limitations described in claim 18.
But Burke‘921 is silent upon the provision of wherein the device of claim 18, comprising a third dielectric layer on the second dielectric layer, a second silicon nitride portion being between the third dielectric layer and the second dielectric layer.
However, Yang‘114 teaches a similar device (fig. 12) comprising a third dielectric layer (30b) on the second dielectric layer (27), a second silicon nitride portion (30a) being between the third dielectric layer (30b) and the second dielectric layer (27).
Burke‘921 and Yang‘114 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Burke‘921 with the features of Yang‘114 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Burke‘921 and Yang‘114 to include multiple insulating layers on top of the gate structure according to the teachings of Yang‘114 with a motivation of protecting the gate structure, the channel and the Source. See Yang‘114, page 11.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817