DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 18 recites the limitation "the body region" in lines 10-11. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, the limitation "the body region" will be replaced by "the first body region".
As claims 19-20 depend on the above rejected claim 18, they are also being rejected on the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tai et al. (US 20130049104 A1, hereinafter Tai’104).
Regarding independent claim 18, Tai’104 teaches, “A device (fig. 1-4; ¶ [0023] - ¶ [0045]), comprising:
a substrate (202, 204, 216, 231, 220a, fig. 2J) having a first surface (see annotation) opposite a second surface (see annotation);
a first trench (208) in the substrate extending in a first direction (D1) toward the second surface;
a first dielectric layer (210a) in the first trench (208);
a first gate portion (212a) in the first dielectric layer (210a);
a second dielectric layer (top portion of dielectric layer 214) on the first gate portion (212a), the second dielectric layer extending past the first surface of the substrate, the second dielectric layer having a third surface (bottom surface) opposite a fourth surface (top surface), the third surface contacting the first gate portion (212a);
a first body region (216) having a second type of conductivity (P) adjacent to the trench (208), the first body region (216) closer to the first surface than the second surface;
a first source region (220a) having the first type of conductivity (N+) in the first surface;
a combined spacer on the first source region (220a) along the first direction (D1), and adjacent to the second dielectric layer (see annotation), the combined spacer having a silicon dioxide portion (214, ¶ [0028]) and a first silicon nitride portion (224a, ¶ [0030]), the first silicon nitride portion (224a) being spaced from the second dielectric layer by the silicon dioxide portion, and the first silicon nitride portion (224a) being spaced from the first source region (220a) by the silicon dioxide portion (214);
a second trench (229a) in the substrate; and
a third trench (229a, contact openings 229a formed on both sides 208) in the substrate, the first trench (208) being between the second trench (229a) and the third trench (229a)”.
PNG
media_image1.png
717
844
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tai’104 as applied to claim 18 as above, and further in view of Burke et al. (US 20130323921 A1, hereinafter Burke’921) of record.
Regarding claim 19, Tai’104 teaches all the limitations described in claim 18.
But Tai’104 is silent upon the provision of wherein a second gate portion in the first dielectric layer, the second gate portion between the first gate portion and the substrate.
However, Burke’921 further teaches, “The device of claim 18, wherein a second gate portion (21) in the first dielectric layer (126), the second gate portion (21) between the first gate portion (28) and the substrate (11)”.
Tai’104 and Burke’921 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tai’104 with the features of Burke’921 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Tai’104 and Burke’921 to include a shield electrode (second gate portion) according to the teachings of Burke’921 with a motivation of achieving reduced switching losses, superior gate oxide reliability, lower on-resistance.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tai’104 as applied to claim 18 as above, and further in view of YANG et al. (CN 106129114 A, hereinafter Yang’114) of record.
Regarding claim 20, Tai’104 teaches all the limitations described in claim 18.
But Tai’104 is silent upon the provision of wherein the device of claim 18, comprising a third dielectric layer on the second dielectric layer, a second silicon nitride portion being between the third dielectric layer and the second dielectric layer.
However, Yang’114 teaches a similar device (fig. 12) comprising a third dielectric layer (30b) on the second dielectric layer (27), a second silicon nitride portion (30a) being between the third dielectric layer (30b) and the second dielectric layer (27).
Tai’104 and Yang’114 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tai’104 with the features of Yang’114 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Tai’104 and Yang’114 to include multiple insulating layers on top of the gate structure according to the teachings of Yang’114 with a motivation of protecting the gate structure, the channel and the Source. See Yang’114, page 11.
Allowable Subject Matter
Claims 7-10 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 7, the applicant has sufficiently claimed and defined a MOS transistor, whereby the prior arts of record and to the examiner's knowledge do not teach or render obvious, at least to the skilled artisan, the instant invention regarding the MOS transistor comprising: P+ body-contact region is closer to the bottom side of the semiconductor body than the P+ body region. The closest prior art of record, Kuruc Marian et al. (US 20140027813 A1, fig. 27) teaches, a semiconductor body (112), a trench (22), a conductive gate region (28), a first oxide region (26, 261), a second oxide region (41), a body region (310), a source region (333), a drain electrode (46), gate spacers (26), recesses (accommodating elements 36 and 43) and enriched regions (36), but fails to teach, the enriched regions (36) are closer to the bottom side of the semiconductor body (112) than the body region (310). None of the prior arts of record, either singularly or in combination, can be used to modify the device of Kuruc Marian et al. to teach the above missing feature with obvious motivation or without breaking the device of Kuruc Marian et al.
Claims 8-10 are also allowed as they depend on the allowed independent claim 7.
Response to Arguments
Applicant’s arguments with respect to the newly amended claims have been considered but are moot because the arguments do not apply to any of the references being as used in the current rejection.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Prosecution Insights