DETAILED ACTION
This action is responsive to the amendment filed November 14, 2025. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 112
The prior §112 rejections are withdrawn on view of the amended claims.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2020/0335396) in view of Sekiya (US 2020/0266103), Geffen et al. (US 6,192,289), Yoshida et al. (US 2017/0123756), Otsuka (US 2007/0087279), and Mikami et al. (US 2020/0144095).
(Re Claim 1) Yamamoto teaches (see Figs. 1-4A and supporting text) a wafer processing method for processing a wafer (11) having a front surface (11a) on which a pattern and a plurality of planned dividing lines are formed, along the planned dividing lines, the wafer processing method comprising:
a holding step of holding the front surface of the wafer by a holding table (Fig. 3A);
a processing step of detecting the planned dividing lines on the front surface from a side of the front surface through the holding table or from a side of a back surface (11b) by using an infrared camera (Fig. 3B, ¶¶6,52-55) and processing the wafer by using a processing unit from the side of the back surface along the planned dividing lines (Fig. 4A).
Yamamoto is silent regarding an inspection step of placing the wafer on an inspection table and inspecting processing quality from the back surface after the processing step, wherein a location of a defective portion of the wafer on the inspection table, as determined during the inspection step, is stored in a storing part on a basis of a characteristic location of the wafer, wherein the method further comprises: a conveying step of conveying the wafer to a picking-up apparatus in a state in which the front surface is exposed: and an excluding step of excluding the location of the defective portion of the wafer stored in the storing part as a target to be picked up by the picking-up apparatus.
A PHOSITA would recognize that it is common practice to perform inspections during all stages of device fabrication, including after dicing operations. Related art from Sekiya discloses inspecting, from a back surface, the dicing grooves to determine if there is damage or defects (Fig. 10, ¶¶70-73). Sekiya inspects each chip and determines if each chip is good and then subsequently uses this information to determine if that chip should be picked up in a subsequent picking operation, thus Sekiya implicitly requires a “storing part” for the inspection information regarding which dies are good, to be available in the next picking operation. If the information is not stored in a storing part, then determining which dies are good and need to be picked cannot occur. Sekiya lacks a table in Fig. 10, however a PHOSITA would find it obvious to place the workpiece on a table when imaging to secure, support, and stabilize the workpiece for improved imaging. Related art from Yoshida (Figs. 4-5, ¶¶38-41,68) performs an inspection on/from the backside of the wafer while the wafer is on a table 31 and stores defect location information in a storing part 38 based on coordinates that are based on the notch and then uses this information to exclude chips with defects in the subsequent picking operation (¶68). Additionally, related art from Geffen discloses when inspecting dicing grooves, the wafer can be placed on a table (Fig. 3) and when imaging the wafer, the locations on the wafer and alignment thereof can be determined on a basis of a characteristic location on the wafer, e.g. a center point and edges, and that this point can be used to determine the locations of areas of interest, e.g. dicing lines with defects (Figs. 5-7B, col 4 line 24- col 5 line 12). Thus from Geffen one can determine or triangulate any location on a wafer, e.g. a location of a bad die, based on the center point and points at edges of the wafer. Regarding the conveying step of conveying the wafer to a picking-up apparatus in a state in which the front surface is exposed. After the dicing, Yamamoto’s wafer is mounted face down on the tape frame (Fig. 4). A PHOSITA would recognize that in most circumstances it is preferable to pick dies from a tape when the dies are facing upward/away from the tape, this is because in conventional pick-and-place apparatus, ejector pins are used to push the dies (and tape) upward while a vacuum effector picks the die up off the tape, it is desirable to have the pins contact the back sides of the dies because this is less likely to cause damage than if the pins press against the active sides of the dies. This orientation also allows for easier and faster inspection of the active surfaces of the dies. Like Yamamoto, related art from Mikami teaches dicing from the backside (Figs. 4A-4B) of the wafer while the frontside is attached to a tape 3. Then a tape transfer process is performed to flip the dies onto a new tape 4 and allow for the protective/dicing/grinding tape 3 to be removed (Fig. 6A-6C). Then the dies can be safely picked from the tape 4 in a face-up orientation such that the ejector pins 17 do not press against the active side of the dies, which can cause damage. Regarding the tape transfer process of Mikami, a PHOSITA would recognize this is conventionally performed in a tape transfer apparatus rather than by manually. Otsuka discloses a tape transfer apparatus for performing tape transferring processes (Figs. 1-7). A PHOSITA would recognize when performing a tape transfer process that flips Yamamoto’s dies onto a new tape for a subsequent pick-and-place operation, this can be automated in Otsuka’s apparatus. The singulated wafer is then mounted with the dies facing upward, and will be transported from the tape transfer apparatus to a pick-and-place apparatus disclosed by Sekiya (not shown, ¶73), and/or Yoshida Fig. 17, and/or Mikami Fig. 7B, while the dies are facing upward and exposed.
In view of the prior art, a PHOSITA would find it obvious to inspect the backside of the wafer for defects after dicing according to Yoshida and Sekiya, and to store the defect location information based on a characteristic location of the wafer such as a notch (Yoshida) or other points (center and edges in Geffen), such that the locations of bad dies are stored which is later used to determine which dies to pick. In addition, following Yamamoto’s dicing with the wafer face down on the tape, a PHOSITA would also find it obvious to flip the singulated wafer onto a new tape as taught by Mikami, using an apparatus as taught by Otsuka, then after the transfer/die flip the dies can be safely and easily picked from the tape without damaging the active sides of the dies.
(Re Claim 2) wherein the characteristic location is a notch in the wafer (Yoshida teaches a correlation to the notch which is the origin for the coordinate system, ¶39)
(Re Claim 3) further comprising: an inspection mark forming step of forming an inspection mark on the back surface by using the processing unit on a basis of an alignment mark formed on the front surface, wherein the characteristic location is the inspection mark (one or more cut grooves, or intersections thereof, formed on the backside may be used/construed as inspection mark(s), and are aligned with the dicing regions on the front based on a front side alignment mark, ¶54-55)
(Re Claim 4) wherein any of a dividing groove that divides the wafer, a processed groove that does not divide the wafer, or a modified layer formed inside the wafer is formed in the processing step and the inspection mark forming step (see discussion above, grooves are formed in Fig. 4A, the processing includes forming groove inspection marks).
(Re Claim 7) wherein the characteristic location is an orientation flat on the wafer (Yoshida teaches the location may be a notch or flat, ¶¶39,59).
(Re Claim 8) wherein the characteristic location is a center point of the wafer (Geffen uses the center point of the wafer to locate/triangulate locations of interest, e.g. bad dies, see col 4 line 25-col 5 line 12, Figs. 6-7B).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2020/0335396) in view of Sekiya (US 2020/0266103), Geffen et al. (US 6,192,289), Yoshida et al. (US 2017/0123756), Otsuka (US 2007/0087279), and Mikami et al. (US 2020/0144095), as applied above, and further in view of Arita et al. (US 2010/0022071) and Rohleder et al. (2017/0092540).
(Re Claim 5) Yamamoto is silent regarding wherein the processing step includes a protective film forming step of forming a protective film on the back surface of the wafer, an exposure step of removing the protective film formed along the planned dividing lines, by using the processing unit, to expose the planned dividing lines after the protective film forming step, and an etching step of executing plasma etching from the back surface to process the wafer along the planned dividing lines after the exposure step, and the inspection mark forming step removes the protective film at a freely-selected position in a manner corresponding to a shape of the inspection mark, by using the processing unit, and forms the inspection mark on the back surface of the wafer in the etching step.
(Re Claim 6) Yamamoto is silent regarding a protective member forming step of forming a first protective member on the front surface before the processing step; and a transfer step of forming a second protective member on the back surface and peeling off the first protective member from the front surface after the inspection step.
Yamamoto uses a mechanical saw blade to perform the dicing. Related dicing art from Rohleder recognizes mechanical blade dicing can cause damage (¶16) while plasma dicing is an improved process causing less damage (¶20). Thus a PHOSITA would find it obvious to substitute a plasma dicing process for the mechanical blade dicing process, and furthermore look to related plasma dicing art to teach additional steps, masks, etc. required when altering the process to include plasma dicing. Related plasma dicing art from Arita teaches plasma dicing a wafer from a back side wherein similarly the dicing pattern on the front is detected from the backside using an IR camera (¶¶23-24), thus would flow naturally from Yamamoto’s existing process. Arita forms a protective film 9 on the back surface (Fig. 5b), an exposure step is performed to remove the protective film along the dicing lines (Fig. 5c), and a plasma etch is performed (Figs. 5d and then 9a) to form dicing grooves. A PHOSITA would find it obvious to perform the plasma dicing according to Arita as this is known to yield the desired results while offering the benefits over a mechanical saw and would flow naturally from Yamamoto’s existing backside dicing process flow. Regarding the inspection mark forming step, as noted above, the marks can be ascribed to one or more grooves or groove intersections, etc., formed in the process, thus the inspection mark forming occurs as the grooves are formed such that the steps in Figs. 5c-d and 9a also form the marks. Also, (Re Claim 6) when performing the plasma dicing, Arita first attaches a protective member 6 to the front surface (Fig. 5a), before the processing steps in Figs. 5c-9, and performs a transfer step of forming a second protective member (Fig. 9b: 30) on the back surface, and peeling off the first protective member (Fig. 9c) from the front surface after the inspection step (e.g. note inspection performed in Fig. 8). Thus when modifying Yamamoto to use plasma dicing instead of blade dicing, Arita’s additional layers used for handling, transferring, and masking would be obvious to incorporate.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related dicing, tape transfer, inspection, pick-and-place process, and techniques for position/location determination.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898