DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Prior rejections of Claim 12 under both 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph and 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of applicant’s amendment to claim 12.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 7-8 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 2022/0254776 A1, newly cited).
Re Claim 7, Cheng teaches a method for manufacturing a semiconductor structure (Fig. 35), comprising:
forming an elongated fin (fin 214, Fig. 35, para [0048]) on a semiconductor substrate (substrate 202, Fig. 35, para [0014]), the elongated fin having a first fin portion (fin portion 202A, Fig. 35) and a second fin portion (fin portion 202B, Fig. 35) displaced from each other in a first direction (y-axis, Fig. 35);
forming a first device (marked “1st device” in annotated Fig. 35 below) on the first fin portion (fin portion 202A), the first device including
two first source/drain portions (1st S/D 238 within 202A, Fig. 35, para [0032]) which are spaced apart from each other in the first direction (y-axis, see Fig. 35),
a first channel portion (channels 2080 within 202A, Fig. 35, para [0035], also see Fig. 32, where 2080 is marked) including at least one first effective channel layer (two effective channels within 202A, see Fig. 35) which extends between the first source/drain portions (1st S/D 238 within 202A, Fig. 35),
two first shielding elements (elements 236 within 202A, Fig. 35, para [0031]) respectively adjacent the first source/drain portions (1st S/D 238 within 202A, Fig. 35) such that an upper surface of one of the first shielding elements (upper surface of elements 236 within 202A) is at a first level (marked “1st level” in annotated Fig. 35 below) not higher than a lower surface of a bottommost one of the at least one first effective channel layer (lower surface of the bottommost channel 2080 within 202A, see Fig. 35), and
a first gate structure (1st gate structure 254+256 in region 202A, Fig. 35, also see Fig. 32 where 254+256 are marked, para [0036]) disposed around the at least one first effective channel layer (channels 2080 within 202A, see Fig. 35) such that two surfaces of the at least one first effective channel layer (top and bottom surfaces of the channels), which are opposite to each other in a second direction (z-axis, Fig. 35) transverse to the first direction (y-axis, Fig. 35), are adjacent to the first gate structure (1st gate structure 254+256 in region 202A, Fig. 35); and
forming a second device (marked “2nd device” in annotated Fig. 35 below) on the second fin portion (fin portion 202B), the second device including
two second source/drain portions (2nd S/D 240 within 202B, Fig. 35, para [0032]) which are spaced apart from each other in the first direction (y-axis, Fig. 35),
a second channel portion (channels 2080 within 202B, Fig. 35, para [0035], also see Fig. 32, where 2080 is marked) including a plurality of second effective channel layers (three effective channels within 202B, see Fig. 35) each of which extends between the two second source/drain portions (2nd S/D 240 within 202B, Fig. 35), the second effective channel layers being separated from each other in the second direction (z-axis, Fig. 35),
two second shielding elements (elements 236 within 202B, Fig. 35, para [0031]) respectively adjacent the second source/drain portions (2nd S/D 240 within 202B) such that an upper surface of one of the second shielding elements is at a second level (marked “2nd level” in annotated Fig. 35 below) not higher than a lower surface of a bottommost one of the plurality of second effective channel layers (lower surface of the bottommost channel 2080 within 202B, see Fig. 35), the second level being different than the first level (“2nd level” is lower than “1st level”, see annotated Fig. 35 below), and
a second gate structure (2nd gate structure 254+256 in region 202B, Fig. 35, also see Fig. 32 where 254+256 are marked, para [0036]) disposed around the second effective channel layers (channels 2080 within 202B, see Fig. 35) such that two surfaces of each of the second effective channel layers (top and bottom surfaces of the channels), which are opposite to each other in the second direction (z-axis, Fig. 35), are adjacent to the second gate structure (see Fig. 35), a number of the second effective channel layers being greater than a number of the at least one first effective channel layer (there are three effective channels in 202B while there are two effective channels in 202A).
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Re Claim 8, Cheng teaches the method as claimed in claim 7, comprising forming two insulating portions (isolation features 2160, Fig. 32) at two opposite sides of the elongated fin (opposite side of fins, Fig. 32) in a third direction (x-axis, Fig. 32) transverse to the first (y-axis, Figs. 32 and 35) and second directions (z-axis, Figs. 32 and 35) such that each of the first fin portion and the second fin portion is disposed between the two insulating portions (isolation features 2160, see Fig. 32), each of the insulating portions being elongated in the first direction (y-axis, compare Figs. 32 and 35).
Re Claim 12, Cheng teaches the method as claimed in claim 7, wherein the second level (“2nd level”) is more proximal (see annotated Fig. 35 above) to the semiconductor substrate (202) than the first level (“1st level”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2022/0254776 A1, newly cited) as applied to claim 8 above, and further in view of Park et al. (US 2022/0320312 A1, of record).
Re Claim 9, Cheng teaches the method as claimed in claim 8, but does not disclose a gate isolation portion between the two device regions.
However, related art Park discloses an isolation structure (178, Fig. 1B, para [0038]) between one of the first source/drain portions (150W) which is proximate to the second device (device in 105N region, Fig. 1B) and one of the second source/drain portions (150N) which is proximate to the first device (device in 105W region, Fig. 1B), the gate isolation portion being elongated in the third direction (y-axis, Fig. 1A).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the method of forming the device of Cheng, by including the isolation structure between the two device regions of Cheng, as taught by Park. The isolation structure will completely isolate the two transistor devices which will prevent any electrical cross-talk between the two devices and hence run the overall semiconductor device more efficiently.
Re Claim 10, Cheng modified by Park teaches the method as claimed in claim 9, wherein the gate isolation portion (178, Fig. 1B, Park) has a bottom surface at a level lower than that of each of the first and second source/drain portions (150N/150W, see Fig. 1B, Park) and higher than that of each of the insulating portions (110, compare Figs. 1B and 1C, Park), such that the first fin portion (105N) and the second fin portion (105W) are connected with each other (see Fig. 1B, Park).
Allowable Subject Matter
Claims 1-6 and 21-28 are allowed.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowable for at least the following reasons. Most of the limitations of claim 1 are taught by Park et al. (US 2022/0320312 A1, of record) as stated in the office action dated 12/16/2025. Park also teaches some of the newly added limitation wherein, “forming a plurality of stack units comprising forming a first stack (stack of 140 and 118, Fig. 10B, para [0093]) on the first fin portion (105N); forming a first source recess in the first stack and a first drain recess in the first stack (recesses “RS” in 105N region, Fig. 12), such that first channel layers of the first stack (channels 140N, Fig. 12) are formed in a first direction (x-axis, Fig. 12) between the first source recess and the first drain recess (see Fig. 12)”. However, Park does not disclose any shielding elements and hence, fails to teach the newly added limitation wherein, “forming a first shielding element in the first source recess and a second shielding element in the first drain recess, such that an upper surface of the first shielding element is at an elevation below a lower surface of an uppermost one of the first channel layers and an upper surface of the second shielding element is at an elevation below the lower surface of the uppermost one of the first channel layers; forming first source/drain portions respectively in the first source recess and the first drain recess to cover the first shielding element and the second shielding element, such that the uppermost one of the first channel layers, which is disposed between the first source/drain portions, serves as the at least one first effective channel layer”. Related art, Cheng et al. (US 2022/0254776 A1, newly cited) discloses the above limitations where the undoped epitaxial layer 236 (see Fig. 35) acts as a shielding element (see rejection of claim 7 above). However, in the Examiner’s opinion, it would not have been obvious to one of ordinary skill to combine the above teachings to reach the limitation wherein, “forming a first shielding element in the first source recess and a second shielding element in the first drain recess, such that an upper surface of the first shielding element is at an elevation below a lower surface of an uppermost one of the first channel layers and an upper surface of the second shielding element is at an elevation below the lower surface of the uppermost one of the first channel layers”, as was also stated in the office action dated 12/16/2025. Claims 2-6 depend from claim 1 and are allowable for at least the reasons above.
Claims 21-28 are allowed for the reasons explained in the office action dated 12/16/2025.
Claim 11 is allowable for at least the reasons of, “wherein the first fin portion and the second fin portion respectively have a first fin width and a second fin width in a third direction transverse to the first direction and the second direction, at least one first effective channel layer having a first channel width in the third direction, each of the second effective channel layers having a second channel width in the third direction which is the same as the second fin width, the second channel width being greater than the first channel width”. This limitation is not taught by Cheng et al. (US 2022/0254776 A1, newly cited), which teaches the independent claim 7. However, the limitation is taught by prior art, Park et al. (US 2022/0320312 A1, of record), see the rejection of claim 1 in the office action dated 12/16/2025. However, in the Examiner’s opinion, it would not have been obvious to one of ordinary skill to combine the teachings of Cheng and Park to reach the above limitation, when viewed in the context of the independent claim 7, as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim 7 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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