Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-6, 9-18, and 42-45 are pending.
-Claims 7, 8, and 19-41 are cancelled.
-Claims 1-4 and 11 are amended.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn.
Response to Arguments
Applicant’s amendments and arguments filed January 2, 2026 have been fully considered, but are not found persuasive.
Firstly, the limitations “the first cross-sectional profile comprising a first angle relative to the interface” and “the second cross-sectional profile comprising a second angle relative to the interface” do not limit where said angles must be. The phrase ‘relative to the interface’ does not mean an angle must be measured directly at the interface, nor is it specified in the limitations that an angle is an interior angle of the via. Assuming arguendo in regards to the interior angle of the top profile which the applicant identified, Lee (U.S. 2022/0216131) still teaches the limitation in two interpretations. As seen in the zoomed-in and annotated Fig. 1 of Lee below, Fig. E, a first angle relative to the interface (A) is less than a second angle (B), which is necessarily true if the interior angle is greater. Similarly, a third angle relative to the top sidewall portion (A’) is less than a fourth angle (interior angle at the interface of bottom cross-sectional profile).
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Secondly, Applicant states in the reply that “none of the other cited references overcome at least this deficiency of Lee”. Examiner finds that even if the claims are amended such that the limitations specified that an angle must be taken at the interface against the inner side of a via, Then (U.S. Pub. 2024/0213118) still teaches the limitation, as can clearly be seen in Then Fig. 1A.
For the sake of compact prosecution, Examiner will incorporate the teachings of Then into the device of Lee within the independent claim as to cover all intended aspects of an angle at the interface.
The rejection has been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-10, 11-18, and 42-45 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2022/0216131), hereinafter Lee, in view of Romanczyk et al. ("N-Polar GaN-on-Sapphire Deep Recess HEMTs With High W-Band Power Density" in IEEE Electron Device Letters, vol. 41, no. 11, pp. 1633-1636, Nov. 2020), hereinafter Romanczyk, and in view of Then et al. (U.S. Pub. 2024/0213118), hereinafter Then.
For consistency in dependency, Claims 1-5, 9-10, and 42-43 will be examined first, followed by Claims 11-18 and 44-45. A zoomed-in and annotated Fig. 1 of Lee, Fig. E, as provided above, is referenced.
Regarding Claim 1, Lee teaches a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), comprising:
-a substrate ((100); Fig. 1, Paragraph [0017]);
-a Group III-nitride semiconductor structure (consisting of the device layer (110) and interconnect (120); Fig. 1, Paragraphs [0018] and [0021]) on the substrate (100); and
-a via (as defined as both an electrode structure (e.g. 125S, 125D, and 125G), excluding the top pads, and a bottom portion (e.g. 130, 140, and 150) hereinafter referred to in total as a (via); Fig. 1, Paragraphs [0024] and [0025]) passing through the substrate (100) and the Group III-nitride semiconductor structure ((110) and (120)), wherein
-a cross-sectional profile of the via changes (e.g. changes slope, consequently width) at an interface between the substrate (100) and the Group III-nitride semiconductor structure ((110) and (120)) with a first cross-sectional profile in the N-polar Group III-nitride semiconductor structure (the upper portion of (via), as defined by the electrode structure excluding the top pads; Fig. 1) and a second cross-sectional profile in the substrate (a bottom portion of (via); Fig. 1).
Lee further teaches:
-the Group III-nitride semiconductor device may be a GaN HEMT (Paragraph [0003])
Lee does not explicitly state:
-the Group III-nitride semiconductor device is N-polar
Romanczyk teaches:
-an N-polar GaN HEMT (Fig. 1; I. Introduction, II. Epitaxial-Growth and Device Details)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the device structure of Romanczyk into the device of Lee such that the Group III-nitride semiconductor structure was N-polar. This would be due to the fact that doing so would have provided the predictable result of incorporating a high-performance device technology (Romanczyk, I. Introduction) into the GaN-based device layer of Lee.
Neither Lee nor Romanczyk teach (as explained in the ‘Response to Arguments’):
the first cross-sectional profile comprising a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprising a second angle relative to the interface, the first angle being less than the second angle.
Then teaches a transistor device featuring vias ((120); Fig. 1A, Paragraph [0039]) which pass through a substrate ((102); Fig. 1A, Paragraph [0038]) and a Group III-nitride semiconductor structure (consisting of (104), (106), and (108); Fig. 1A, Paragraph [0038]), wherein the via (120) has a first cross-sectional width (hereinafter referred to as (W1) at the second side of the Group III-nitride semiconductor structure (top of (108)) and a second cross-sectional width (hereinafter referred to as (W2)) at the interface (bottom of (104) / top of (102)), wherein:
-between a first cross-sectional profile ((120B); Fig. 1A, Paragraph [0039]) in the N-polar Group III-nitride semiconductor structure ((104), (106), and (108)), the first cross-sectional profile comprising a first angle relative to the interface (e.g. 90 degrees, as portion is vertical, Paragraph [0039]), and a second cross-sectional profile ((120A); Fig. 1A, Paragraph [0039]) in the substrate (102), the second cross-sectional profile comprising a second angle relative (necessarily greater than 90 degrees, due to tapered profile, Paragraph [0039]) to the interface, the first angle being less than the second angle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Then into the device of Lee and Romancztk such that between a first cross- sectional profile in the N-polar Group III-nitride semiconductor structure, the first cross-sectional profile comprises a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprises a second angle relative to the interface, the first angle being less than the second angle. This would be due to the fact that it would achieve the predictable result of lowering power dissipation (Then, Paragraph [0034])
Regarding Claim 2, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the via (Lee, (via)) has the first cross-sectional profile in the N-polar Group III-nitride semiconductor structure ((110) and (120)) that is substantially constant (Lee, Fig. 1; e.g. between elements (123)). (The Examiner notes that while ‘substantially’ is not defined by the Applicant, one of ordinary skill in the art would understand the limitation to mean as constant as allowable by manufacturing tolerances)
Regarding Claim 3, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the via (Lee, (via)) has the first cross-sectional profile in the N-polar Group III-nitride semiconductor structure ((110) and (120)) that narrows as it approaches the interface (Lee, Fig. 1; e.g. within layer (110)).
Regarding Claim 4, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 3, wherein:
-the via (Lee, (via)) has the second cross-sectional profile in substrate (Lee, (100)) that narrows as it approaches the interface (Lee, Fig. 1).
Regarding Claim 5, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the cross-sectional profile of the via (Lee, (via)) comprises an hourglass-shaped cross-sectional profile, and wherein a narrow convergence of the hourglass-shaped cross-sectional profile is at the interface (Lee, Fig. 1; See at surface (100a)).
Regarding Claim 9, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the substrate (Lee, (100)) comprises a silicon carbide substrate (Lee, Paragraph [0017]).
Regarding Claim 10, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the semiconductor device is a high electron mobility transistor (HEMT) device. (Romanczyk, Fig. 1; I. Introduction, II. Epitaxial-Growth and Device Details)
Regarding Claim 42, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, further comprising:
-an electrode (Lee, electrode pad (e.g. 120S, 120D, 120G); Fig. 1, Paragraph [0024])) coupled to the N-polar Group III-nitride semiconductor structure ((110) and (120)).
Regarding Claim 43, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 42, wherein:
-the via (Lee, (via)) has a conductive portion (Lee, metal plugs (123); Fig. 1, Paragraph [0024]) that is electrically coupled to the electrode (e.g. 120D).
Regarding Claim 11, Lee teaches a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), comprising:
-a substrate ((100); Fig. 1, Paragraph [0017]) having a first side ((100b); Fig. 1) and an opposing second side ((100a); Fig. 1);
-a Group III-nitride semiconductor structure (consisting of the device layer (110) and interconnect (120); Fig. 1, Paragraphs [0018] and [0021]) having a first side (bottom of (110)) and an opposing second side (top of (120)), the first side of the N-polar Group III-nitride semiconductor structure (bottom of (110)) being on the second side of the substrate (100a) to define an interface; and
-a via (as defined as both an electrode structure (e.g. 125S, 125D, and 125G), excluding the top pads, and a bottom portion (e.g. 130, 140, and 150) hereinafter referred to in total as a (via); Fig. 1, Paragraphs [0024] and [0025]) passing through the substrate (100) and the Group III-nitride semiconductor structure ((110) and (120)), the via comprising a first cross-sectional profile in the N-polar Group III-nitride semiconductor structure (the upper portion of (via), as defined by the electrode structure excluding the top pads; Fig. 1) and a second cross-sectional profile in the substrate (a bottom portion of (via); Fig. 1), wherein
-the via (via) has a first cross-sectional width (hereinafter referred to as (W1)) of at the second side of the Group III-nitride semiconductor structure (top of (120)) and a second cross-sectional width (hereinafter referred to as (W2)) at the interface (at bottom of (110) / at (100a)), and wherein
- the first cross-sectional width (W1) is greater than or equal to the second cross-sectional width (W2). (See Fig. 1, this case it is greater than)
Lee does not explicitly state:
-the Group III-nitride semiconductor device (here a HEMT) is N-polar
Romanczyk teaches:
-an N-polar GaN HEMT (Fig. 1; I. Introduction, II. Epitaxial-Growth and Device Details)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the device structure of Romanczyk into the device of Lee such that the Group III-nitride semiconductor structure was N-polar. This would be due to the fact that doing so would have provided the predictable result of incorporating a high-performance device technology (Romanczyk, I. Introduction) into the GaN-based device layer of Lee.
Neither Lee nor Romanczyk teach (as explained in the ‘Response to Arguments’):
the first cross-sectional profile comprising a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprising a second angle relative to the interface, the first angle being less than the second angle.
Then teaches a transistor device featuring vias ((120); Fig. 1A, Paragraph [0039]) which pass through a substrate ((102); Fig. 1A, Paragraph [0038]) and a Group III-nitride semiconductor structure (consisting of (104), (106), and (108); Fig. 1A, Paragraph [0038]), wherein the via (120) has a first cross-sectional width (hereinafter referred to as (W1) at the second side of the Group III-nitride semiconductor structure (top of (108)) and a second cross-sectional width (hereinafter referred to as (W2)) at the interface (bottom of (104) / top of (102)), wherein:
-the via (120) comprising a first cross-sectional profile ((120B); Fig. 1A, Paragraph [0039]) in the N-polar Group III-nitride semiconductor structure ((104), (106), and (108)), the first cross-sectional profile comprising a first angle relative to the interface (e.g. 90 degrees, as portion is vertical, Paragraph [0039]), and a second cross-sectional profile ((120A); Fig. 1A, Paragraph [0039]) in the substrate (102), the second cross-sectional profile comprising a second angle relative (necessarily greater than 90 degrees, due to tapered profile, Paragraph [0039]) to the interface, the first angle being less than the second angle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Then into the device of Lee and Romancztk such that the via comprises a first cross-sectional profile in the N-polar Group III-nitride semiconductor structure, the first cross-sectional profile comprises a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprising a second angle relative to the interface, the first angle being less than the second angle. This would be due to the fact that it would achieve the predictable result of lowering power dissipation (Then, Paragraph [0034])
Regarding Claim 12, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, wherein:
-wherein the first cross-sectional width (Lee, (W1)) is greater than the second cross-sectional width (Lee, (W2)).
Regarding Claim 13, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, upon which depends, but does not explicitly disclose:
-the first cross-sectional width (W1) is substantially the same as the second cross-sectional width (W2). (as part of ‘essentially vertical portion’ (120B)) (The Examiner notes that while ‘substantially’ is not defined by the Applicant, one of ordinary skill in the art would understand the limitation to mean as constant as allowable by manufacturing tolerances)
Regarding Claim 14, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, wherein:
- the via (Lee, (via)) has a third cross-sectional width (Lee, hereinafter referred to as (W3)) at the first side of the substrate (Lee, (100b)), and wherein the third cross-sectional width (Lee, (W3)) is greater than or equal to the second cross-sectional width (Lee, (W2)). (Lee, see Fig. 1, this case it is greater than)
Regarding Claim 15, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, wherein:
the N-polar Group III-nitride semiconductor structure comprises (Consequently due to bringing the device structure of Romanczyk into the device layer of Lee):
a barrier layer (Romanczyk, (AlGaN Backbarrier); Fig. 1, I. Introduction)), wherein the barrier layer comprises N-polar AlwGa1-wN, where 0.1<w<0.4 (in this case w = 0.38); and
-a channel layer (Romanczyk, (GaN Channel); Fig. 1, I. Introduction)), on the barrier layer (Romanczyk, (AlGaN Backbarrier)), wherein the channel layer comprises N-polar AlxGa1-xN, where 0≤x≤0.1 (in this case, x = 0).
Regarding Claim 16, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 15, wherein:
the N-polar Group III-nitride semiconductor structure comprises (Consequently due to bringing the device structure of Romanczyk into the device layer of Lee):
a buffer layer (Romanczyk, (GaN Buffer); Fig. 1, I. Introduction)), wherein the barrier layer (Romanczyk, (AlGaN Backbarrier)) is on the buffer layer (Romanczyk, (GaN Buffer)), such that the barrier layer is between the buffer layer and the channel layer (Romanczyk, (GaN Channel)),.
Regarding Claim 17, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 16, wherein:
- the buffer layer (Romanczyk, (GaN Buffer)) comprises N-polar AlvGa1-vN, where 0≤v≤0.1 (in this case v = 0).
Regarding Claim 18, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 15, further comprising:
-one or more cap layers on the channel layer (Romanczyk, (Al0.27Ga0.73N Cap); Fig. 1, I. Introduction)).
Regarding Claim 44, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, further comprising:
-a gate contact (Lee, electrode pad (120G); Fig. 1, Paragraph [0024])), a source contact (Lee, electrode pad (e.g. 120S); Fig. 1, Paragraph [0024])), and a drain contact (Lee, electrode pad (120D); Fig. 1, Paragraph [0024])) on the N-polar Group III-nitride semiconductor structure ((110) and (120)).
Regarding Claim 45, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 44, wherein:
-the gate contact (Lee, (120G)) is between the source contact (Lee, (120S)) and the drain contact (Lee, (120D)). (See Lee, right side of Fig. 3, top to bottom)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Romanczyk, and Then in view of Wu et al. (U.S. Pub. 2016/0020313), hereinafter Wu.
Regarding Claim 6, Lee, Romanczyk, and Then teach a semiconductor device (‘semiconductor device structure’ of assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, upon which it depends, but does not explicitly disclose:
-the N-polar Group III-nitride semiconductor structure comprises an N-face at a surface opposite the substrate.
Wu teaches a semiconductor device, wherein:
the N-polar Group III-nitride semiconductor structure (device (1100) including a series of III-N layers, Fig. 11G, Paragraph [0106]) comprises an N-face at a surface opposite the substrate ((1102); Fig. 11G, Paragraph [0106]) (Paragraph [0106])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Wu into the device of Lee and Romanczyk such that the N-polar Group III-nitride semiconductor structure comprises an N-face at a surface opposite the substrate. This would be due to the fact that it would achieve the predictable result of having a [0 0 0 -1] orientation on the substrate.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/D.M./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812