Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 14, 2026 has been entered.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-6, 9-18, and 42-45 are pending.
-Claims 1 and 11 are Amended.
Response to Arguments
Applicant's arguments filed May 14, 2026 have been fully considered but they are not persuasive. As was noted in the Advisory Action dated May 29, 2026, the amended limitation “a metal etch stop in the via which terminates at the interface between the substrate and the N-polar Group III-nitride semiconductor structure” is taught by the previously cited Lee et al. (U.S. Pub. 2022/0216131), particularly by the elements (150)/(140)/(130). Examiner notes that the metal layers (150)/(140)/(130) are separate than the vias they are deposited in (the actual holes within the element (100)). For clarity in that regard, Examiner will reference “shapes” in the claim rejections below.
The rejection has been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-10, 11-18, and 42-45 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2022/0216131), hereinafter Lee, in view of Romanczyk et al. ("N-Polar GaN-on-Sapphire Deep Recess HEMTs With High W-Band Power Density" in IEEE Electron Device Letters, vol. 41, no. 11, pp. 1633-1636, Nov. 2020), hereinafter Romanczyk, and in view of Then et al. (U.S. Pub. 2024/0213118), hereinafter Then.
For consistency in dependency, Claims 1-5, 9-10, and 42-43 will be examined first, followed by Claims 11-18 and 44-45. A zoomed-in and annotated Fig. 1 of Lee, Fig. E, as provided above, is referenced.
Regarding Claim 1, Lee teaches a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), comprising:
-a substrate ((100); Fig. 1, Paragraph [0017]);
-a Group III-nitride semiconductor structure (consisting of the device layer (110) and interconnect (120); Fig. 1, Paragraphs [0018] and [0021]) on the substrate (100); and
-a via (as defined as the shape of both an electrode structure (e.g. shape of 125S, 125D, and 125G within 110 and 120), excluding the top pads, and of the shape of a bottom portion (e.g. shape of 130, 140, and 150 within 100) hereinafter referred to in total as a (via); Fig. 1, Paragraphs [0024] and [0025]) passing through the substrate (100) and the Group III-nitride semiconductor structure ((110) and (120)), wherein
-a cross-sectional profile of the via changes (e.g. changes slope, consequently width) at an interface between the substrate (100) and the Group III-nitride semiconductor structure ((110) and (120)) with a first cross-sectional profile in the N-polar Group III-nitride semiconductor structure (the upper portion of (via), as defined by the shape of the electrode structure excluding the top pads; Fig. 1) and a second cross-sectional profile in the substrate (the bottom portion of (via); Fig. 1).
-a metal etch stop (e.g. (140); Fig. 1, Paragraph [0026]) in the via (via) which terminates at the interface between the substrate (100) and the N-polar Group III-nitride semiconductor structure ((110) and (120)).
Lee further teaches:
-the Group III-nitride semiconductor device may be a GaN HEMT (Paragraph [0003])
Lee does not explicitly state:
-the Group III-nitride semiconductor device is N-polar
Romanczyk teaches:
-an N-polar GaN HEMT (Fig. 1; I. Introduction, II. Epitaxial-Growth and Device Details)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the device structure of Romanczyk into the device of Lee such that the Group III-nitride semiconductor structure was N-polar. This would be due to the fact that doing so would have provided the predictable result of incorporating a high-performance device technology (Romanczyk, I. Introduction) into the GaN-based device layer of Lee.
Neither Lee nor Romanczyk teach (as explained in the ‘Response to Arguments’ of the Final dated March 16, 2026):
the first cross-sectional profile comprising a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprising a second angle relative to the interface, the first angle being less than the second angle.
Then teaches a transistor device featuring vias ((120); Fig. 1A, Paragraph [0039]) which pass through a substrate ((102); Fig. 1A, Paragraph [0038]) and a Group III-nitride semiconductor structure (consisting of (104), (106), and (108); Fig. 1A, Paragraph [0038]), wherein the via (120) has a first cross-sectional width (hereinafter referred to as (W1) at the second side of the Group III-nitride semiconductor structure (top of (108)) and a second cross-sectional width (hereinafter referred to as (W2)) at the interface (bottom of (104) / top of (102)), wherein:
-between a first cross-sectional profile ((120B); Fig. 1A, Paragraph [0039]) in the N-polar Group III-nitride semiconductor structure ((104), (106), and (108)), the first cross-sectional profile comprising a first angle relative to the interface (e.g. 90 degrees, as portion is vertical, Paragraph [0039]), and a second cross-sectional profile ((120A); Fig. 1A, Paragraph [0039]) in the substrate (102), the second cross-sectional profile comprising a second angle relative (necessarily greater than 90 degrees, due to tapered profile, Paragraph [0039]) to the interface, the first angle being less than the second angle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Then into the device of Lee and Romancztk such that between a first cross- sectional profile in the N-polar Group III-nitride semiconductor structure, the first cross-sectional profile comprises a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprises a second angle relative to the interface, the first angle being less than the second angle. This would be due to the fact that it would achieve the predictable result of lowering power dissipation (Then, Paragraph [0034])
Regarding Claim 2, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the via (Lee, (via)) has the first cross-sectional profile in the N-polar Group III-nitride semiconductor structure ((110) and (120)) that is substantially constant (Lee, Fig. 1; e.g. between elements (123)). (The Examiner notes that while ‘substantially’ is not defined by the Applicant, one of ordinary skill in the art would understand the limitation to mean as constant as allowable by manufacturing tolerances)
Regarding Claim 3, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the via (Lee, (via)) has the first cross-sectional profile in the N-polar Group III-nitride semiconductor structure ((110) and (120)) that narrows as it approaches the interface (Lee, Fig. 1; e.g. within layer (110)).
Regarding Claim 4, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 3, wherein:
-the via (Lee, (via)) has the second cross-sectional profile in substrate (Lee, (100)) that narrows as it approaches the interface (Lee, Fig. 1).
Regarding Claim 5, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the cross-sectional profile of the via (Lee, (via)) comprises an hourglass-shaped cross-sectional profile, and wherein a narrow convergence of the hourglass-shaped cross-sectional profile is at the interface (Lee, Fig. 1; See at surface (100a)).
Regarding Claim 9, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the substrate (Lee, (100)) comprises a silicon carbide substrate (Lee, Paragraph [0017]).
Regarding Claim 10, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the semiconductor device is a high electron mobility transistor (HEMT) device. (Romanczyk, Fig. 1; I. Introduction, II. Epitaxial-Growth and Device Details)
Regarding Claim 42, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, further comprising:
-an electrode (Lee, electrode pad (e.g. 120S, 120D, 120G); Fig. 1, Paragraph [0024])) coupled to the N-polar Group III-nitride semiconductor structure ((110) and (120)).
Regarding Claim 43, Lee, Romanczyk, and Then teach a semiconductor device (assembly (10); Fig. 1, Paragraph [0017]), of Claim 42, wherein:
-the via (Lee, (via)) has a conductive portion (Lee, metal plugs (123); Fig. 1, Paragraph [0024]) that is electrically coupled to the electrode (e.g. 120D).
Regarding Claim 11, Lee teaches a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), comprising:
-a substrate ((100); Fig. 1, Paragraph [0017]) having a first side ((100b); Fig. 1) and an opposing second side ((100a); Fig. 1);
-a Group III-nitride semiconductor structure (consisting of the device layer (110) and interconnect (120); Fig. 1, Paragraphs [0018] and [0021]) having a first side (bottom of (110)) and an opposing second side (top of (120)), the first side of the N-polar Group III-nitride semiconductor structure (bottom of (110)) being on the second side of the substrate (100a) to define an interface; and
-a via (as defined as the shape of both an electrode structure (e.g. shape of 125S, 125D, and 125G within 110 and 120), excluding the top pads, and of the shape of a bottom portion (e.g. shape of 130, 140, and 150 within 100) hereinafter referred to in total as a (via); Fig. 1, Paragraphs [0024] and [0025]) passing through the substrate (100) and the Group III-nitride semiconductor structure ((110) and (120)), the via comprising a first cross-sectional profile in the N-polar Group III-nitride semiconductor structure (the upper portion of (via), as defined by the shape of the electrode structure excluding the top pads; Fig. 1) and a second cross-sectional profile in the substrate (a bottom portion of (via); Fig. 1), wherein
-the via (via) has a first cross-sectional width (hereinafter referred to as (W1)) of at the second side of the Group III-nitride semiconductor structure (top of (120)) and a second cross-sectional width (hereinafter referred to as (W2)) at the interface (at bottom of (110) / at (100a)), and wherein
- the first cross-sectional width (W1) is greater than or equal to the second cross-sectional width (W2). (See Fig. 1, this case it is greater than)
-a metal etch stop (e.g. (140); Fig. 1, Paragraph [0026]) in the via (via) which terminates at the interface between the substrate (100) and the N-polar Group III-nitride semiconductor structure ((110) and (120)).
Lee does not explicitly state:
-the Group III-nitride semiconductor device (here a HEMT) is N-polar
Romanczyk teaches:
-an N-polar GaN HEMT (Fig. 1; I. Introduction, II. Epitaxial-Growth and Device Details)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the device structure of Romanczyk into the device of Lee such that the Group III-nitride semiconductor structure was N-polar. This would be due to the fact that doing so would have provided the predictable result of incorporating a high-performance device technology (Romanczyk, I. Introduction) into the GaN-based device layer of Lee.
Neither Lee nor Romanczyk teach (as explained in the ‘Response to Arguments’ of the Final dated March 16, 2026):
the first cross-sectional profile comprising a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprising a second angle relative to the interface, the first angle being less than the second angle.
Then teaches a transistor device featuring vias ((120); Fig. 1A, Paragraph [0039]) which pass through a substrate ((102); Fig. 1A, Paragraph [0038]) and a Group III-nitride semiconductor structure (consisting of (104), (106), and (108); Fig. 1A, Paragraph [0038]), wherein the via (120) has a first cross-sectional width (hereinafter referred to as (W1) at the second side of the Group III-nitride semiconductor structure (top of (108)) and a second cross-sectional width (hereinafter referred to as (W2)) at the interface (bottom of (104) / top of (102)), wherein:
-the via (120) comprising a first cross-sectional profile ((120B); Fig. 1A, Paragraph [0039]) in the N-polar Group III-nitride semiconductor structure ((104), (106), and (108)), the first cross-sectional profile comprising a first angle relative to the interface (e.g. 90 degrees, as portion is vertical, Paragraph [0039]), and a second cross-sectional profile ((120A); Fig. 1A, Paragraph [0039]) in the substrate (102), the second cross-sectional profile comprising a second angle relative (necessarily greater than 90 degrees, due to tapered profile, Paragraph [0039]) to the interface, the first angle being less than the second angle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Then into the device of Lee and Romancztk such that the via comprises a first cross-sectional profile in the N-polar Group III-nitride semiconductor structure, the first cross-sectional profile comprises a first angle relative to the interface, and a second cross-sectional profile in the substrate, the second cross-sectional profile comprising a second angle relative to the interface, the first angle being less than the second angle. This would be due to the fact that it would achieve the predictable result of lowering power dissipation (Then, Paragraph [0034])
Regarding Claim 12, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, wherein:
-wherein the first cross-sectional width (Lee, (W1)) is greater than the second cross-sectional width (Lee, (W2)).
Regarding Claim 13, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, wherein:
-the first cross-sectional width (W1) is substantially the same as the second cross-sectional width (W2). (as part of ‘essentially vertical portion’ (120B)) (The Examiner notes that while ‘substantially’ is not defined by the Applicant, one of ordinary skill in the art would understand the limitation to mean as constant as allowable by manufacturing tolerances)
Regarding Claim 14, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, wherein:
- the via (Lee, (via)) has a third cross-sectional width (Lee, hereinafter referred to as (W3)) at the first side of the substrate (Lee, (100b)), and wherein the third cross-sectional width (Lee, (W3)) is greater than or equal to the second cross-sectional width (Lee, (W2)). (Lee, see Fig. 1, this case it is greater than)
Regarding Claim 15, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, wherein:
the N-polar Group III-nitride semiconductor structure comprises (Consequently due to bringing the device structure of Romanczyk into the device layer of Lee):
a barrier layer (Romanczyk, (AlGaN Backbarrier); Fig. 1, I. Introduction)), wherein the barrier layer comprises N-polar AlwGa1-wN, where 0.1<w<0.4 (in this case w = 0.38); and
-a channel layer (Romanczyk, (GaN Channel); Fig. 1, I. Introduction)), on the barrier layer (Romanczyk, (AlGaN Backbarrier)), wherein the channel layer comprises N-polar AlxGa1-xN, where 0≤x≤0.1 (in this case, x = 0).
Regarding Claim 16, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 15, wherein:
the N-polar Group III-nitride semiconductor structure comprises (Consequently due to bringing the device structure of Romanczyk into the device layer of Lee):
a buffer layer (Romanczyk, (GaN Buffer); Fig. 1, I. Introduction)), wherein the barrier layer (Romanczyk, (AlGaN Backbarrier)) is on the buffer layer (Romanczyk, (GaN Buffer)), such that the barrier layer is between the buffer layer and the channel layer (Romanczyk, (GaN Channel)),.
Regarding Claim 17, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 16, wherein:
- the buffer layer (Romanczyk, (GaN Buffer)) comprises N-polar AlvGa1-vN, where 0≤v≤0.1 (in this case v = 0).
Regarding Claim 18, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 15, further comprising:
-one or more cap layers on the channel layer (Romanczyk, (Al0.27Ga0.73N Cap); Fig. 1, I. Introduction)).
Regarding Claim 44, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 11, further comprising:
-a gate contact (Lee, electrode pad (120G); Fig. 1, Paragraph [0024])), a source contact (Lee, electrode pad (e.g. 120S); Fig. 1, Paragraph [0024])), and a drain contact (Lee, electrode pad (120D); Fig. 1, Paragraph [0024])) on the N-polar Group III-nitride semiconductor structure ((110) and (120)).
Regarding Claim 45, Lee, Romanczyk, and Then teach a transistor device (assembly (10); Fig. 1, Paragraph [0017], wherein GaN power transistors (HEMT) are used, Paragraph [0018]), of Claim 44, wherein:
-the gate contact (Lee, (120G)) is between the source contact (Lee, (120S)) and the drain contact (Lee, (120D)). (See Lee, right side of Fig. 3, top to bottom)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Romanczyk, and Then in view of Wu et al. (U.S. Pub. 2016/0020313), hereinafter Wu.
Regarding Claim 6, Lee, Romanczyk, and Then teach a semiconductor device (‘semiconductor device structure’ of assembly (10); Fig. 1, Paragraph [0017]), of Claim 1, upon which it depends, but does not explicitly disclose:
-the N-polar Group III-nitride semiconductor structure comprises an N-face at a surface opposite the substrate.
Wu teaches a semiconductor device, wherein:
the N-polar Group III-nitride semiconductor structure (device (1100) including a series of III-N layers, Fig. 11G, Paragraph [0106]) comprises an N-face at a surface opposite the substrate ((1102); Fig. 11G, Paragraph [0106]) (Paragraph [0106])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Wu into the device of Lee and Romanczyk such that the N-polar Group III-nitride semiconductor structure comprises an N-face at a surface opposite the substrate. This would be due to the fact that it would achieve the predictable result of having a [0 0 0 -1] orientation on the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DMITRI MIHALIOV/Examiner, Art Unit 2812
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights