DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor
Claims 1-7 have been examined.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statement dated February 14, 2023 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. A copy of the PTOL-1449 initialed and dated by the Examiner is attached to the instant office action.
Drawings
The drawings are objected to because of the following informalities.
Figure 1 includes the reference character “101,” which is not mentioned in the specification. The figures therefore fail to comply with 37 CFR 1.84(p)(5), which states, “Reference characters not mentioned in the description shall not appear in the drawings.”
In Figure 1, the text “Custom instruction Interface” is crossed by a dotted line. The figure therefore fails to comply with 37 CFR 1.84(p)(5), which states, “Numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height. They should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines.” (emphasis supplied)
The lines and text are faint, fuzzy, blurry, and pixelated. The figures therefore fail to comply with 37 CFR 1.84(l), which states, “All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. Lines and strokes of different thicknesses may be used in the same drawing where different thicknesses have a different meaning.” This issue commonly results from using grayscale or the like when producing the figures, e.g., in Adobe.
The view numbers are improperly capitalized. The figures therefore fail to comply with 37 CFR 1.84(u)(1), which states, “View numbers must be preceded by the abbreviation "FIG." Please amend from “Fig.” to “FIG.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of US Patent 12,190,160 (reference patent) which was filed as US Patent Application No. 18/169,003. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate the claims in the instant application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites, at line 5, “comprises of.” This phrase introduces ambiguity as the meaning of the word “of” cannot be determined in this context. It is customary to use “of” in the closed transitional phrase “consists of” and to omit the word “of” in the open-ended transitional phrase “comprising.” The open-ended transition “comprising” is complete in its meaning that the following elements are included in a set that may also include other elements. The phrase “comprising of” is a hybrid of the open-ended and closed transitions, and renders the scope of the claims indefinite. For purposes of examination, the limitation is interpreted as, “comprising [[of]].” The term is used throughout the claims and each instance is likewise rejected.
Claim 2 recites, at lines 5-6, “a data buffer (403) to hold data from said custom instruction input, store data from said custom instruction input or combination thereof.” The meaning of this term cannot be definitely determined. Holding data is essentially synonymous with storing data, so the use of the two as alternatives does not make sense. Nor does the use of the two in combination. For purposes of examination, the limitation is interpreted as, “a data buffer (403) to store data from said custom instruction input .”
Claim 5 recites, at line 3, “while become intermediary.” The meaning of this term cannot be definitely determined. For purposes of examination, the limitation is interpreted as the control block transfers the data in question between the embedded processor and the neural network layer accelerator. Claim 6 has similar limitations and is similarly rejected.
Claims 2-7 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,204,747 by Zejda et al. (hereinafter referred to as “Zejda”) in view of US Publication No. 2023/0042226 by Itani et al. (hereinafter referred to as “Itani”).
Regarding claim 1, Zejda discloses:
a neural network accelerator (103) in a field programmable gate array (FPGA), comprising of (Zejda discloses, Abstract, a neural network accelerator on an FPGA.):
at least one neural network layer accelerator (303) (Zejda discloses, at Figure 1 and related description, a multilayer neural network. Zejda discloses, a Figure 2 and related description, a neural network accelerator to implement the multilayer neural network in an FPGA. Together this discloses at least one neural network layer accelerator.);
characterized in that said neural network accelerator (103) further comprises of a command control block (301) (Zejda discloses, at Figure 10 and related description, control logic, which discloses that said neural network accelerator (103) further comprises of a command control block.);
said neural network accelerator (103) further comprises of a response control block (305) (Zejda discloses, at Figure 10 and related description, write control, which discloses said neural network accelerator further comprises a response control block.);
said neural network accelerator (103) is connected to at least one embedded processor (102) in said FPGA through…[an] interface (Zejda discloses, at Figure 10 and related description, an interface coupling the kernel to peripheral components. As disclosed at Figure 9 and related description, the peripherals can include a microprocessor. Together this discloses said neural network accelerator is connected to at least one embedded processor in said FPGA through…[an] interface.
Zejda does not explicitly disclose the aforementioned interface is a custom instruction interface.
However, in the same field of endeavor (e.g., instruction processing) Itani discloses:
custom instructions (Itani discloses, at ¶ [0224], custom instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zejda’s interface to apply to custom instructions, as disclosed by Itani, in order to improve performance by allowing acceleration of commonly occurring operations. See, e.g., Itani, ¶ [0224].
Regarding claim 2, Zejda, as modified, discloses the elements of claim 1, as discussed above. Zejda also discloses:
said neural network layer accelerator (303) comprises of: a control unit (401) to interpret at least one custom instruction input of said custom instruction interface (Zejda discloses, at Figure 10 and related description, read control, which discloses a control unit to interpret at least one custom instruction input of said custom instruction interface.);
a data buffer (403) to hold data from said custom instruction input, store data from said custom instruction input or combination thereof (Zejda discloses, at Figure 10 and related description, FIFOs, which discloses a data buffer to hold data from said custom instruction input, store data from said custom instruction input or combination thereof.); and
a compute unit (405) to perform at least one operation, computation or combination thereof, required by at least one targeted layer type of said neural network accelerator (103) (Zejda discloses, at Figure 10 and related description, a compute array, which discloses a compute unit to perform at least one operation, computation or combination thereof, required by at least one targeted layer type of said neural network accelerator.);
said control unit (401) further to facilitate transfer of computation output from said compute unit (405) to said response control block (305) (Zejda discloses, at Figure 10 and related description, read control, which discloses said control unit further to facilitate transfer of computation output from said compute unit to said response control block as there will be no output without there first being input.).
Regarding claim 3, Zejda, as modified, discloses the elements of claim 1, as discussed above. Zejda also discloses:
said custom instruction interface comprises of input related signals and output related signals (Zejda discloses, at Figure 10 and related description, an interface for reading and writing data, which discloses said custom instruction interface comprises of input related signals and output related signals.).
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Zejda in view of Itani in view of US Publication No. 2016/0196227 by Yoo et al. (hereinafter referred to as “Yoo”).
Regarding claim 4, Zejda, as modified, discloses the elements of claim 3, as discussed above. Zejda does not explicitly disclose said input related signals are "commandvalid" signal and "command ready" signal that are used to indicate the validity of "input0" signal, "inputl" signal, and "function_id" signal; and said output related signals are "response valid" signal and the "response ready" signal that are used to indicate the validity of "output" signal.
However, in the same field of endeavor (e.g., interfaces) Yoo discloses:
valid and ready signals (Yoo discloses, at Figure 7 and related description, valid and ready signals for requests, responses, and data, which discloses said input related signals are "commandvalid" signal and "command ready" signal that are used to indicate the validity of "input0" signal, "inputl" signal, and "function_id" signal; and said output related signals are "response valid" signal and the "response ready" signal that are used to indicate the validity of "output" signal.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zejda to include valid and ready signals, as disclosed by Yoo, to ensure proper communications.
Regarding claim 5, Zejda, as modified, discloses the elements of claim 4, as discussed above. Zejda does not explicitly disclose said command control block (301) receives said "functionid" signal from said embedded processor (102) while become intermediary for transferring of "commandvalid" signal from said embedded processor (102) to said neural network layer accelerator (303) and transferring of "command ready" signal from said neural network layer accelerator (303) to said embedded processor.
However, in the same field of endeavor (e.g., interfaces) Yoo discloses:
valid and ready signals (Yoo discloses, at Figure 7 and related description, valid and ready signals for requests, responses, and data, which discloses said command control block (301) receives said "functionid" signal from said embedded processor (102) while become intermediary for transferring of "commandvalid" signal from said embedded processor (102) to said neural network layer accelerator (303) and transferring of "command ready" signal from said neural network layer accelerator (303) to said embedded processor.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zejda to include valid and ready signals, as disclosed by Yoo, to ensure proper communications.
Regarding claim 6, Zejda, as modified, discloses the elements of claim 4, as discussed above. Zejda also discloses:
said response control block (305) becomes intermediary for transferring of "response valid" signal and "output" signal from said neural network layer accelerator (303) to said embedded processor (102) (Zejda discloses, at Figures 9 and 10 and related description, write control that transfers information between processing circuitry, i.e., neural network layer accelerator circuitry, and peripherals, e.g., embedded processor, which discloses, said response control block (305) becomes intermediary for transferring of "response valid" signal and "output" signal from said neural network layer accelerator (303) to said embedded processor (102).).
Regarding claim 7, Zejda, as modified, discloses the elements of claim 4, as discussed above. Zejda also discloses:
said layer accelerator (303) receives said "input0" signal, "inputi" signal, said "response ready" signal and said "function_id" signal from said embedded processor (102); receives "commandvalid" signal from said embedded processor (102) through said command control block (301); transmits "commandready" signal to said embedded processor (102) through said command control block (301); transmits "responsevalid" signal and "output" signal to said embedded processor (102) through said command control block (301) (Zejda discloses, at Figures 9 and 10 and related description, processing circuitry exchanging signals with peripherals, which discloses said layer accelerator (303) receives said "input0" signal, "inputi" signal, said "response ready" signal and said "function_id" signal from said embedded processor (102); receives "commandvalid" signal from said embedded processor (102) through said command control block (301); transmits "commandready" signal to said embedded processor (102) through said command control block (301); transmits "responsevalid" signal and "output" signal to said embedded processor (102) through said command control block (301).).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20190272150 by Lin discloses NN layer.
US 20240394550 by Ghavami discloses an FPGA accelerator with a core, control, buffer.
US 20160034617 by Caltagirone discloses input and output ready and valid signals.
US 20240078417 by Temam discloses a neural network accelerator with an interface and buses.
US 12423096 by Dasaluku discloses an accelerator and interface and input and output.
US 12393823 by Tian discloses I/O interface.
US 20210073171 by Master discloses ready and valid.
US 7844761 by Orthner discloses control interface, buffers.
US 20070169022 by Jones discloses valid and accept signals.
US 20230419585 by Smith discloses ready and valid signals and ids.
US 20190361486 by Malik discloses tready, tvalid, tdata,, tctrl.
US 20150236870 by Lee discloses interface signals and has a timing diagram.
US 20220012574 by Imber discloses a DNN accelerator with layers.
US 20210256303 by Wei discloses accelerators assigned to layers of the CNN.
US 20200301898 by Samynathan discloses a multi-layer accelerator, embedded core.
NPL_Valencia discloses neural network acceleration using FPGA.
NPL_Sharma discloses NN acceleration on FPGA.
NPL_Liu discloses CNNs on FPGAs and a controller.
NPL_Indirli discloses multiple layers of accelerators.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183