DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 3-7 have been amended.
Claim 2 has been cancelled.
Claims 1 and 3-7 have been examined.
The drawing objections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The double patenting rejections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
Drawings
The drawings are objected to because of the following informalities.
The lines and text are faint, fuzzy, blurry, and pixelated. The figures therefore fail to comply with 37 CFR 1.84(l), which states, “All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. Lines and strokes of different thicknesses may be used in the same drawing where different thicknesses have a different meaning.” This issue commonly results from using grayscale or the like when producing the figures, e.g., in Adobe.
The view numbers are improperly capitalized. The figures therefore fail to comply with 37 CFR 1.84(u)(1), which states, “View numbers must be preceded by the abbreviation "FIG." Please amend from “Fig.” to “FIG.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
a control unit configured to interpret in claim 1—no corresponding structure found; and
a compute unit configured to perform in claim 1-- no corresponding structure found.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 3-7 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites a control unit configured to interpret and a compute unit configured to perform. The disclosure does not provide adequate structure to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. This rejection could be overcome by changing unit to circuit, or something similar.
Claims 3-7 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites a control unit configured to interpret and a compute unit configured to perform. These limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because they use a generic placeholder, i.e., unit, tied to functional language. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed functions and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite. This rejection could be overcome by changing unit to circuit, or something similar.
Claim 1 recites, “the neural network layer accelerator.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the limitation is interpreted as, “the at least one neural network layer accelerator.” Claims 5 and 6 include similar language and are similarly rejected.
Claim 1 recites, “the response valid signal. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites, “the output signal. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites, at line 2, “comprises of.” This phrase introduces ambiguity as the meaning of the word “of” cannot be determined in this context. It is customary to use “of” in the closed transitional phrase “consists of” and to omit the word “of” in the open-ended transitional phrase “comprises.” The open-ended transition “comprises” is complete in its meaning that the following elements are included in a set that may also include other elements. The phrase “comprises of” is a hybrid of the open-ended and closed transitions, and renders the scope of the claims indefinite. For purposes of examination, the limitation is interpreted as, “comprises [[of]].”
Claim 7 recites, “said layer accelerator.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the limitation is interpreted as, “said at least one neural network layer accelerator
Claims 3-7 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,204,747 by Zejda et al. (hereinafter referred to as “Zejda”) in view of US Publication No. 2023/0042226 by Itani et al. (hereinafter referred to as “Itani”) in view of US Publication No. 2016/0196227 by Yoo et al. (hereinafter referred to as “Yoo”).
Regarding claim 1, Zejda discloses:
a neural network accelerator in a field programmable gate array (FPGA), comprising (Zejda discloses, Abstract, a neural network accelerator on an FPGA.):
at least one neural network layer accelerator (Zejda discloses, at Figure 1 and related description, a multilayer neural network. Zejda discloses, a Figure 2 and related description, a neural network accelerator to implement the multilayer neural network in an FPGA. Together this discloses at least one neural network layer accelerator.);
a command control block (Zejda discloses, at Figure 10 and related description, control logic, which discloses a command control block.);
a response control block (Zejda discloses, at Figure 10 and related description, write control, which discloses a response control block.);
wherein the neural network accelerator is connected to at least one embedded processor …through…[an] interface (Zejda discloses, at Figure 10 and related description, an interface coupling the kernel to peripheral components. As disclosed at Figure 9 and related description, the peripherals can include a microprocessor. Together this discloses said neural network accelerator is connected to at least one embedded processor through…[an] interface See also col. 5, lines 26-31, which discloses using the interface with an embedded processor.), and
wherein the neural network layer accelerator comprises: a control unit configured to interpret at least one custom instruction input of the custom instruction interface (Zejda discloses, at Figure 10 and related description, read control, which discloses a control unit to interpret at least one custom instruction input of said custom instruction interface.);
a data buffer configured to store data from the custom instruction input (Zejda discloses, at Figure 10 and related description, FIFOs, which discloses a data buffer to hold data from said custom instruction input, store data from said custom instruction input or combination thereof.);
a compute unit configured to perform at least one of an operation or a computation required by at least one targeted layer type of the neural network accelerator (Zejda discloses, at Figure 10 and related description, a compute array, which discloses a compute unit to perform at least one operation, computation or combination thereof, required by at least one targeted layer type of said neural network accelerator.);
the control unit being further configured to transfer computation output from the compute unit to the response control block (Zejda discloses, at Figure 10 and related description, read control, which discloses said control unit further to facilitate transfer of computation output from said compute unit to said response control block as there will be no output without there first being input.).
wherein the response control block is configured to transfer, by means of multiplexing… signal[s] from each of the at least one neural network layer accelerator to the custom instruction interface to the at least one embedded processor (Zejda discloses, at Figure 10 and related description, write control sending signals to the interface using a mux, which discloses transferring, by means of multiplexing, signals to the interface.).
Zejda does not explicitly disclose the aforementioned embedded processor is in the FPGA, the aforementioned interface is a custom instruction interface, and the aforementioned signals are response valid and output.
However, Zejda discloses, at Figure 9 and related description, various configurations, including system on chip, and the like. This discloses that it would have been obvious to incorporate the processor, e.g., processing system 912 of Figure 9, into the FPGA. See also Figure 11, which shows a second processing system in the programmable IC 928, i.e., in the FPGA.
Also, in the same field of endeavor (e.g., instruction processing) Itani discloses:
custom instructions (Itani discloses, at ¶ [0224], custom instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zejda’s interface to apply to custom instructions, as disclosed by Itani, in order to improve performance by allowing acceleration of commonly occurring operations. See, e.g., Itani, ¶ [0224].
Also, in the same field of endeavor (e.g., interfaces) Yoo discloses:
valid and ready signals (Yoo discloses, at Figure 7 and related description, valid and payload signals for requests, responses, and data, which discloses valid and output signals.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zejda to include valid and ready signals, as disclosed by Yoo, to ensure proper communications.
Regarding claim 3, Zejda, as modified, discloses the elements of claim 1, as discussed above. Zejda also discloses:
said custom instruction interface comprises of input related signals and output related signals (Zejda discloses, at Figure 10 and related description, an interface for reading and writing data, which discloses said custom instruction interface comprises of input related signals and output related signals.).
Regarding claim 4, Zejda, as modified, discloses the elements of claim 3, as discussed above. Zejda does not explicitly disclose said input related signals are "command_valid" signal and "command_ready" signal that are used to indicate the validity of "input0" signal, "inputl1 signal, and "function_id" signal; and said output related signals are "response_valid" signal and the "response_ready" signal that are used to indicate the validity of "output" signal.
However, in the same field of endeavor (e.g., interfaces) Yoo discloses:
valid and ready signals (Yoo discloses, at Figure 7 and related description, valid and ready signals for requests, responses, and data, which discloses said input related signals are "command_valid" signal and "command_ready" signal that are used to indicate the validity of "input0" signal, "input1" signal, and "function_id" signal; and said output related signals are "response_valid" signal and the "response_ready" signal that are used to indicate the validity of "output" signal.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zejda to include valid and ready signals, as disclosed by Yoo, to ensure proper communications.
Regarding claim 5, Zejda, as modified, discloses the elements of claim 4, as discussed above. Zejda does not explicitly disclose said command control block receives said "function_id" signal from said embedded processor, transfers a "command_valid" signal from said embedded processor to said neural network layer accelerator and transfers a "command_ready" signal from said neural network layer accelerator to said embedded processor.
However, in the same field of endeavor (e.g., interfaces) Yoo discloses:
valid and ready signals (Yoo discloses, at Figure 7 and related description, valid and ready signals for requests, responses, and data, which discloses said command control block receives said "function_id" signal from said embedded processor, transfers a "command_valid" signal from said embedded processor to said neural network layer accelerator and transfers a "command_ready" signal from said neural network layer accelerator to said embedded processor.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Zejda to include valid and ready signals, as disclosed by Yoo, to ensure proper communications.
Regarding claim 6, Zejda, as modified, discloses the elements of claim 4, as discussed above. Zejda also discloses:
said response control block transfers a "response_valid" signal and an "output" signal from said neural network layer accelerator to said embedded processor (Zejda discloses, at Figures 9 and 10 and related description, write control that transfers information between processing circuitry, i.e., neural network layer accelerator circuitry, and peripherals, e.g., embedded processor, which discloses, said response control block (305) becomes intermediary for transferring of "response valid" signal and "output" signal from said neural network layer accelerator (303) to said embedded processor (102).).
Regarding claim 7, Zejda, as modified, discloses the elements of claim 4, as discussed above. Zejda also discloses:
said layer accelerator receives said "input0" signal, "input1" signal, said "response_ready" signal and said "function_id" signal from said embedded processor; receives "command_valid" signal from said embedded processor through said command control block; transmits "command_ready" signal to said embedded processor through said command control block; transmits "response_valid" signal and "output" signal to said embedded processor through said command control block (Zejda discloses, at Figures 9 and 10 and related description, processing circuitry exchanging signals with peripherals, which discloses said layer accelerator receives said "input0" signal, "input1" signal, said "response_ready" signal and said "function_id" signal from said embedded processor; receives "command_valid" signal from said embedded processor through said command control block; transmits "command_ready" signal to said embedded processor through said command control block; transmits "response_valid" signal and "output" signal to said embedded processor through said command control block.).
Response to Arguments
On pages 7-8 of the response filed May 6, 2026 (“response”), the Applicant argues, “Applicant submits that, accordingly, the neural accelerator is configured so that users, designers or developers can enable only the specific types of layer accelerator that are required for a targeted neural network application, instead of enabling all of a plurality of network layer accelerators that are available, thereby providing efficient resource utilization, as discussed on page 7, line 8 to page 8, line 2 of the specification of the present application.”
Though fully considered, the Examiner respectfully disagrees. The Applicant is arguing limitations from the specification that are not required by the claims. As it is improper to import limitations from the specification, and since the Applicant has chosen not to include the limitations in the claims, the Applicant’s arguments are deemed unpersuasive.
On page 8 of the response the Applicant argues, “For example, the presently recited neural network accelerator includes, at least one neural network layer accelerator that is connected to at least one embedded processor in the field programmable gate array (FPGA) through a custom instruction interface. Neither Zedia nor Itani teach such feature. That is, whereas the claimed invention is directed to a system having a physical, low-latency custom instruction interface that is built directly into a CPUpipeline, Zejda abstracts accelerator behavior into assembly like instructions (Zejda at col. 4, lines 6 - 16). FIG. 9 of Zejda, which is cited in the Office Action, shows acceleration circuit 930, which includes static region 934 and programmable region 936, included in programmable IC 928, which is not embedded within processing system 910, much less microprocessor 912, contrary to what is alleged on pages 6 - 7 of the Office Action. Further, at col. 12, lines 45 - 50, Zejda further discloses that processing system 910 is shown separately from hardware accelerator 816, though other examples have processing system 910 and hardware accelerator 816 implemented on a same IC. That is, Zejda does not include any teaching or suggestion of an accelerator connected to an embedded processor in an FPGA through a custom instruction interface, as presently recited. Further, by having the neural network accelerator connected to at least one embedded processor in the FPGA through a custom instruction interface, the processor is able to actively interpret a custom instruction, store data from the custom instruction input, and perform at least one operation or computation required by at least one targeted layer type of the neural network accelerator, as disclosed at, e.g., page 10, line 17 to page 11, line 6 of the specification of the present application. Zejda does not teach or suggest such a processor-based neural network accelerator actively executing the model, as in Claim 1.”
Though fully considered, the Examiner respectfully disagrees. As discussed above, Zejda discloses an interface between programmable circuitry, e.g., an FPGA and a processor. See, e.g., Figure 5 or Figure 9. Zejda discloses that the processor can be an embedded processor. See, e.g., col. 5, lines 26-31. The Examiner concedes that the processor is not explicitly disclosed as being included in the FPGA. However, it would have been obvious to do so because whether to make components separate or integrated is one of the many fundamental design choices based on well-known tradeoffs that are within the skill of those of skill in the art. See, e.g., col. 12, which discloses implementations that utilize various degrees of integration. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 8 of the response the Applicant argues, “Claim 1 is currently amended to further recite that the previously recited compute unit is configured to transfer, by multiplexing, "the 'response_valid' signal and the 'output' signal from each of the at least one neural network layer accelerator to one 'response_valid' signal and one 'output' signal of the custom instruction interface to the at least one embedded processor." Such features are not taught or suggested by Zejda.”
Though fully considered, the Examiner respectfully disagrees. Zejda discloses using multiplexers to select between signals. See, e.g., Figure 10. When combined with Yoo’s disclosure of the signals in question, the claims are obvious. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
Prosecution Insights