DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/23/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4,6,8-11 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: reference character 156 shown in Fig 3C. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2022/0344463 A1, hereinafter Jung ‘463.) in view of Brown et al. (US 2010/0035403 A1, hereinafter Brown ‘403), in view of the following arguments.
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With respect to Claim 1 Jung ‘463 discloses an integrated circuit (IC) structure (Fig. 1, 3A-3F and 17), comprising:
a substrate (substrate upon which structure of Fig 1, 3A-3F is fabricated, Fig 17, Para [0129] discloses a substrate) including a first active region (RX01, Fig 3D, Para [0057]) and a second active region (RX02, Fig 3D, Para [0057]);
a first gate electrode (GE1, as shown in annotated Fig 3D of Jung ‘463, Para [0053]) over the first active region (RX01)(arrangement disclosed in annotated Fig 3D of Jung ‘463);
a second gate electrode (GE2, as shown in annotated Fig 3D of Jung ‘463, Para [0053]) over the second active region (RX02);
a first trench isolation (IS01, Fig 3D, Para [0053]) electrically isolating the first active region (RX01) and the first gate electrode (GE1) from the second active region (RX02) and the second gate electrode (GE2), wherein first ends (as shown in annotated Fig 3D of Jung ‘463, hereinafter FEFAR) of the first active region (RX01) and the first gate electrode (GE1) abut a first sidewall (as shown in annotated Fig 3D of Jung ‘463, hereinafter FSFTI) of the first trench isolation (IS01) and first ends (as shown in annotated Fig 3D of Jung ‘463, hereinafter FESAR) of the second active region (RX02) and the second gate electrode (GE2) abut a second, opposing sidewall (as shown in annotated Fig 3D of Jung ‘463, hereinafter SSFTI) of the first trench isolation (IS01); and
a conductive strap (conductive area over IS01, Fig 3D, Para [0148-0149]) extending over an upper end (top of IS01) of the first trench isolation (IS01)(disclosed in Fig 3D) and electrically coupling the first gate electrode (GE1) and the second gate electrode (GE2)(Para [0053] discloses G01 (of which GE1 is part) as electrically connected to RX01 and RX02).
Jung ‘463 fails to expressly disclose a buried insulator layer and a first trench isolation extending below the buried insulator layer.
Nevertheless, in a related endeavor (Fig 2 of Brown ‘403), Brown ‘403 teaches a buried insulator layer (112, Fig 2 of Brown ‘403, Para [0038]) and a first trench isolation (140, Fig 2 of Brown ‘403, Para [0042]) extending below the buried insulator layer (112, Fig 2 of Brown ‘403, Para [0042])(140 extending below buried insulator layer 112 disclosed in Fig 2 and Para [0042]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Brown ‘403’s teaching a buried insulator layer and a first trench isolation extending below the buried insulator layer into Jung ‘463’s integrated circuit structure. Jung ‘463 teaches a standard cell IC structure with a first trench isolation that electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode but Jung ‘463 is silent on the depth of the first trench isolation. Brown ‘403 teaches isolation regions between active regions and teaches the isolation trench extending below the buried insulator on the substrate as described above. The ordinary artisan would have been motivated to modify Jung ‘463 in the manner set forth above, at least, because as Brown ‘403 teaches in Para [0037] the taught embodiment can “improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer”.
As incorporated, the teaching of Brown ‘403 of a buried insulator layer (112) would be used in the substrate of Jung ‘463. And the teaching of Brown ‘403 of a first trench isolation (140) extending below the buried insulator layer (112) would be used such that (IS01) of Jung ‘463 would extend below the buried insulator layer (112) of Jung ‘463 as modified by Brown ‘403.
As incorporated, the first active region (RX01) and second active region (RX02) of Jung ‘463 are over the buried insulator layer (112) of Jung ‘463 as modified by Brown ‘403.
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With respect to Claim 2 Jung ‘463 as modified by Brown ‘403 discloses all limitations of the IC structure of claim 1, and Jung ‘463 further discloses wherein the first end (FEFAR) of the first active region (RX01) is vertically aligned (annotated Fig 3D_2 of Jung ‘463 discloses first end of the first active region vertically aligned with first end of the first gate electrode at the area they contact) with the first end (first end of GE1 as shown in annotated Fig 3D_2 of Jung ‘463) of the first gate electrode (GE1) against the first sidewall (FSFTI) of the first trench isolation (IS01)(annotated Fig 3D_2 of Jung ‘463 discloses alignment), and the first end (FESAR as shown in annotated Fig 3D_2 of Jung ‘463) of the second active region (RX02) is vertically aligned (annotated Fig 3D_2 of Jung ‘463 discloses first end of the second active region vertically aligned with first end of the second gate electrode at the area they contact) with the first end (first end of GE2 as shown in annotated Fig 3D_2 of Jung ‘463) of the second gate electrode (GE2) against the second (SSFTI), opposite side of the first trench isolation (IS01)(arrangement disclosed in annotated Fig 3D_2 of Jung ‘463).
With respect to Claim 3 Jung ‘463 as modified by Brown ‘403 discloses all limitations of the IC structure of claim 1,
And in a related endeavor (Fig 13A of Jung ‘463), Jung ‘463 teaches further comprising a second trench isolation (CT1, as shown in annotated Fig 13A of Jung ‘463, Para [0094]) at a second end (right side of F21 as shown in annotated Fig 13A of Jung ‘463) of the first active region (F22/F21, First active region shown in annotated Fig 13A of Jung ‘463, Para [0093]) and the first gate electrode (CA1, first gate electrode as shown in annotated Fig 13A of Jung ‘463, Para [0093]) opposite the first ends thereof (left side of F22 as they abut first trench isolation CT2 as shown in annotated Fig 13A of Jung ‘463)(Para [0093] discloses active areas F21/F22 and F12/F11, each separated by isolation regions).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teaching of Jung 463’s further comprising a second trench isolation at a second end of the first active region and the first gate electrode opposite the first ends thereof into Jung 463 as modified by Brown ‘403’s device. The ordinary artisan would have been motivated to modify Jung ‘463 as modified by Brown ‘403 in the manner set forth above, at least, because the additional trench isolation at the second end of the first active device and first gate electrode provides additional dielectric protection to the active area, reducing the possibility of parasitic capacitance between active regions. In addition the additional trench isolation serves the same purpose as the first isolation trench and is merely a duplication of the first trench isolation. MPEP 2144.04(VI)(B).
As incorporated, the second trench isolation at a second end of the first active region and the first gate electrode opposite the first ends thereof as taught by Jung ‘463 in the further embodiment would be used in the device of Jung ‘463 as modified by Brown ‘403.
With respect to Claim 4 Jung ‘463 as modified by Brown ‘403 discloses all limitations of the IC structure of claim 3, and Jung ‘463 discloses further comprising a third trench isolation (CT3, as shown in annotated Fig 13A of Jung ‘463, Para [0094]) at a second end (left side of F24 as shown in annotated Fig 13A of Jung ‘463) of the second active region (F23/F24, Second active region shown in annotated Fig 13A of Jung ‘463, Para [0093]) and the second gate electrode (CA2, second gate electrode as shown in annotated Fig 13A of Jung ‘463, Para [0093]) opposite the first ends thereof (right side of F23 as they abut first trench isolation CT2 as shown in annotated Fig 13A of Jung ‘463)(Para [0093] discloses active areas F24/F23 and F32/F31, each separated by isolation regions).
With respect to Claim 6 Jung ‘463 as modified by Brown ‘403 discloses all limitations of the IC structure of claim 1, and Jung ‘463 discloses further wherein the first active region (RX01) includes an n-type dopant (disclosed in Para [0033]) to create an n-type field effect transistor (NFET in RX01 is disclosed in Para [0033]) with the first gate electrode (GE1), and the second active region (RX02) include a p-type dopant (disclosed in Para [0033]) to create a p-type field effect transistor (PFET in RX01 is disclosed in Para [0033]) with the second gate electrode (GE2).
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With respect to Claim 8 Jung ‘463 discloses a standard cell for an integrated circuit (IC) structure (Fig. 1, 3A-3F and 17)(Para [0032] discloses structure C01 as standard cell) having logic (cell design used in logic synthesis disclosed in Para [0125]) arranged in a plurality of cell rows (Para [0032] discloses a plurality of cells of Fig 1) extending in a first direction (X as shown in Fig 1, Para [0032]), the standard cell comprising:
within a cell boundary (boundary of C01, Fig 1, Para [0033], denoted by dashed box:
an area (areas disclosed in Fig 1) defining a first active region (RX01, Fig 1, Para [0033]) and a second active region (RX02, Fig 1, Para [0033]);
a first gate electrode (GE1, as shown in annotated Fig 3D of Jung ‘463, Para [0053]) over the first active region (RX01)(arrangement disclosed in annotated Fig 3D of Jung ‘463);
a first gate electrode over the first active region (addressed above, see Examiner interpretation above);
a second gate electrode (GE2, as shown in annotated Fig 3D of Jung ‘463, Para [0053]) over the second active region (RX02);
a first trench isolation (IS01, Fig 3D, Para [0053]) electrically isolating the first active region (RX01) and the first gate electrode (GE1) from the second active region (RX02) and the second gate electrode (GE2)(arrangement disclosed in annotated Fig 3D of Jung ‘463), wherein first ends (as shown in annotated Fig 3D of Jung ‘463, hereinafter FEFAR) of the first active region (RX01) and the first gate electrode (GE1) abut a first sidewall (as shown in annotated Fig 3D of Jung ‘463, hereinafter FSFTI) of the first trench isolation (IS01) and first ends (as shown in annotated Fig 3D of Jung ‘463, hereinafter FESAR) of the second active region (RX02) and the second gate electrode (GE2) abut a second, opposing sidewall (as shown in annotated Fig 3D of Jung ‘463, hereinafter SSFTI) of the first trench isolation (IS01); and
a conductive strap (conductive area over IS01, Fig 3D, Para [0148-0149]) extending over an upper end (top of IS01) of the first trench isolation (IS01)(disclosed in Fig 2D) and electrically coupling the first gate electrode (GE1) and the second gate electrode (GE2)(Para [0053] discloses G01 (of which GE1 is part) as electrically connected to RX01 and RX02).
Jung ‘463 fails to expressly disclose a buried insulator layer and a first trench isolation extending below the buried insulator layer.
Nevertheless, in a related endeavor (Fig 2 of Brown ‘403), Brown ‘403 teaches a buried insulator layer (112, Fig 2 of Brown ‘403, Para [0038]) and a first trench isolation (140, Fig 2 of Brown ‘403, Para [0042]) extending below the buried insulator layer (112, Fig 2 of Brown ‘403, Para [0042])(140 extending below buried insulator layer 112 disclosed in Fig 2 and Para [0042]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Brown ‘403’s teaching a buried insulator layer and a first trench isolation extending below the buried insulator layer into Jung ‘463’s integrated circuit structure. Jung ‘463 teaches a standard cell IC structure with a first trench isolation that electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode but Jung ‘463 is silent on the depth of the first trench isolation. Brown ‘403 teaches isolation regions between active regions and teaches the isolation trench extending below the buried insulator on the substrate as described above. The ordinary artisan would have been motivated to modify Jung ‘463 in the manner set forth above, at least, because as Brown ‘403 teaches in Para [0037] the taught embodiment can “improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer”.
As incorporated, the teaching of Brown ‘403 of a buried insulator layer (112) would be used in the substrate of Jung ‘463. And the teaching of Brown ‘403 of a first trench isolation (140) extending below the buried insulator layer (112) would be used such that (IS01) of Jung ‘463 would extend below the buried insulator layer (112) of Jung ‘463 as modified by Brown ‘403.
As incorporated, the first active region (RX01) and second active region (RX02) of Jung ‘463 are over the buried insulator layer (112) of Jung ‘463 as modified by Brown ‘403.
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With respect to Claim 9 Jung ‘463 as modified by Brown ‘403 discloses all limitations of the standard cell of claim 8, and Jung ‘463 further discloses wherein the first end (FEFAR) of the first active region (RX01) is vertically aligned (annotated Fig 3D_2 of Jung ‘463 discloses first end of the first active region vertically aligned with first end of the first gate electrode at the area they contact) with the first end (first end of GE1 as shown in annotated Fig 3D_2 of Jung ‘463) of the first gate electrode (GE1) against the first sidewall (FSFTI) of the first trench isolation (IS01)(annotated Fig 3D_2 of Jung ‘463 discloses alignment), and the first end (FESAR as shown in annotated Fig 3D_2 of Jung ‘463) of the second active region (RX02) is vertically aligned (annotated Fig 3D_2 of Jung ‘463 discloses first end of the second active region vertically aligned with first end of the second gate electrode at the area they contact) with the first end (first end of GE2 as shown in annotated Fig 3D_2 of Jung ‘463) of the second gate electrode (GE2) against the second (SSFTI), opposite side of the first trench isolation (IS01)(arrangement disclosed in annotated Fig 3D_2 of Jung ‘463).
With respect to Claim 10 Jung ‘463 as modified by Brown ‘403 discloses all limitations of the standard cell of claim 8,
And in a related endeavor (Fig 13A of Jung ‘463), Jung ‘463 teaches further comprising a second trench isolation (CT1, as shown in annotated Fig 13A of Jung ‘463, Para [0094]) at a second end (right side of F21 as shown in annotated Fig 13A of Jung ‘463) of the first active region (F22/F21, First active region shown in annotated Fig 13A of Jung ‘463, Para [0093]) and the first gate electrode (CA1, first gate electrode as shown in annotated Fig 13A of Jung ‘463, Para [0093]) opposite the first ends thereof (left side of F22 as they abut first trench isolation CT2 as shown in annotated Fig 13A of Jung ‘463)(Para [0093] discloses active areas F21/F22 and F12/F11, each separated by isolation regions), wherein a portion of the second trench isolation (CT1) extends beyond the cell boundary (boundary between R1 and R2 as shown in Fig 13A)(Fig 13A discloses CT1 extends between R1 and R2, and Para [0094] discloses CT1 on boundary).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teaching of Jung 463’s further comprising a second trench isolation at a second end of the first active region and the first gate electrode opposite the first ends thereof, wherein a portion of the second trench isolation extends beyond the cell boundary into Jung 463 as modified by Brown ‘403’s device. The ordinary artisan would have been motivated to modify Jung ‘463 as modified by Brown ‘403 in the manner set forth above, at least, because the additional trench isolation at the second end of the first active device and first gate electrode provides additional dielectric protection to the active area, reducing the possibility of parasitic capacitance between active regions. In addition the additional trench isolation serves the same purpose as the first isolation trench and is merely a duplication of the first trench isolation. MPEP 2144.04(VI)(B).
As incorporated, the second trench isolation at a second end of the first active region and the first gate electrode opposite the first ends thereof as taught by Jung ‘463 in the further embodiment would be used in the device of Jung ‘463 as modified by Brown ‘403.
With respect to Claim 11 Jung ‘463 as modified by Brown ‘403 discloses all limitations of the standard cell of claim 10, and Jung ‘463 discloses further comprising a third trench isolation (CT3, as shown in annotated Fig 13A of Jung ‘463, Para [0094]) at a second end (left side of F24 as shown in annotated Fig 13A of Jung ‘463) of the second active region (F23/F24, Second active region shown in annotated Fig 13A of Jung ‘463, Para [0093]) and the second gate electrode (CA2, second gate electrode as shown in annotated Fig 13A of Jung ‘463, Para [0093]) opposite the first ends thereof (right side of F23 as they abut first trench isolation CT2 as shown in annotated Fig 13A of Jung ‘463)(Para [0093] discloses active areas F24/F23 and F32/F31, each separated by isolation regions), wherein a portion of the third trench isolation (CT3) extends beyond the cell boundary(boundary between R2 and R3 as shown in Fig 13A)(Fig 13A discloses CT3 extends between R2 and R3, and Para [0094] discloses CT3 on boundary).
With respect to Claim 13 Jung ‘463 as modified by Brown ‘403 disclose all limitations of the standard cell of claim 8, and Jung ‘463 further discloses wherein the first active region (RX01) includes an n-type dopant (disclosed in Para [0033]) to create an n-type field effect transistor (NFET in RX01 is disclosed in Para [0033]) with the first gate electrode (GE1), and the second active region (RX02) include a p-type dopant (disclosed in Para [0033]) to create a p-type field effect transistor (PFET in RX01 is disclosed in Para [0033]) with the second gate electrode (GE2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
