DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/03/26 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 7, 9-11, 15-17, and 19, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bahl et al. (US Patent 9,922,951 hereinafter referred to as “Bahl”).
Bahl discloses the semiconductor device as claimed. See figures 3-4 and corresponding text, where Bahl teaches, claim 1, a semiconductor package, comprising:
a substrate (306) comprising a through hole (324) extending through the substrate (306); (figures 3A and 4; col. 5, lines 15-42, lines 51-67; col. 6, lines 1-28)
a semiconductor die (302) on the substrate (306), the semiconductor die (302) overlapping the through hole (324); (figures 3A and 4; col. 5, lines 15-42, lines 51-67; col. 6, lines 1-28) and
a conductive catalytic layer within the through hole (324) and on the semiconductor die (302); (figures 3A and 4; col. 5, lines 15-42, lines 51-67; col. 6, lines 1-28)
wherein the through hole (324) in the substrate (306) is at least partially filled with an electroless deposited portion initiated from the conductive catalytic layer (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 2, wherein an area of the through hole in a plane that is parallel to the semiconductor die is less than an area of the semiconductor die (figures 3A and 4; col. 5, lines 15-42, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 3, wherein the electroless deposited portion is coupled to the semiconductor die (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 4, wherein the electroless deposited portion comprises copper or nickel (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 6, wherein the electroless deposited portion comprises a first electroless deposited portion in the through hole and a second electroless deposited portion in the through hole (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 7, wherein the first electroless deposited portion comprises copper and the second electroless deposited portion comprises nickel (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 9, wherein the conductive catalytic layer comprises one or more of gold, palladium, nickel, or aluminum (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 10, wherein the conductive catalytic layer comprises one or more of a gold alloy, a palladium alloy, a nickel alloy, or an aluminum alloy (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 11, wherein the semiconductor package comprises a conductive adhesion layer between the conductive catalytic layer and the semiconductor die (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 12, wherein the conductive adhesion layer comprises titanium (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 13, further comprising a die-attach material between a peripheral portion of the semiconductor die and the substrate, wherein the die-attach material at least partially surrounds the through hole on a surface of the substrate. (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28)
Bahl teaches, claim 15, wherein the substrate comprises a first surface and an opposing second surface, the substrate comprising a recess in the first surface, the recess overlapping the through hole (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 16, wherein the semiconductor die is in the recess (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 17, wherein the substrate comprises a stepped surface in the recess, wherein a peripheral portion of the semiconductor die is on the stepped surface (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Bahl teaches, claim 19, wherein the substrate is a conductive substrate (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 22, 23 and 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bahl et al. (US Patent 9,922,951 hereinafter referred to as “Bahl”) as applied to claim 1 above, and further in view of Von Koblinski et al. (US PGPub 2015/0243591, hereinafter referred to as “Von Koblinski”).
Bahl discloses the semiconductor device substantially as claimed. See the rejection above.
However, Bahl fails to explicitly teach, in claim 22, wherein the semiconductor die comprises a wide band gap semiconductor.
Von Koblinski teaches a similar device that includes a semiconductor chip that has a wide band gap semiconductor that is well known in the art ([0022]). Specifically, for the operational purposes of higher voltages, frequencies, and temperatures. In addition, Von Koblinski provides the advantages of direct plating improves electrical and thermal contact between the metal structure and the semiconductor chip and eliminating thermal-mechanical stress ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the semiconductor die comprises a wide band gap semiconductor for the conventional purposes of operation at higher voltages, frequences and temperatures. In addition, it is advantages perform direct plating for the improvement of electrical and thermal contact between the metal structure and the semiconductor chip and eliminating thermal-mechanical stress.
However, Bahl fails to explicitly teach, in claim 23, wherein the semiconductor die comprises silicon carbide.
Von Koblinski teaches a similar device that includes a semiconductor die that includes silicon carbide that is well known in the art ([0022]). Specifically, for the operational purposes of higher voltages, frequencies, and temperatures. In addition, Von Koblinski provides the advantages of direct plating improves electrical and thermal contact between the metal structure and the semiconductor chip and eliminating thermal-mechanical stress ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the semiconductor die comprises silicon carbide for the conventional purposes of operation at higher voltages, frequences and temperatures. In addition, it is advantages perform direct plating for the improvement of electrical and thermal contact between the metal structure and the semiconductor chip and eliminating thermal-mechanical stress.
Bahl teaches, claim 42, a power semiconductor device, comprising:
a substrate (306) comprising a through hole (324); (figures 3A and 4; col. 5, lines 15-42, lines 51-67; col. 6, lines 1-28)
a semiconductor die (302) coupled to the substrate (306) with an electroless deposited portion that at least partially fills the through hole (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28); and
a conductive catalytic layer between the semiconductor die (302) and the electroless deposited portion, wherein the electroless deposited portion is initiated from the conductive catalytic layer (figures 3B and 4; col. 5, lines 43-50, lines 51-67; col. 6, lines 1-28).
However, Bahl fails to explicitly teach, in claim 42, wherein the semiconductor die comprises is a power semiconductor die; a wide band gap semiconductor.
Von Koblinski teaches a similar device that includes a semiconductor chip that has a wide band gap semiconductor that is well known in the art ([0022]). Specifically, for the operational purposes of higher voltages, frequencies, and temperatures. In addition, Von Koblinski provides the advantages of direct plating improves electrical and thermal contact between the metal structure and the semiconductor chip and eliminating thermal-mechanical stress ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the semiconductor die comprises is a power semiconductor die; a wide band gap semiconductor for the conventional purposes of operation at higher voltages, frequences and temperatures. In addition, it is advantages perform direct plating for the improvement of electrical and thermal contact between the metal structure and the semiconductor chip and eliminating thermal-mechanical stress.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 25, 2026
