DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 2/05/26. Claims 1-4, 6-13, 15-17, 19, 22, 23 and 42 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The rejection of claim(s) 1-4, 6-13, 15-17, 19, 22, 23 and 42 i under 35 U.S.C. 103 as being unpatentable over Von Koblinski et al. (US PGPub 2015/0243591, hereinafter referred to as “Von Koblinski”) in view of Tsai et al. (US PGPub 2011/0298126, hereinafter referred to as “Tsai”) has been maintained for reasons or record.
Von Koblinski discloses the semiconductor package substantially as claimed. See figures 1A-4B and corresponding text, where Von Koblinski shows, in claim 1, a semiconductor package, comprising:
a substrate (100) comprising a through hole (105) extending through the substrate (100) (figure 2A; [0047-0048]); and
a semiconductor die (200) on the substrate (100), the semiconductor die (200) overlapping the through hole (105) (figure 2D; [0061-0062]);
wherein the through hole (105) in the substrate (100) (figure 2D; [0062])
However, Von Koblinski fails to show, in claim 1, at least partially filled with an electroless deposited portion.
Tsai teaches, in claim 1, for a conductive layer within an opening formed by electroless plating (figure 4A and 4B; [0044-0045]). In addition, Tsai provides the advantages of having a plurality of conductive traces to be flexibly disposed to metal carrier to enhance the electrical connection quality of the semiconductor package ([0025]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of claimed invention, to incorporate fails to show is at least partially filled with an electroless deposited portion, in the device of Von Koblinski, according to the teachings of Tsai, with the motivation of having the conductive layer to be flexibly disposed to carrier to enhance the electrical connection quality of the semiconductor package.
Von Koblinski in view of Tsai shows, in claim 2, wherein an area of the through hole in a plane that is parallel to the semiconductor die is less than an area of the semiconductor die (figures 2B and 2C; [0059-0062]).
Von Koblinski in view of Tsai shows, in claim 3, wherein the electroless deposited portion is coupled to the semiconductor die (figure 4A and 4B; [0044-0045], Tsai electroless process).
Von Koblinski in view of Tsai shows, in claim 4, wherein the electroless deposited portion comprises copper or nickel (figure 4A and 4B; [0044-0045], Tsai electroless process; [0074-0078], Von Koblinski teaches copper and/or nickel).
Von Koblinski in view of Tsai shows, in claim 6, wherein the electroless deposited portion comprises a first electroless deposited portion in the through hole and a second electroless deposited portion in the through hole (figure 4A and 4B; [0044-0045], Tsai electroless process; [0074-0078], Von Koblinski teaches the two plating steps).
Von Koblinski in view of Tsai shows, in claim 7, wherein the first electroless deposited portion comprises copper and the second electroless deposited portion comprises nickel (figure 4A and 4B; [0044-0045], Tsai electroless process; [0074-0078], Von Koblinski teaches copper and/or nickel).
Von Koblinski in view of Tsai shows, in claim 8, wherein the semiconductor package comprises a conductive catalytic layer on the semiconductor die ([0078], seed layer)
Von Koblinski in view of Tsai shows, in claim 9, wherein the conductive catalytic layer comprises one or more of gold, palladium, nickel, or aluminum ([0076-0078]. Nickel).
Von Koblinski in view of Tsai shows, in claim 10, wherein the conductive catalytic layer comprises one or more of a gold alloy, a palladium alloy, a nickel alloy, or an aluminum alloy ([0060], gold alloy)
Von Koblinski in view of Tsai shows, in claim 11, wherein the semiconductor package comprises a conductive adhesion layer between the conductive catalytic layer and the semiconductor die ([0060]).
Von Koblinski in view of Tsai shows, in claim 12, wherein the conductive adhesion layer comprises titanium ([0060]).
Von Koblinski in view of Tsai shows, in claim 13, further comprising a die-attach material (130) between a peripheral portion of the semiconductor die and the substrate, wherein the die-attach material at least partially surrounds the through hole on a surface of the substrate (figures 2F and 2G; [0065-0069])
Von Koblinski in view of Tsai shows, in claim 15, wherein the substrate comprises a first surface and an opposing second surface, the substrate comprising a recess (103) in the first surface, the recess overlapping the through hole (105) (figure 2C; [0059])
Von Koblinski in view of Tsai shows, in claim 16, wherein the semiconductor die is in the recess (figure 1C; [0021]).
Von Koblinski in view of Tsai shows, in claim 17, wherein the substrate comprises a stepped surface in the recess, wherein a peripheral portion of the semiconductor die is on the stepped surface (figure 1C; [0021]).
Von Koblinski in view of Tsai shows, in claim 19, wherein the substrate is a conductive substrate ([0019-0022]).
Von Koblinski in view of Tsai shows, in claim 22, wherein the semiconductor die comprises a wide band gap semiconductor ([0022]).
Von Koblinski in view of Tsai shows, in claim 23, wherein the semiconductor die comprises silicon carbide (figure 1C; [0022]).
Von Koblinski in view of Tsai shows, in claim 42, a power semiconductor device, comprising:
a substrate (100); and
a power semiconductor die (200) comprising a wide band gap semiconductor, the power semiconductor die coupled to the substrate (figure 1B-1D; [0018-0023]).
However, Von Koblinski fails to show an electroless deposited portion.
Tsai teaches, in claim 42, for a conductive layer within an opening formed by electroless plating (figure 4A and 4B; [0044-0045]). In addition, Tsai provides the advantages of having a plurality of conductive traces to be flexibly disposed to metal carrier to enhance the electrical connection quality of the semiconductor package ([0025]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of claimed invention, to incorporate fails to show is at least partially filled with an electroless deposited portion, in the device of Von Koblinski, according to the teachings of Tsai, with the motivation of having the conductive layer to be flexibly disposed to carrier to enhance the electrical connection quality of the semiconductor package.
Response to Arguments
Applicant's arguments filed 2/05/26 have been fully considered but they are not persuasive. In the remarks applicant raises the clear issue as to whether Tsai alone or in combination with Von Koblinski suggests or renders obvious wherein the through hole in the substrate is at least partially filled with an electroless deposited portion.
The examiner views that the combination of Tsai in view of Von Koblinski does suggest the claimed invention. Specifically, Von Koblinski teaches a substrate (100) that includes an opening (105) (implied through hole) where as “conductive seed layer (120)” of Fig. 2C, at least partially filling the “receptable (105)” prior to placing the “semiconductor chip (200)” in Fig. 2D,(paragraphs [0059-0062]). However, Von Koblinski only fails to teach filling the opening with a electroless plating processing. Tsai teaches the process of forming the seed layer of Von Koblinski, by performing a conventional electroless process to enhance the electrical connection quality of the semiconductor package, by known properties such as improved coating uniformity, enhanced corrosion and wear resistance.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 May 29, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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