DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/08/2026 has been entered.
Response to Amendment
The Amendment filed on 03/30/2026 has been entered. Claims 1-8, 10-15, 17, 21-24 and newly added claim 25, remain pending in the application. Claims 9, 16, 18-20 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hawk et al., (United States Patent Application Publication Number, US 2014/0131854 A1), hereinafter referenced as Hawk, in view of Yu et al., (United States Patent Number, US 10,153,222 B2), hereinafter referenced as Yu, and in view of Mahajan et al., (United States Patent Number, US 9,275,955 B2), hereinafter referenced as Mahajan.
Regarding claim 1, Hawk teaches a semiconductor package, comprising: a first semiconductor die and a second semiconductor die disposed adjacent one another (Fig.4, elements #110 and #410), on a substrate (Fig.4, element #405).
Hawk does not teach the first semiconductor die and the second semiconductor die are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction different from the first direction, wherein the first scribe line and the second scribe line are both between the first semiconductor die and the second semiconductor die. Yu teaches a first semiconductor die and a second semiconductor die (Fig.13, elements #68 in the upper left and bottom right corners) separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction different from the first direction, wherein the first scribe line and the second scribe line are both between the first semiconductor die and the second semiconductor die (Fig 13, elements #94, vertical and horizontal scribe lines). ). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. As disclosed by Yu, the scribe lines can be used as a reference for placing the dies on a substrate so that they match preexisting circuit patterns of the substrate.
Hawk further teaches a semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die (Fig.4C, bridging block in the center of the figure). As noted above, Yu teaches the scribe lines are located in the space separating the dies, and therefore the combination of Hawk and Yu teaches the semiconductor bridge overlaying the first scribe line or the second scribe line.
Hawk further teaches wherein the semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die (Fig.4, the runner #210 connecting the four interior corners of the bridging block contacts electrically couples the dies).
Hawk further teaches the first and the semiconductor dies have electrical contacts that allows them to be connected to other dies or substrates (Fig.4, elements #115b and #410a). The combination of Hawk and Yu does not teach and a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively, wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die. Mahajan teaches a third semiconductor die (Fig.6, element #620) and a fourth semiconductor die (Fig.6, element #622) electrically coupled to the first semiconductor die and the second semiconductor die respectively, (Fig.6, third die, element #620, is electrically coupled to the first die, element #608, and the fourth die, element #622 is electrically coupled to the second die, element #610), wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die (Fig.6, bridge #614 is interposed between elements #620 and #622). Mahajan doesn’t specifically teach the first and second semiconductor dies, elements #608 and #610, are placed on the substrate diagonally, as disclosed by Hawk. However, one of ordinary skilled in the art, would recognize that the third and fourth dies disclosed by Mahajan could be connected to the contacts of the first and second dies as disclosed by Hawk. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mahajan and disclose a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively, wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die. Stacking the dies on top of each other and interposing the bridge between the dies, allows for a reduced footprint of the package in the horizontal plane.
Regarding claim 3, the combination of Hawk, Yu and Mahajan teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Mahajan further teaches the semiconductor package of claim 1, wherein the semiconductor bridge is laterally separated from the third semiconductor die and the fourth semiconductor die by a gap-fill layer (Fig.6, element #626). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mahajan and disclose wherein the semiconductor bridge is laterally separated from the third semiconductor die and the fourth semiconductor die by a gap-fill layer. The gap-fill layer protects the dies and the bridge from environmental factors such as moisture and improves the mechanical stability of the dies inside the package.
Regarding claim 24, the combination of Hawk, Yu and Mahajan teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Mahajan further teaches the semiconductor package of claim 1, wherein the third semiconductor die is stacked along a third direction over the first semiconductor die (Fig.6, element #620 is stacked on the first die, element #608 in the vertical direction) and the fourth semiconductor die is stacked along the third direction over the second semiconductor die (Fig.6, element #622 is stacked on the first die, element #610 in the vertical direction), wherein the third direction is perpendicular to the first direction and the second direction (the vertical direction in Fig.6 is perpendicular to the horizontal plane/substrate, where the first and second directions reside), and wherein the semiconductor bridge is interposed in a space extending along the third direction separating the third semiconductor die and the fourth semiconductor die (Fig.6, element #614 extends in the vertical direction, between the third and fourth die). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Mahajan and disclose wherein the third semiconductor die is stacked along a third direction over the first semiconductor die, and the fourth semiconductor die is stacked along the third direction over the second semiconductor die, wherein the third direction is perpendicular to the first direction and the second direction, and wherein the semiconductor bridge is interposed in a space extending along the third direction separating the third semiconductor die and the fourth semiconductor die. Stacking the dies on top of each other and interposing the bridge between the dies, allows for a reduced footprint of the package in the horizontal plane.
Regarding claim 25, the combination of Hawk, Yu and Mahajan teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The semiconductor package of claim 1, wherein the first direction is perpendicular to the second direction (Fig.13, elements #94 extent in the vertical and horizontal directions, respectively).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hawk, Yu and Mahajan, in view of Jun et al., (United States Patent Application Publication Number, US 2022/0415837 A1) hereinafter referenced as Jun.
Regarding claim 2, the combination of Hawk, Yu and Mahajan teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Mahajan further teaches the semiconductor package of claim 1, wherein the first semiconductor die and the third semiconductor die are coupled using a first set of interconnects and the second semiconductor die and the fourth semiconductor die are coupled using a second set of interconnects (Fig.6, elements #604 on top of elements #608 and #610).
The combination of Hawk, Yu and Mahajan does not teach the first semiconductor die and the third semiconductor die are coupled at a first bonding interface layer, and the second semiconductor die and the fourth semiconductor die are coupled at a second bonding interface layer. Jun teaches wherein the first semiconductor die (Fig.3H, element #370d) and the third semiconductor die (Fig.3H, element #370a) are coupled at a first bonding interface layer (Fig.3H, element #371d), and the second semiconductor die (Fig.3H, element #370e) and the fourth semiconductor die (Fig.3H, element #370c) are coupled at a second bonding interface layer (Fig.3H, element #377e). Thus, both references, Mahajan and Jun teach dies coupled together thought different connecting elements. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the interconnects disclosed by Gomes could have been replaced for the bonding interface layer disclosed by Jun because both serve the same purpose of providing an electrical connection between the dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the dies. The bonding interface layer allows for smaller connection pitches, and therefore more compact designs.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hawk in view of Yu, Mahajan, in view of Wang et al., (United States Patent Application Publication Number, US 2016/0071818 A1), hereinafter referenced as Wang and in view of Enquist et al., (United States Patent Application Publication Number, US 2019/0355706 A1), hereinafter referenced as Enquist.
Regarding claim 8, the combination of Hawk, Yu and Mahajan teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Hawk, Yu and Mahajan does not teach the semiconductor package of claim 1, further comprising a first redistribution structure disposed on a back side of the first semiconductor die and a second redistribution structure disposed on a back side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure.
Wang teaches a first semiconductor dies (Fig.6A, element #110F.1 on the top left corner) a second semiconductor die (Fig.6A, element #110F.1 on the top right corner) a third semiconductor die (Fig.6A, element #110F.1 on the bottom right corner) and a fourth semiconductor die (Fig.6A, element #110F.1 on the bottom left corner), where the third semiconductor die is electrically coupled to the second semiconductor die via a connecting structure (Fig.6A, element#350 located below the second semiconductor die, and paragraph [0100], rows 5-9) and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second structure (Fig.6A, element#350 located below the first semiconductor die, and paragraph [0100], rows 5-9). In a different embodiment, Wang teaches a semiconductor package further comprising a first redistribution structure disposed on the bottom side of the first semiconductor die (Fig.9E, element #890 disposed under element #110F.1) and a second redistribution structure disposed on a bottom side the second semiconductor die (Fig.9E, element #890 disposed under element #110F.2), wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features (Fig.9E, elements #890 include conductive features #894 and #902). Thus, in two different embodiments Wang teaches two different types of connections between dies. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the structure #350 disclosed in Figure 6A could have been replaced by the redistribution layer, element #890 of Figure 9E, because both serve the same purpose of providing an electrical connection between the dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the dies. The redistribution layer provides better flexibility, an efficient signal routing and can accommodate complex electrical connections.
Thus, Wang teaches a first redistribution structure disposed on a bottom side of the first semiconductor die and a second redistribution structure disposed on a bottom side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wang and disclose redistribution structures disposed on a bottom side of the first and second semiconductor dies, including a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. The redistribution structures allow direct connections between parts of the dies that the bridge cannot reach due to design constraints.
The combination of Hawk, Yu, Mahajan and Wang does not teach that the redistribution structures are disposed on back side of the dies. Enquist teaches redistribution structures disposed on back side of the dies (Fig.3, element #310, paragraph [0046], rows 3-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Enquist and disclose redistribution structures disposed on back sides of die. Disposing the redistribution structures on the back side of dies facilitates integration of multiple devices and offers design flexibility.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hawk in view of Yu and in view of Elsherbini et al., (United States Patent Application Publication Number, US 2019/0385977 A1), hereinafter referenced as Elsherbini_977.
Regarding claim 1, Hawk teaches a semiconductor package, comprising: a first semiconductor die and a second semiconductor die disposed adjacent one another (Fig.4, elements #110 and #410), on a substrate (Fig.4, element #405).
Hawk does not teach the first semiconductor die and the second semiconductor die are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction different from the first direction, wherein the first scribe line and the second scribe line are both between the first semiconductor die and the second semiconductor die. Yu teaches a first semiconductor die and a second semiconductor die (Fig.13, elements #68 in the upper left and bottom right corners) separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction different from the first direction, wherein the first scribe line and the second scribe line are both between the first semiconductor die and the second semiconductor die (Fig 13, elements #94, vertical and horizontal scribe lines). ). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. As disclosed by Yu, the scribe lines can be used as a reference for placing the dies on a substrate so that they match preexisting circuit patterns of the substrate.
Hawk further teaches a semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die (Fig.4C, bridging block in the center of the figure). As noted above, Yu teaches the scribe lines are located in the space separating the dies, and therefore the combination of Hawk and Yu teaches the semiconductor bridge overlaying the first scribe line or the second scribe line.
Hawk further teaches wherein the semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die (Fig.4, the runner #210 connecting the four interior corners of the bridging block contacts electrically couples the dies).
Hawk further teaches the first and the semiconductor dies have electrical contacts that allows them to be connected to other dies or substrates (Fig.4, elements #115b and #410a). The combination of Hawk and Yu does not teach and a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively, wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die. Elsherbini_977 teaches a third semiconductor die (Fig.1A, element #114-3) and a fourth semiconductor die (Fig.1A, element #114-5) electrically coupled to the first semiconductor die and the second semiconductor die, respectively (Fig.1A, first die, element #114-1 is electrically coupled to the third die, element #114-3 through at least one element #152 located between the two dies, and second die, element #114-5 is electrically coupled with fourth die, element #114-5, through at least element #152 located between the two dies), wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die (Fig.2A, element #114-2 is interposed between elements #114-3 and #114-5 from top view). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Elsherbini_977 and disclose a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively, wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die. Stacking the dies on multiple levels along the vertical direction and interposing the bridge between the dies, as disclosed by Elsherbini_977, allows for a reduced footprint of the package in the horizontal plane.
Regarding claim 4, the combination of Hawk, Yu and Elsherbini_977 teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Elsherbini_977 further teaches the semiconductor package of claim 1, wherein the third semiconductor die and the fourth semiconductor die are disposed over and overlap with corners of the semiconductor bridge (Fig.2A, elements #114C, equivalent with elements #114-3 and #114-5 in Fig.1A are disposed over and overlap with the corners of the bridge, element #114B, equivalent with element #114-2 in Fig.3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Elsherbini_977 and disclose wherein the third semiconductor die and the fourth semiconductor die are disposed over and overlap with corners of the semiconductor bridge. Disposing the dies overlapping and over the corners of the bridge, provides the largest separation between the dies which allows connecting large dies to the bridge.
Allowable Subject Matter
Claims 5 and 6 are allowed if written in independent form. Claim 7 is allowed as
being dependent on claim 6. Claims 10 and 21 are allowed. Claims 11-15 and 17 are allowed as being dependent on claim 10. Claims 22 and 23 are allowed as being dependent on claim 21.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 5, the cited prior art does not teach or fairly suggests, along with other
claimed features: “fifth semiconductor die vertically sandwiched between the first semiconductor die and the third semiconductor die and a sixth semiconductor die vertically sandwiched between the second semiconductor die and the fourth semiconductor die, wherein the semiconductor bridge is interposed between the fifth semiconductor die and the sixth semiconductor die.” Elsherbini_977 teaches a fifth semiconductor die (Fig.3, element #114-3) vertically sandwiched between the first semiconductor die (Fig.3, element #114-1) and the third semiconductor die (Fig.3, element #114-7) and a sixth semiconductor die (Fig.3, element #114-5) vertically sandwiched between the second semiconductor die (Fig.3, element #114-4) and the fourth semiconductor die (Fig.3, element #114-9), wherein the semiconductor bridge (Fig.3, element #114-2) is interposed between the fifth semiconductor die and the sixth semiconductor die (Fig.3, element #114-2 is interposed between element #114-3 and #114-5). However, Elsherbini_977 this is not consistent with the limitation of claim 1, which requires the third semiconductor die to be electrically coupled to the first semiconductor die (element #114-7 is not electrically coupled to element #114-1).
Regarding claim 6, the cited prior art does not teach or fairly suggests, along with other
claimed features: “wherein the semiconductor bridge includes a first via and a second via extending through a substrate of the semiconductor bridge”. Hawk teaches against a bridge that includes vias (paragraph [0012]).
Regarding claim 10, the cited prior art does not teach or fairly suggests, along with other
claimed features: “wherein the semiconductor bridge includes a first via electrically coupled to the first semiconductor die and a second via electrically coupled to the second semiconductor die, the first via and the second via extending through a substrate of the semiconductor bridge”. Hawk teaches against a bridge that includes vias (paragraph [0012]).
Regarding claim 21, the cited prior art does not teach or fairly suggests, along with other
claimed features: “and a third semiconductor die and a fourth semiconductor die disposed over and electrically coupled to the semiconductor bridge”. Elsherbini_977 teaches and a third semiconductor die (Fig.3, element #114-3), and a fourth semiconductor die (Fig.3, element #114-5), disposed over and electrically coupled to the semiconductor bridge (Fig.3, element #114-2). However, Hawk teaches a bridge that has connections on only one side and therefore cannot be electrically connected to a third and fourth die disposed over the bridge.
Response to Arguments
Applicant’s arguments filed on 03/30/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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