DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 11/19/2025 has been entered. Claims 1-8, 10-17, 21-23 and newly added claim 24, remain pending in the application. Claims 9 and 18-20 have been canceled. Applicant’s amendments have overcome to objection to claim 7, the 112(a) rejection of claims 16 and 23, and the 112(b) rejection of claim 15 as previously set forth in the Non-Final Office Action mailed on 08/20/2025.
Corrected drawings were submitted on 01/12/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al., (United States Patent Application Publication Number US 2020/0211970 A1) hereinafter referenced as Gomes, in view of Yu et al., (United States Patent Number, US 10,153,222 B2), hereinafter referenced as Yu and in view of Hawk et al., (United States Patent Application Publication Number, US 2014/0131854 A1), hereinafter referenced as Hawk.
Regarding claim 1, Gomez teaches a semiconductor package, comprising: a first semiconductor die and a second semiconductor die disposed adjacent one another (Fig.4C, elements #421a and #421b) a semiconductor bridge (Fig.4B, element #433, paragraph [0035], rows 12-14).
Gomes teaches dies separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction (Fig.4A, scribe lines element #405). Gomes does not teach the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. Yu teaches the first and the second semiconductor dies (Fig.8, elements #92 and #90) are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction (Fig 13, element #94) wherein both the first scribe line and the second scribe line are filled with a gap-fill layer (Fig.8, element #112, column 10, rows 3-18 fills the space between the dies and the scribe lines). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. As disclosed by Yu, the scribe lines can be used as a reference for placing the dies on a substrate so that they match preexisting circuit patterns of the substrate. Filling the scribe lines and the space between the dies with a gap-fill layer increases the mechanical integrity of the semiconductor package.
Gomes teaches the semiconductor bridge overlaying a space separating the first and second die (Fig. 4C, the bridge element #433 overlays the space between the dies). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore the combination of Yu and Gomes teaches the semiconductor bridge overlaying the first scribe line or the second scribe line. The combination of Gomes and Yu does not teach the semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. Hawk teaches a bridge overlaying the intersection between the lines separating the chips (Fig.4, element #125 overlays the intersection between the lines separating the chip), and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die (Fig.4, element #125 overlaps a first corner of the first semiconductor die, element #110, and a second corner of the second semiconductor die, element #105). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore the combination of Yu and Hawk teaches the bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and Hawk and disclose a semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. As disclosed by Hawk, this allows the bridge to electrically connect the corners of all the dies separated by the intersection of the two scribe lines (Fig.4).
Gomes further teaches wherein the semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die (Fig.4C, element #433); and a third semiconductor die (Fig.4C, element #423a) and a fourth semiconductor die (Fig.4C, element #423b) electrically coupled to the first semiconductor die (Fig.4C, first die, element #421 is electrically coupled with third die, element #432a through element #425a) and the second semiconductor die (Fig.4C, second die, element #421b is electrically coupled with fourth die, element #432b, through element #425b), respectively, wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die (Fig.4C, element #433 is interposed between elements #432a and 423b).
Regarding claim 24, the combination of Gomes, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Gomes further teaches the semiconductor package of claim 1, wherein the third semiconductor die is stacked along a third direction over the first semiconductor die (Fig.4C, third die, element #423a is stacked along the vertical direction over the first die, element #421a), and the fourth semiconductor die is stacked along the third direction over the second semiconductor die (Fig.4C, fourth die, element #423b is stacked along the vertical direction over the second die, element #421b), wherein the third direction is perpendicular to the first direction and the second direction (third direction is perpendicular to the first and second directions which are in the horizontal plane), and wherein the semiconductor bridge is interposed in a space extending along the third direction separating the third semiconductor die and the fourth semiconductor die (Fig.4C, element #433 extends vertically and separates elements #432a and #423b).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes, Yu and Hawk, in view of Jun et al., (United States Patent Application Publication Number, US 2022/0415837 A1) hereinafter referenced as Jun.
Regarding claim 2, the combination of Gomes, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the anticipation rejection. Gomes further teaches the semiconductor package of claim 1, wherein the first semiconductor die and the third semiconductor die are coupled through a set of die interconnects (Fig.4C, first die, element #421 is electrically coupled with third die, element #432a through element #425a), and the second semiconductor die and the fourth semiconductor die are coupled through another set of interconnects (Fig.4C, second die, element #421b is electrically coupled with fourth die, element #432b, through element #425b). The combination of Gomes, Yu and Hawk does not teach wherein the first semiconductor die and the third semiconductor die are coupled at a first bonding interface layer, and the second semiconductor die and the fourth semiconductor die are coupled at a second bonding interface layer. Jun teaches wherein the first semiconductor die (Fig.3H, element #370d) and the third semiconductor die (Fig.3H, element #370a) are coupled at a first bonding interface layer (Fig.3H, element #371d), and the second semiconductor die (Fig.3H, element #370e) and the fourth semiconductor die (Fig.3H, element #370c) are coupled at a second bonding interface layer (Fig.3H, element #377e). Thus, both references, Gomes and Jun teach dies coupled together thought different connecting elements. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the interconnects disclosed by Gomes could have been replaced for the bonding interface layer disclosed by Jun because both serve the same purpose of providing an electrical connection between the dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the dies. The bonding interface layer allows for smaller connection pitches, and therefore more compact designs.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes in view of Yu, Hawk and in view of Elsherbini et al., (United States Patent Application Publication Number, US 2021/0111124 A1), hereinafter referenced as Elsherbini_124.
Regarding claim 3, the combination of Gomes, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Gomes further teaches wherein the semiconductor bridge is laterally separated from the third semiconductor die and the fourth semiconductor die (Fig. 4C, element #433 is laterally separated from elements #432a and #423b). the combination of Gomes, Yu and Hawk does not teach the semiconductor package of claim 1, wherein the semiconductor bridge is laterally separated from the third semiconductor die and the fourth semiconductor die by a gap-fill layer. Elsherbini_124 teaches semiconductor dies interposed between other dies that are laterally separated from one another by a gap-fill layer (Fig.19F, the dies are separated by layer, element #127). Elsherbini_124 also teaches that dies can be bridges (paragraph [0120], rows 1-3). Therefore, Elsherbini_124 teaches wherein the semiconductor bridge is laterally separated from the third semiconductor die and the fourth semiconductor die by a gap-fill layer. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Elsherbini_124 and disclose wherein the semiconductor bridge is laterally separated from the third semiconductor die and the fourth semiconductor die by a gap-fill layer. The gap-fill layer protects the dies and the bridge from environmental factors such as moisture and improves the mechanical stability of the dies inside the package.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes in view of Yu, Hawk and in view of Elsherbini et al., (United States Patent Application Publication Number, US 2019/0385977 A1), hereinafter referenced as Elsherbini_977.
Regarding claim 4, the combination of Gomes, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Gomes, Yu and Hawk does not teach the semiconductor package of claim 1, wherein the third semiconductor die and the fourth semiconductor die are disposed over and overlap with corners of the semiconductor bridge. Elsherbini_977 teaches wherein the third semiconductor die and the fourth semiconductor die are disposed over and overlap with corners of the semiconductor bridge (Fig.2A, elements 114C, equivalent with elements #114-7 and #114-9 in Fig.3 are disposed over and overlap with the corners of the bridge, element #114B, equivalent with element #114-2 in Fig.3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Elsherbini_977 and disclose wherein the third semiconductor die and the fourth semiconductor die are disposed over and overlap with corners of the semiconductor bridge. Disposing the dies overlapping and over the corners of the bridge, provides the largest separation between the dies which allows connecting large dies to the bridge.
Regarding claim 5, the combination of Gomes, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the obviousness rejection and the combination of Gomes, Yu, Hawk and Elsherbini_977 teaches the semiconductor package of claim 4 as set forth in the obviousness rejection. The combination of Gomes, Yu and Hawk does not teach the semiconductor package of claim 4, further comprising a fifth semiconductor die vertically sandwiched between the first semiconductor die and the third semiconductor die and a sixth semiconductor die vertically sandwiched between the second semiconductor die and the fourth semiconductor die, wherein the semiconductor bridge is interposed between the fifth semiconductor die and the sixth semiconductor die. Elsherbini_977 teaches a fifth semiconductor die (Fig.3, element #114-3) vertically sandwiched between the first semiconductor die (Fig.3, element #114-1) and the third semiconductor die (Fig.3, element #114-7) and a sixth semiconductor die (Fig.3, element #114-5) vertically sandwiched between the second semiconductor die (Fig.3, element #114-4) and the fourth semiconductor die (Fig.3, element #114-9), wherein the semiconductor bridge (Fig.3, element #114-2) is interposed between the fifth semiconductor die and the sixth semiconductor die (Fig.3, element #114-2 is interposed between element #114-3 and #114-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Elsherbini_977 and disclose a fifth semiconductor die vertically sandwiched between the first semiconductor die and the third semiconductor die and a sixth semiconductor die vertically sandwiched between the second semiconductor die and the fourth semiconductor die, wherein the semiconductor bridge is interposed between the fifth semiconductor die and the sixth semiconductor die. As disclosed by Elsherbini_977, this may help lower cost, improve power delivery and signal speed while reducing the size of the package (paragraph [0018], rows 5-15).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini_977, in view of Yu and in view of Hawk.
Regarding claim 1, Elsherbini_977 teaches a semiconductor package, comprising: a first semiconductor die and a second semiconductor die disposed adjacent one another (Fig.1A, elements #114-1 and #114-4).
Elsherbini_977 teaches a gap fill material between the first and second die (Fig.4C, element #430 also shown in Fig.1A but not numbered). Elsherbini_977 does not teach the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. Yu teaches the first and the second semiconductor dies (Fig.8, elements #92 and #90) are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction (Fig 13, element #94) wherein both the first scribe line and the second scribe line are filled with a gap-fill layer (Fig.8, element #112, column 10, rows 3-18 fills the space between the dies and the scribe lines). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. As disclosed by Yu, the scribe lines can be used as a reference for placing the dies on a substrate so that they match preexisting circuit patterns of the substrate. Filling the scribe lines and the space between the dies with a gap-fill layer increases the mechanical integrity of the semiconductor package.
Elsherbini_977 further teaches a semiconductor bridge (Fig.1A, element #114-2, paragraph [0078], rows 1-4) overlaying a space separating the first and second die (Fig.1A, the bridge element #114-2 overlays a space between the dies). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore, the combination of Elsherbini_977 and Yu teaches the semiconductor bridge overlaying the first scribe line or the second scribe line. The combination of Elsherbini_977 and Yu does not teach the semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. Hawk teaches a bridge overlaying the intersection between the lines separating the chips (Fig.4, element #125 overlays the intersection between the lines separating the chip), and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die (Fig.4, element #125 overlaps a first corner of the first semiconductor die, element #110, and a second corner of the second semiconductor die, element #105). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore the combination of Yu and Hawk teaches the bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and Hawk and disclose a semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. As disclosed by Hawk, this allows the bridge to electrically connect the corners of all the dies separated by the intersection of the two scribe lines (Fig.4).
Elsherbini_977 further teaches wherein the semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die (paragraph [0078], rows 1-4); and a third semiconductor die (Fig.1A, element #114-3) and a fourth semiconductor die (Fig.1A, element #114-5) electrically coupled to the first semiconductor die (Fig.1A, first die, element #114-1 is electrically coupled with third die, element #114-3 through at least elements #152) and the second semiconductor die (Fig.1A, second die, element #114-4 is electrically coupled with fourth die, element #114-5, through at least element #152 at the right side of the figure), respectively, wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die (Fig.1A, element #114-2 is interposed between elements #114-3 and #114-5 from top view).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini_977 in view of Yu, Hawk and in view of Cheah et al., (United States Patent Application Publication Number, US 2023/0065380 A1), hereinafter referenced as Cheah.
Regarding claim 6, the combination of Elsherbini_977, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Elsherbini_977, Yu and Hawk does not teach the semiconductor package of claim 1, wherein the semiconductor bridge includes a first via and a second via extending through a substrate of the semiconductor bridge. Cheah teaches wherein the semiconductor bridge includes a first via and a second via extending through a substrate of the semiconductor bridge (Fig.4, elements #405 and #406, filled with metal, paragraph [0058], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose the semiconductor bridge includes a first via and a second via extending through a substrate of the semiconductor bridge. As disclosed by Cheah, the vias allow direct electrical connections between dies located at opposite sides of the bridge.
Regarding claim 7, the combination of Elsherbini_977, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the obviousness rejection and the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 6 as set forth in the obviousness rejection. Cheah further teaches the semiconductor package of claim 6, wherein the first semiconductor die (Fig.4, first semiconductor die, element #420 equivalent with element #120 in Fig.1) and the third semiconductor die (Fig.4, third semiconductor die, element #422 equivalent with element #122 in Fig.1) are coupled through the first via (Fig.4, shows element #420 and element #422 are coupled through element #405) and the second semiconductor die (Fig.4, second semiconductor die, element #421 equivalent with element #121 in Fig.1) and the fourth semiconductor die (Fig.4, fourth semiconductor die, element #423 equivalent with element #123 in Fig.1) are coupled through the second via (Fig.4, shows element #421 and element #423 are coupled through element #406). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose the semiconductor package wherein the first semiconductor die and the third semiconductor die are coupled through the first via and the second semiconductor die and the fourth semiconductor die are coupled through the second via. The vias provide the shortest path for electrical connections between dies located at opposite sides of the bridge, which can improve high-speed data transfer between the dies and increase power efficiency.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini_977 in view of Yu, Hawk, in view of Wang et al., (United States Patent Application Publication Number, US 2016/0071818 A1), hereinafter referenced as Wang and in view of Enquist et al., (United States Patent Application Publication Number, US 2019/0355706 A1), hereinafter referenced as Enquist.
Regarding claim 8, the combination of Elsherbini_977, Yu and Hawk teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Elsherbini_977, Yu and Hawk does not teach the semiconductor package of claim 1, further comprising a first redistribution structure disposed on a back side of the first semiconductor die and a second redistribution structure disposed on a back side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure.
Wang teaches a first semiconductor dies (Fig.6A, element #110F.1 on the top left corner) a second semiconductor die (Fig.6A, element #110F.1 on the top right corner) a third semiconductor die (Fig.6A, element #110F.1 on the bottom right corner) and a fourth semiconductor die (Fig.6A, element #110F.1 on the bottom left corner), where the third semiconductor die is electrically coupled to the second semiconductor die via a connecting structure (Fig.6A, element#350 located below the second semiconductor die, and paragraph [0100], rows 5-9) and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second structure (Fig.6A, element#350 located below the first semiconductor die, and paragraph [0100], rows 5-9). In a different embodiment, Wang teaches a semiconductor package further comprising a first redistribution structure disposed on the bottom side of the first semiconductor die (Fig.9E, element #890 disposed under element #110F.1) and a second redistribution structure disposed on a bottom side the second semiconductor die (Fig.9E, element #890 disposed under element #110F.2), wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features (Fig.9E, elements #890 include conductive features #894 and #902). Thus, in two different embodiments Wang teaches two different types of connections between dies. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the structure #350 disclosed in Figure 6A could have been replaced by the redistribution layer, element #890 of Figure 9E, because both serve the same purpose of providing an electrical connection between the dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the dies. The redistribution layer provides better flexibility, an efficient signal routing and can accommodate complex electrical connections.
Thus, Wang teaches a first redistribution structure disposed on a bottom side of the first semiconductor die and a second redistribution structure disposed on a bottom side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wang and disclose redistribution structures disposed on a bottom side of the first and second semiconductor dies, including a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. The redistribution structures allow direct connections between parts of the dies that the bridge cannot reach due to design constraints.
The combination of Elsherbini_977, Yu, Hawk and Wang does not teach that the redistribution structures are disposed on back side of the dies. Enquist teaches redistribution structures disposed on back side of the dies (Fig.3, element #310, paragraph [0046], rows 3-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Enquist and disclose redistribution structures disposed on back sides of die. Disposing the redistribution structures on the back side of dies facilitates integration of multiple devices and offers design flexibility.
Claims 10, 11, 14, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini_977 in view of Yu, Hawk, and Cheah.
Regarding claim 10, Elsherbini_977 teaches a semiconductor package, comprising: a first semiconductor die and a second semiconductor die disposed adjacent one another (Fig.1A, elements #114-1 and #114-4); a semiconductor bridge (Fig.1A, element #114-2, paragraph [0078], rows 1-4), wherein the semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die (paragraph [0078], rows 1-4).
Elsherbini_977 teaches a gap fill materials between the first and second die (Fig.4C, element #430 also shown in Fig.1A but not numbered). Elsherbini_977 does not teach the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. Yu teaches the first and the second semiconductor dies (Fig.8, elements #92 and #90) are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction (Fig 13, element #94) wherein both the first scribe line and the second scribe line are filled with a gap-fill layer (Fig.8, element #112, column 10, rows 3-18 fills the space between the dies and the scribe lines). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. As disclosed by Yu, the scribe lines can be used as a reference for placing the dies on a substrate so that they match preexisting circuit patterns of the substrate. Filling the scribe lines and the space between the dies with a gap-fill layer increases the mechanical integrity of the semiconductor package.
Elsherbini_977 teaches the semiconductor bridge overlaying a space separating the first and second die (Fig.1A, the bridge element #114-2 overlays the space between the dies). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore the combination of Elsherbini_977 and Yu teaches the semiconductor bridge overlaying the first scribe line or the second scribe line. The combination of Elsherbini_977 and Yu does not teach the semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. Hawk teaches a bridge overlaying the intersection between the lines separating the chips (Fig.4, element #125 overlays the intersection between the lines separating the chip), and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die (Fig.4, element #125 overlaps a first corner of the first semiconductor die, element #110, and a second corner of the second semiconductor die, element #105). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore, the combination of Yu and Hawk teaches the bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and Hawk and disclose a semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. As disclosed by Hawk, this allows the bridge to electrically connect the corners of all the dies separated by the intersection of the two scribe lines (Fig.4).
The combination of Elsherbini_977, Yu and Hawk does not teach wherein the semiconductor bridge includes a first via electrically coupled to the first semiconductor die and a second via electrically coupled to the second semiconductor die, the first via and the second via extending through a substrate of the semiconductor bridge. Cheah teaches and wherein the semiconductor bridge (Fig.4, bridge element #402) includes a first via (Fig.4 vias, element #405) electrically coupled to the first semiconductor die (Fig.4 via, elements #405, paragraph [0058], rows 1-4, is electrically coupled to the first die, element #420) and a second via (Fig.4 via, element #406) electrically coupled to the second semiconductor die (Fig.4 via, element #406, paragraph [0058], rows 1-4, is electrically coupled to the second die, element #421), the first via and the second via extending through a substrate of the semiconductor bridge (Fig.4 via, element #406, extend through the bridge element #402). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose wherein the semiconductor bridge includes a first via electrically coupled to the first semiconductor die and a second via electrically coupled to the second semiconductor die, the first via and the second via extending through a substrate of the semiconductor bridge. As disclosed by Cheah, the vias allow direct electrical connections between dies located at opposite sides of the bridge.
Elsherbini_977 further teaches a third semiconductor die (Fig.1A, element #114-3) and a fourth semiconductor die (Fig.1A, element #114-5) disposed over and electrically coupled to the semiconductor bridge (Fig.1A, elements #114-3 and #114-5 are electrically coupled to the bridge, element #114-2), wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die (Fig.1A, element #114-2 is interposed between elements #114-3 and #114-5 from top view), wherein the third semiconductor die is electrically coupled to the first semiconductor die, and wherein the fourth semiconductor die is electrically coupled to the second semiconductor die. (Fig.1A, second die, element #114-4 is electrically coupled with fourth die, element #114-5, through at least element #152). The combination of Elsherbini_977, Yu, Hawk does not teach that electrical coupling between the first and third semiconductor die is through the first via and electrical coupling between the second and fourth semiconductor die is through the second via. Cheah teaches wherein the third semiconductor die is electrically coupled to the first semiconductor die through the first via (Fig.4, shows first die, element #420 and third die element #422 coupled through first via, element #405), and wherein the fourth semiconductor die is electrically coupled to the second semiconductor die through the second via (Fig.4, shows fourth die, element #423, and second die, element #421, coupled through second via, element #406). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose wherein the third semiconductor die is electrically coupled to the first semiconductor die through the first via, and wherein the fourth semiconductor die is electrically coupled to the second semiconductor die through the second via. Connecting the dies located at opposite sides of the bridge through bridge vias provides the shortest path for electrical connections, which can improve high-speed data transfer between the dies and increase power efficiency.
Regarding claim 11, the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 10 as set forth in the obviousness rejection. Cheah further teaches the semiconductor package of claim 10, wherein the semiconductor bridge includes a redistribution structure disposed on its back side (Fig.4, element #412 or #413). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose wherein the semiconductor bridge includes a redistribution structure disposed on its back side. Disposing a redistribution structure on the back side of the bridge offers design flexibility in terms of electrical connections between the bridge and the dies connected to it, and facilitates integration and connections of multiple devices as part of the semiconductor package.
Regarding claim 14, the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 10 as set forth in the obviousness rejection. Hawk further teaches the semiconductor package of claim 10, wherein the first corner and the second corner are laterally offset from one another (Fig.4, the corners of dies #110 and #105 overlap by the bridge, element #125, are laterally offset from one another). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hawk and disclose wherein the first corner and the second corner are laterally offset from one another. As disclosed by Hawk, the dies disposed in the same package layer do not overlap and therefore the corners of two dies are laterally offset (Fig.4).
Regarding claim 16, the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 10 as set forth in the obviousness rejection. Elsherbini_977 further teaches wherein the semiconductor bridge is separated from the third semiconductor die and the fourth semiconductor die by a gap-fill layer (Fig.1A, element #127 separates the bridge #114-2 from all the surrounding dies).
Regarding claim 17, the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 10 as set forth in the obviousness rejection. Elsherbini_977 further teaches the semiconductor package of claim 10, wherein the third semiconductor die and the fourth semiconductor die are over the semiconductor bridge, and wherein the third semiconductor die and the fourth semiconductor die each overlap a corner of the semiconductor bridge (Fig.2A, elements 114C, equivalent with elements #114-3 and #114-5 in Fig.3 are disposed over and overlap with the corners of the bridge, element #114B, equivalent with element #114-2 in Fig.3).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini_977 in view of Yu, Hawk, Cheah, Wang and Enquist.
Regarding claim 12, the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 10 as set forth in the obviousness rejection. The combination of Elsherbini_977, Yu, Hawk and Cheah does not teach the semiconductor package of claim 10, further comprising a first redistribution structure disposed on a back side of the first semiconductor die and a second redistribution structure disposed on a back side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure.
Wang teaches a first semiconductor dies (Fig.6A, element #110F.1 on the top left corner) a second semiconductor die (Fig.6A, element #110F.1 on the top right corner) a third semiconductor die (Fig.6A, element #110F.1 on the bottom right corner) and a fourth semiconductor die (Fig.6A, element #110F.1 on the bottom left corner), where the third semiconductor die is electrically coupled to the second semiconductor die via a connecting structure (Fig.6A, element#350 located below the second semiconductor die, and paragraph [0100], rows 5-9) and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second structure (Fig.6A, element#350 located below the first semiconductor die, and paragraph [0100], rows 5-9). In a different embodiment, Wang teaches a semiconductor package further comprising a first redistribution structure disposed on the bottom side of the first semiconductor die (Fig.9E, element #890 disposed under element #110F.1) and a second redistribution structure disposed on a bottom side the second semiconductor die (Fig.9E, element #890 disposed under element #110F.2), wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features (Fig.9E, elements #890 include conductive features #894 and #902). Thus, in two different embodiments Wang teaches two different types of connections between dies. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the structure #350 disclosed in Figure 6A could have been replaced by the redistribution layer, element #890 of Figure 9E, because both serve the same purpose of providing an electrical connection between the dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the dies. The redistribution layer provides better flexibility, an efficient signal routing and can accommodate complex electrical connections.
Thus, Wang teaches a first redistribution structure disposed on a bottom side of the first semiconductor die and a second redistribution structure disposed on a bottom side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wang and disclose redistribution structures disposed on a bottom side of the first and second semiconductor dies, including a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. The redistribution structures allow direct connections between parts of the dies that the bridge cannot reach due to design constraints.
The combination of Elsherbini_977, Yu, Hawk and Wang does not teach that the redistribution structures are disposed on back side of the dies. Enquist teaches redistribution structures disposed on back side of the dies (Fig.3, element #310, paragraph [0046], rows 3-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Enquist and disclose redistribution structures disposed on back sides of die. Disposing the redistribution structures on the back side of dies facilitates integration of multiple devices and offers design flexibility.
Regarding claim 13, the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 10 as set forth in the obviousness rejection and the combination of Elsherbini_977, Yu, Hawk, Cheah, Wang and Enquist teaches the semiconductor package of claim 12 as set forth in the obviousness rejection. Cheah further teaches the semiconductor package of claim 12, wherein the semiconductor bridge includes a third redistribution structure on its back side (Fig.4, element #412 or #413). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose wherein the semiconductor bridge includes a third redistribution structure on its back side. Disposing a redistribution structure on the back side of the bridge offers design flexibility in terms of electrical connections between the bridge and the dies connected to it, and facilitates integration and connections of multiple devices as part of the semiconductor package.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini_977, Yu, Hawk and Cheah, in view of Knickerbocker et al., (United States Patent Application Publication Number, US 2021/0249381 A1) hereinafter referenced as Knickerbocker.
Regarding claim 15, the combination of Elsherbini_977, Yu, Hawk and Cheah teaches the semiconductor package of claim 10 as set forth in the obviousness rejection. The combination of Elsherbini_977, Yu, Hawk and Cheah does not teach the semiconductor package of claim 10, wherein the semiconductor bridge is a first semiconductor bridge, further comprising a second semiconductor bridge overlapping a first edge of the first semiconductor die and a second edge of the semiconductor die, wherein the second semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die. Knickerbocker teaches wherein the semiconductor bridge is a first semiconductor bridge, further comprising a second semiconductor bridge (Fig.9, first bridge is element #925A, second bridge is element #925B) overlapping a first edge of the first semiconductor die (Fig.9, element #925B overlaps the bottom edge of the first die, element #150 in the upper right corner) and a second edge of the second semiconductor die (Fig.9, element #925B overlaps the top edge of the second die element #150 in the bottom right corner), wherein the second semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die (paragraph [0132], rows 6-10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Knickerbocker and disclose wherein the semiconductor bridge is a first semiconductor bridge, further comprising a second semiconductor bridge overlapping a first edge of the first semiconductor die and a second edge of the semiconductor die, wherein the second semiconductor bridge electrically couples the first semiconductor die to the second semiconductor die. As disclosed by Knickerbocker, the two bridges allow the connection of multiple sides of the two dies, and each one of the bridges can a passive or an active bridge, made of different materials, which offers a high degree of flexibility in designing the package.
Claims 21, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini_977 in view of Yu, Hawk, Cheah and Enquist.
Regarding claim 21, Elsherbini_977 teaches a semiconductor package, comprising: a first semiconductor die and a second semiconductor die disposed adjacent one another (Fig.1A, elements #114-1 and #114-4).
Elsherbini_977 teaches a gap fill materials between the first and second die (Fig.4C, element #430 also shown in Fig.1A but not numbered). Elsherbini_977 does not teach the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. Yu teaches the first and the second semiconductor dies (Fig.8, elements #92 and #90) are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction (Fig 13, element #94) wherein both the first scribe line and the second scribe line are filled with a gap-fill layer (Fig.8, element #112, column 10, rows 3-18 fills the space between the dies and the scribe lines). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose the first and the second semiconductor dies are separated by a first scribe line extending along a first direction and a second scribe line extending along a second direction wherein both the first scribe line and the second scribe line are filled with a gap-fill layer. As disclosed by Yu, the scribe lines can be used as a reference for placing the dies on a substrate so that they match preexisting circuit patterns of the substrate. Filling the scribe lines and the space between the dies with a gap-fill layer increases the mechanical integrity of the semiconductor package.
Elsherbini_977 further teaches a semiconductor bridge (Fig.1A, element #114-2, paragraph [0078], rows 1-4). Elsherbini_977 further teaches the semiconductor bridge overlaying a space separating the first and second die (Fig.1A, the bridge element #114-2 overlays the space between the dies). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore the combination of Elsherbini_977 and Yu teaches the semiconductor bridge overlaying the first scribe line or the second scribe line.
The combination of Elsherbini_977 and Yu does not teach the semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. Hawk teaches a bridge overlaying the intersection between the lines separating the chips (Fig.4, element #125 overlays the intersection between the lines separating the chip), and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die (Fig.4, element #125 overlaps a first corner of the first semiconductor die, element #110, and a second corner of the second semiconductor die, element #105). As noted above, Yu teaches the scribe line is located in the space separating the dies, and therefore the combination of Yu and Hawk teaches the bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and Hawk and disclose a semiconductor bridge overlaying an intersection of the first scribe line and the second scribe line and overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. As disclosed by Hawk, this allows the bridge to electrically connect the corners of all the dies separated by the intersection of the two scribe lines (Fig.4).
Elsherbini_977 further teaches a third semiconductor die (Fig.1A, element #114-3) and a fourth semiconductor die (Fig.1A, element #114-5) disposed over and electrically coupled to the semiconductor bridge (Fig.1A, elements #114-3 and #114-5 are electrically coupled to the bridge, element #114-2).
The combination of Elsherbini_977, Yu and Wang does not teach wherein the semiconductor bridge comprises a first redistribution structure disposed on a back side of the first semiconductor die and a second redistribution structure disposed on a back side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. Cheah teaches wherein the semiconductor bridge (Fig.1, formed by bridge element #402 and the redistribution structures to the left and right side of it) comprises a redistribution structure disposed on a bottom side of the first semiconductor die (Fig.4A, structure on the left side of element #402) and a second redistribution structure disposed on a bottom side of the second semiconductor die (Fig.4A, structure on the right side of element #402), wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features (Fig.4A, both structures include conductive features, element #410 is same as element #101 in Fig.1, paragraph [0031], rows 4-6), such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure (Fig.4, element #420 is electrically coupled to element #422 via the redistribution structure on the left side of element #402) and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure (Fig.4, element #421 is electrically coupled to element #423 via the redistribution structure on the right side of element #402). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose wherein the semiconductor bridge comprises a first redistribution structure disposed on a bottom side of the first semiconductor die and a second redistribution structure disposed on a bottom side of the second semiconductor die, wherein each of the first redistribution structure and the second redistribution structure includes a plurality of conductive features such that the third semiconductor die is electrically coupled to the second semiconductor die via the first redistribution structure and the fourth semiconductor die is electrically coupled to the first semiconductor die via the second redistribution structure. Disposing the redistribution structures on the bottom sides of dies provides short electrical paths connecting the dies, which can improve high-speed data transfer between the dies and increase power efficiency, and offers design flexibility in terms of making the electrical connections and placing the dies with respect to one another and the bridge, as part of the semiconductor package.
The combination Elsherbini_977, Yu, Wang and Cheah does not teach the redistribution structures are disposed on the back side of semiconductor dies. Enquist teaches redistribution structures disposed on back side of the dies (Fig.3, #310, paragraph [0046], rows 3-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Enquist and disclose redistribution structures disposed on backsides of die. Disposing the redistribution structure on the back side of dies may results in improved electrical performance by providing short signal paths and facilitate integration of multiple devices as part of the semiconductor package.
Regarding claim 22, the combination of Elsherbini_977, Yu, Wang, Cheah and Enquist teaches the semiconductor package of claim 21 as set forth in the obviousness rejection. Cheah further teaches the semiconductor package of claim 21, wherein the semiconductor bridge includes a first via electrically coupled to the first semiconductor die and a second via electrically coupled to the second semiconductor die, the first via and the second via extending through a substrate of the semiconductor bridge (Fig.4 elements #405 and #406, filled with metal, paragraph [0058], rows 1-4 are coupled to the first and semiconductor die respectively ), wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die (Fig.1 element #402 is interposed between, elements #422 and #423), wherein the third semiconductor die (Fig.4, third semiconductor die, element #422) is electrically coupled to the first semiconductor die (Fig.4, first semiconductor die, element #420) through the first via (Fig.4, shows element #420 and element #422 coupled through element #405), and wherein the fourth semiconductor die (Fig.4, fourth semiconductor die, element #423) is electrically coupled to the second semiconductor die (Fig.4, second semiconductor die, element #421) through the second via (Fig.4, shows element #423 and element #421 coupled through element #406). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cheah and disclose wherein the semiconductor bridge includes a first via electrically coupled to the first semiconductor die and a second via electrically coupled to the second semiconductor die, the first via and the second via extending through a substrate of the semiconductor bridge, wherein the semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die, wherein the third semiconductor die is electrically coupled to the first semiconductor die through the first via, and wherein the fourth semiconductor is electrically coupled to the second semiconductor die through the second via. As disclosed by Cheah, the vias allow direct electrical connections between dies located at opposite sides of the bridge. Connecting the dies located at opposite sides of the bridge through bridge vias provides the shortest path for electrical connections, which can improve high-speed data transfer between the dies and increase power efficiency.
Regarding claim 23, the combination of Elsherbini_977, Yu, Wang, Cheah and Enquist teaches the semiconductor package of claim 21 as set forth in the obviousness rejection. Elsherbini_977 further teaches wherein the semiconductor bridge is separated from the third semiconductor die and the fourth semiconductor die by a gap-fill layer (Fig.1A, element #127 separates the bridge #114-2 from all the surrounding dies).
Response to Arguments
Applicant’s arguments filed on 11/19/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims 1, 10 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899