Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 6, 2026 has been entered.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-17 and 21-23 are pending.
-Claims 18-20 are cancelled.
-Claims 1, 13, and 21 are amended.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn.
Response to Arguments
Applicant's arguments filed March 06, 2026 have been fully considered.
Examiner finds the previously cited references do teach the subject matter of the amended Claims 1, 13, and 21, contrary to Applicant’s arguments, as will be included in the sections below. These limitations seem to be directed towards characteristics of cyclical RIE processes, which Examiner noted in the Advisory Action dated March 17, 2026 as being already taught by the prior art and would not be considered novel by one of ordinary skill in the art.
In regards to Applicant’s arguments directed towards a ratio of a maximum recessed distance and a ratio of a maximum protruding distance, Examiner will henceforth treat the limitations as explicitly directed towards vertical spacings as defined in the instant Specification’s Paragraph [0056] and Fig. 32. However, even under this clarified interpretation, Examiner finds that the prior art still teaches the limitations. Notably, where no spacings are stated between elements, the distance between may be taken as approximately 0, thus as expounded upon below, these limitations are met.
The rejection has been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 15-17, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Pub. 2023/0178437), hereinafter Xie, in view of Lin et al. (U.S. Pub. 2022/0037498), hereinafter Lin.
Regarding Claim 13, Xie teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) comprising:
-forming a plurality of channel regions (regions (150), (152), (154), (156); Fig. 2, Paragraph [0039]- Examiner hereinafter will refer to the group of regions together as (15X)) over a substrate ((102); Fig. 2, Paragraph [0036]), wherein the plurality of channel regions (15X), in parallel with one another, extend along a first lateral direction (e.g. the X-direction, as given in the ‘X-view’; Fig. 2);
-forming a plurality of isolation structures ((STI), Fig. 2, Paragraph [0031]) wherein each of the plurality of channel regions (15X) has a lower portion (e.g. (104); Fig. 2, Paragraph [0031]) embedded by a corresponding pair of the isolation structures (STI) (See Y1 or Y2 view);
-forming a first gate structure (consisting of portions (140), (142), (144), (146); Fig. 2, Paragraph [0032]- Examiner hereinafter will refer to the group of portions together as (14X)) over the plurality of channel regions (15X), wherein the first gate structure (14X) extends along a second lateral direction (e.g. the Y-direction, as seen in the tow-down reference view and the ‘Y1-view’ and ‘Y2-view’; Fig. 2);
-forming a plurality of pairs of epitaxial structures (epitaxially grown S/D regions (130A) and (130B); Fig. 2, Paragraph [0037]) wherein each of the pairs of epitaxial structures ((130A) and (130B)) is disposed on opposite sides (On the right and left in the ‘X-view’; Fig. 2) of the first gate structure (14X);
- removing, through a first process (‘e.g. gate/nanosheet cut techniques’ thus forming (510A); Fig. 5, Paragraph [0043]), a portion of the first gate structure (portion (142)) that was disposed over a first one of the plurality of channel regions (region (152));
-removing, through a second process (consisting of depositing protective liners (160A), (160B), (160C), and (160D) followed by reactive ion etching (RIE); Figs. 6 and 7, Paragraphs [0044]-[0042]), a portion of the first channel region (portion of (104) in region (152));
-removing, through a third process (‘RIE’ thus forming (510B); Fig. 8, Paragraph [0047]), a portion of the substrate (102) that was disposed below the removed portion of the first channel region (portion of (104) in region (152));
-the third process (‘RIE’) forms an opening (510B) that is interposed between at least the corresponding pair of the isolation structures (e.g. left and center (STI); Y2-view of Fig. 8);
-filling, with a dielectric material, an opening formed through the first to third processes (Fig. 1, Paragraph [0048]); and
-replacing a remaining portion of the first gate structure (e.g. (146) in Fig. 2) with a second gate structure (recessed (146) in Fig. 3) (Examiner notes that the element ‘remaining portion of the first gate structure’ isn’t limited to a particular process or at any part of the method and is thus understood by the examiner to mean generally at any point),
-wherein a first ratio of a maximum recessed distance of an upper portion of each of a first one and a second one of the isolation structures (STI) separated by the first channel region to a total height of the isolation structures (Height of (STI)) is less than about 0.15 (Approximately 0, See Fig. 1), and wherein a second ratio of a maximum protruding distance of a portion of the substrate (102) that extends along a lower upper portion of each of the first and second isolation structures to the total height of the isolation structures (Height of (STI)) is less than about 0.11 (Approximately 0, See Fig. 1). (Examiner noted in the Response to Argument section above that Applicant has explicitly defined the maximum recessed distance and maximum protruding distance of the claim limitations as being the vertical ratios as seen in the instant application’s Fig. 32 and defined in Paragraph [0056]. In the case of Xie, no such vertical recesses or protrusions affect the isolation structures, therefore as disclosed these distances are 0, which equate to ratios of 0, which are both less than 0.15 and 0.11 respectively.).
Xie discloses the use of reactive ion etching (RIE), but does not explicitly disclose:
-the third process comprises (i) depositing a protection layer over a surface in an opening formed via the first and second processes, (ii) etching a portion of the protection layer to expose the portion of the substrate disposed below the removed portion of the first channel region, and (iii) removing the portion of the substrate and subsequently a remaining portion of the protection layer
-at least one of the first to third processes includes at least one silicon etching process comprising flowing SiCl4 and N2.
Lin teaches a method for fabricating semiconductor devices which incorporates the use of RIE (Paragraph [0071]) wherein:
-the process comprises (i) depositing a protection layer over a surface in an opening (‘byproduct layers’ (80)/(80B); Fig. 7A, Paragraph [0047]), (ii) etching a portion of the protection layer ((80)/(80B)) to expose a portion disposed below the removed portion (Paragraphs [0048] and [0049]), and (iii) removing subsequently a remaining portion of the protection layer (Figs. 9A-9C, Paragraph [0043])
-includes at least one silicon etching process comprising flowing SiCl4 and N2 (Paragraphs [0049] and [0050]).
As incorporated into the method of Xie, the teachings of Lin would necessarily result in:
the third process comprising (i) depositing a protection layer over a surface in an opening formed via the first and second processes, (ii) etching a portion of the protection layer to expose the portion of the substrate disposed below the removed portion of the first channel region, and (iii) removing the portion of the substrate and subsequently a remaining portion of the protection layer
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lin into the method of Xie such that the third process comprises (i) depositing a protection layer over a surface in an opening formed via the first and second processes, (ii) etching a portion of the protection layer to expose the portion of the substrate disposed below the removed portion of the first channel region, and (iii) removing the portion of the substrate and subsequently a remaining portion of the protection layer and at least one of the first to third processes includes at least one silicon etching process comprising flowing SiCl4 and N2. This would be due to the fact that doing so would have the expected result of using suitable gases to perform a reactive ion etch (RIE) while also adopting a cyclic removal process which protects the upper portion of the etching area (Lin, Paragraph [0048]).
Regarding Claim 15, Xie as modified by Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 13, wherein:
-at least one of the first to third processes further includes at least one silicon oxide deposition process. (As due to the incorporation of the teachings of Lin into the method of Xie. The removal process of Lin is such that at least one of the first to third processes includes at least one silicon oxide deposition process (Lin, Paragraph [0050]- Where in one of the first to third processes, we shall say the second process, uses an oxygen-based passivation gas while the other(s) maintain(s) the use of N2)).
Regarding Claim 16, Xie as modified by Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 15, wherein:
- the second process sequentially includes the at least one silicon etching process (Lin, ‘first etching process’, Paragraph [0046]) and a number of cycles of the at least one silicon oxide deposition process (Lin, ‘byproduct layers’ (80/80B), which are produced following the first etch; Fig. 8A/8B, Paragraph [0048]). (Lin, ‘etching process may include cycling….’ Paragraph [0049]).
Regarding Claim 17, Xie as modified by Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 13, wherein:
-during the first to third processes, a remaining portion of the first gate structure (Xie, (146)) remains substantially intact (Xie, No processing is done to (146) in the first to third processes).
Regarding Claim 21, Xie teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) comprising:
-forming a plurality of channel regions (regions (150), (152), (154), (156); Fig. 2, Paragraph [0039]- Examiner hereinafter will refer to the group of regions together as (15X)) over a substrate ((102); Fig. 2, Paragraph [0036]), wherein the plurality of channel regions (15X), are parallel with one another (parallel along the X-direction),
-forming a plurality of isolation structures ((STI), Fig. 2, Paragraph [0031]) wherein the plurality of channel regions (15X) comprise a respective lower portion (e.g. (104); Fig. 2, Paragraph [0031]) interposed between the plurality of isolation structures (STI) (See Y1 or Y2 view);
-forming a gate structure (consisting of gate portions (140), (142), (144), (146) and gate spacers (120); Fig. 2, Paragraph [0032]- Examiner hereinafter will refer to the group of gate portions together as (14X)) over the plurality of channel regions (15X);
-forming a hardmask material ((402); Fig. 4, Paragraph [0042]) over the gate structure ((14X) and (120));
-removing at least a portion of the hardmask material (thereby forming trench patterns (410) and (420); Fig. 4, Paragraph [0042]) disposed over the plurality of channel regions (15X), a portion of the gate structure (thus forming a part of (510A) and (520); Fig. 5, Paragraph [0043]) disposed over the plurality of channel regions (15X), and a portion of the plurality of channel regions (thus forming the remaining part of (510A); Fig. 5, Paragraph [0043]);
-removing the portion of the substrate (102) to form an opening ((510B); Fig. 8, Paragraph [0047]) that is interposed between at least a corresponding pair of the plurality of isolation structures (e.g. left and center (STI); Y2-view of Fig. 8);
- filling, with a dielectric material (thus forming (170A) and (SAC); Fig. 1, Paragraphs [0048]), the opening formed by removing the portions (‘SDB Trench’ (510A); Fig. 6 Paragraph [0043]); and
-removing at least an upper portion of the dielectric material (via planarizing, Fig. 1, Paragraph [0048]) and an upper portion of the hardmask material (via ash removal operation, Fig. 1, paragraph [0048]), wherein a top surface of the dielectric material is level (e.g. top of (SAC) in the X-view; Fig. 1) with a top surface of the gate structure (e.g. top of adjacent gate spacers (120); Fig. 1).
Xie discloses the use of reactive ion etching (RIE), but does not explicitly disclose:
-depositing, subsequent to removing the portion of the plurality of channel regions, a protection layer over a surface in an opening formed after removing at least the portion of the hardmask material, the portion of the gate structure, and the portion of the plurality of channel regions;
-etching a portion of the protection layer to expose a portion of the substrate disposed below the removed portion of the plurality of channel regions;
-removing (i) the portion of the substrate and subsequently (ii) a remaining portion of the protection layer to form an opening that is interposed between at least a corresponding pair of the plurality of isolation structures;
-removing at least a portion of the hardmask material comprises flowing 02, Ar, and at least one of SiCl4, N2, 02, or chlorine.
Lin teaches a method for fabricating semiconductor devices which incorporates the use of RIE (Paragraph [0071]) wherein:
-depositing a protection layer over a surface in an opening (‘byproduct layers’ (80)/(80B); Fig. 7A, Paragraph [0047])
-etching a portion of the protection layer to expose a portion disposed below the removed portion (Paragraphs [0048] and [0049])
- removing (i) the portion (e.g. lower portions (76L); Figs. 7B and 8A, Paragraph [0048]) and subsequently (ii) a remaining portion of the protection layer to form an opening (Figs. 9A-9C, Paragraph [0043])
-removing at least a portion of the hardmask material comprises flowing O2, Ar, and at least one of SiCl4, N2, O2, or chlorine (Paragraphs [0049] and [0050]).
As incorporated into the method of Xie, the teachings of Lin would necessarily result in:
depositing, subsequent to removing the portion of the plurality of channel regions, a protection layer over a surface in an opening formed after removing at least the portion of the hardmask material, the portion of the gate structure, and the portion of the plurality of channel regions;
etching a portion of the protection layer to expose a portion of the substrate disposed below the removed portion of the plurality of channel regions;
removing (i) the portion of the substrate and subsequently (ii) a remaining portion of the protection layer to form an opening that is interposed between at least a corresponding pair of the plurality of isolation structures;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lin into the method of Xie such that in includes depositing, subsequent to removing the portion of the plurality of channel regions, a protection layer over a surface in an opening formed after removing at least the portion of the hardmask material, the portion of the gate structure, and the portion of the plurality of channel regions;etching a portion of the protection layer to expose a portion of the substrate disposed below the removed portion of the plurality of channel regions;removing (i) the portion of the substrate and subsequently (ii) a remaining portion of the protection layer to form an opening that is interposed between at least a corresponding pair of the plurality of isolation structures; and removing at least a portion of the hardmask material comprises flowing 02, Ar, and at least one of SiCl4, N2, 02, or chlorine. This would be due to the fact that doing so would have the expected result of using suitable gases to perform a reactive ion etch (RIE) while also adopting a cyclic removal process which protects the upper portion of the etching area (Lin, Paragraph [0048]).
Regarding Claim 22, Xie as modified by Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 21, wherein:
-the plurality of channel regions (Xie, (15X)), extend along a first lateral direction (Xie, e.g. the X-direction, as given in the ‘X-view’; Fig. 2), and wherein the gate structure (Xie, (14X)) extends along a second lateral direction perpendicular to the first lateral direction (Xie, e.g. the Y-direction, as seen in the tow-down reference view and the ‘Y1-view’ and ‘Y2-view’; Fig. 2);
Regarding Claim 23, Xie as modified by Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 21, wherein:
-wherein a first ratio of a maximum recessed distance of an upper portion of each of a first one and a second one of the isolation structures (STI) separated by the first channel region to a total height of the isolation structures (Height of (STI)) is less than about 0.15 (Approximately 0, See Fig. 1), and wherein a second ratio of a maximum protruding distance of a portion of the substrate (102) that extends along a lower upper portion of each of the first and second isolation structures to the total height of the isolation structures (Height of (STI)) is less than about 0.11 (Approximately 0, See Fig. 1). (Examiner noted in the Response to Argument section above that Applicant has explicitly defined the maximum recessed distance and maximum protruding distance of the claim limitations as being the vertical ratios as seen in the instant application’s Fig. 32 and defined in Paragraph [0056]. In the case of Xie, no such vertical recesses or protrusions affect the isolation structures, therefore as disclosed these distances are 0, which equate to ratios of 0, which are both less than 0.15 and 0.11 respectively.).
Claims 1-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Lin, and in further view of LeFevre et al. (U.S. Pub. 2015/0126033), hereinafter LeFevre.
Regarding Claim 1, Xie teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) comprising:
-forming a plurality of channel regions (regions (150), (152), (154), (156); Fig. 2, Paragraph [0039]- Examiner hereinafter will refer to the group of regions together as (15X)) over a substrate ((102); Fig. 2, Paragraph [0036]), wherein the plurality of channel regions (15X), in parallel with one another, extend along a first lateral direction (e.g. the X-direction, as given in the ‘X-view’; Fig. 2) and wherein each of the plurality of channel regions (15X) includes at least a respective pair of epitaxial structures (epitaxially grown S/D regions (130A) and (130B); Fig. 2, Paragraph [0037])
-forming a gate structure (consisting of portions (140), (142), (144), (146); Fig. 2, Paragraph [0032]- Examiner hereinafter will refer to the group of portions together as (14X)) over the plurality of channel regions (15X), wherein the first gate structure (14X) extends along a second lateral direction (e.g. the Y-direction, as seen in the tow-down reference view and the ‘Y1-view’ and ‘Y2-view’; Fig. 2);
- removing, through a first process (‘e.g. gate/nanosheet cut techniques’ thus forming (510A); Fig. 5, Paragraph [0043]), a portion of the first gate structure (portion (142)) that was disposed over a first channel region of the plurality of channel regions (region (152));
-performing second process, wherein a portion of the first channel region (portion of (104) in region (152); Fig. 2 and 6, Paragraph [0031]) is removed by at least one silicon etching process (reactive ion etching (RIE); Fig. 7, Paragraph [0046]),
-removing, through a third process (‘RIE’ thus forming (510B); Fig. 8, Paragraph [0047]), a portion of the substrate (102) that was disposed below the removed portion of the first channel region (portion of (104) in region (152))
-wherein the third process comprises removing the portion of the substrate ((510B) of (102))
-wherein the third process forms an opening that is interposed between: (i) remaining portions of the first channel region after the second process (e.g. between adjacent portions in the Y1/Y2 views of Fig. 8, refer also to top-down reference (101A)), and (ii) a pair of epitaxial structures (e.g. left and center (130B) and (130A); X-view of Fig. 8);
Xie does not teach:
-wherein the second process comprises at least one silicon oxide deposition process
-wherein the third process comprises (i) depositing a protection layer over a surface in an opening formed via the first and second processes, (ii) etching a portion of the protection layer to expose the portion of the substrate disposed below the removed portion of the first channel region, and (iii) removing the portion of the substrate and subsequently a remaining portion of the protection layer,
-a third process controlled based on a pulse signal
LeFevre teaches a method of etching for the formation of deep trenches with smooth profiles based on a reactive ion etch (RIE) basis wherein:
-the process (‘etching deep silicon features’; e.g. Fig. 1A, 1B, and 4, Paragraph [0007]) includes at least one silicon oxide deposition process (‘oxide deposition’ Fig. 1A, Paragraph [0020])
-the process comprises (i) depositing a protection layer ((135); Fig. 1A, Paragraph [0020]) over a surface in an opening ((107); Figs. 1A and 1B, Paragraph [0020]), (ii) etching a portion of the protection layer ((135); Fig. 1B) to expose the portion of the substrate ((105); Figs. 1A and 1B, Paragraph [0020]) disposed below the removed portion (on bottom of (107); Fig. 1B), and (iii) removing the portion of the substrate (105) and subsequently a remaining portion of the protection layer (135) ((460); Figs. 3C And 4, Paragraphs [0023] and [0032])
-the process (‘etching deep silicon features’; e.g. Fig. 1A, 1B, and 4, Paragraph [0007]) is controlled based on a pulse signal (‘The RF power output… may be pulsed between an off-state and an on-state’; Paragraph [0039])
As incorporated into the method of Xie, the teachings of LeFevre would necessarily result in:
wherein the third process comprises (i) depositing a protection layer over a surface in an opening formed via the first and second processes, (ii) etching a portion of the protection layer to expose the portion of the substrate disposed below the removed portion of the first channel region, and (iii) removing the portion of the substrate and subsequently a remaining portion of the protection layer,
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of LeFevre into the method of Xie such that the second process includes at least one silicon oxide deposition process, the third process comprises (i) depositing a protection layer over a surface in an opening formed via the first and second processes, (ii) etching a portion of the protection layer to expose the portion of the substrate disposed below the removed portion of the first channel region, and (iii) removing the portion of the substrate and subsequently a remaining portion of the protection layer, and the third process is controlled based on a pulse signal. This would be due to the fact that doing so would provide for a faster etch rate, good mask selectivity, and an etched profile with no or little undercut (LeFevre, Paragraph [0018]).
Xie as modified by LeFevre does not explicitly state:
- the at least one silicon etching process comprises flowing CF4 and Ar.
Lin teaches a method for fabricating semiconductor devices which incorporates the use of RIE (Paragraph [0071]), including cycling between deposition and etching (Paragraphs [0046]-[0048]), wherein:
-the at least one silicon etching process comprises flowing CF4 and Ar. (Paragraphs [0049] and [0050])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lin into the method of Xie as modified by LeFevre such the at least one silicon etching process comprises flowing CF4 and Ar. This would be due to the fact that doing so would have the expected result of using suitable gases to perform a cyclic removal process with reactive ion etching (RIE).
Regarding Claim 2, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 1, wherein:
- the second process sequentially includes the at least one silicon etching process (LeFevre, corresponding to the increased flow of etch chemistry (120); Fig. 2C, Paragraph [0022]) and a number of cycles of the at least one silicon oxide deposition process (LeFevre, corresponding to the increased flow of oxidizing chemistry (110); Fig. 2C, Paragraph [0022])
Regarding Claim 3, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 1, wherein:
- during the first to third processes, a remaining portion of the gate structure (Xie, e.g. (146) Figs. 1 and 4-8) remains substantially intact (No processing is done to (146) in the first to third processes).
Regarding Claim 4, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 1, wherein:
-the at least one silicon oxide deposition process comprises flowing at least one gas selected from the group consisting of silane (SiCl4), hydrogen bromide (HBr), argon (Ar), or oxygen (LeFevre, e.g. ‘SiCl4’; Paragraph [0020]).
Regarding Claim 5, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 1, wherein:
-the channel regions (Xie, (15X)) have their respective lower portions (Xie, e.g. (104); Fig. 2, Paragraph [0031]), and wherein adjacent ones of the lower portions are separated from each other (Xie, e.g. Fig. 2, See Y1 or Y2 view) with a corresponding one of a plurality of isolation structures (Xie, (STI), Fig. 2, Paragraph [0031]).
Regarding Claim 6, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 5, wherein:
-each of the plurality of channel regions (Xie, (15X)) includes a plurality of semiconductor layers vertically spaced from one another (Xie, stacked and spaced-apart nanosheets (112), (114), (116); Fig. 2, Paragraphs [0031] and [0037]) and in contact with the respective pair of epitaxial structures (Xie, (130A) and (130B)).
Regarding Claim 7, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 6, wherein:
-a ratio of a maximum recessed distance (Xie, (RD); Fig. 1A) of an upper portion of each of a first one and a second one of the isolation structures (Xie, (STI)) separated by the first channel region to a total height of the isolation structures (Xie, (TH); Fig. 1A) is less than about 0.15 (Approximately 0.02).
Regarding Claim 8, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 6, wherein:
- a ratio of a maximum protruding distance (Xie, (PD); Fig. 1A) of a portion of the substrate (Xie, (102)) that extends along a lower upper portion of each of the first and second isolation structures to the total height of the isolation structures (Xie, (TH); Fig. 1A) is less than about 0.11 (Approximately 0.03).
Regarding Claim 9, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 1, further comprising:
-filling, with a dielectric material, an opening formed through the first to third processes (Xie, Fig. 1, Paragraph [0048]) thereby electrically isolating (Xie, Paragraph [0032]) respective pair of epitaxial structures (Xie, Specifically the (130B) on the left, and the (130A) in the X-view, Fig. 1) of the first channel region (Xie, (152)) from each other.
Regarding Claim 10, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 5, wherein:
- each of the plurality of channel regions (Xie, (15X)) includes a one-piece structure (Xie, e.g. nanosheet (114); Fig. 2) that is in contact with the corresponding respective pair of epitaxial structures (Xie, (130A) and (130B)).
Regarding Claim 11, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 10, wherein:
-a ratio of a maximum recessed distance (Xie, (RD); Fig. 1A) of an upper portion of each of a first one and a second one of the isolation structures (Xie, (STI)) separated by the first channel region to a total height of the isolation structures (Xie, (TH); Fig. 1A) is less than about 0.1 (Approximately 0.02).
Regarding Claim 12, Xie as modified by LeFevre and Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 10, wherein:
- a ratio of a maximum protruding distance (Xie, (PD); Fig. 1A) of a portion of the substrate (Xie, (102)) that extends along a lower upper portion of each of the first and second isolation structures to the total height of the isolation structures (Xie, (TH); Fig. 1A) is less than about 0.1 (Approximately 0.03).
Regarding Claim 14, Xie as modified by Lin teaches a method for fabricating semiconductor devices (disclosed in steps for fabricating ‘IC wafer’ (100); Figs. 1-8, Paragraphs [0008]-[0016] and [0031]) of Claim 13, but does not teach:
- at least one of the first to third processes is controlled based on a pulse signal.
LeFevre teaches a method of etching for the formation of deep trenches with smooth profiles based on a reactive ion etch (RIE) basis wherein:
- at least one process (‘etching deep silicon features’; e.g. Fig. 1A, 1B, and 4, Paragraph [0007]) is controlled based on a pulse signal (‘The RF power output… may be pulsed between an off-state and an on-state’; Paragraph [0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of LeFevre into the method of Xie as modified by Lin such that at least one of the first to third processes is controlled based on a pulse signal. This would be due to the fact that doing so would provide for a faster etch rate, good mask selectivity, and an etched profile with no or little undercut (LeFevre, Paragraph [0018]).
Conclusion
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/D.M./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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