DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/6/26 has been entered.
Claim Objections
Claim 16 is objected to because it should end in a period.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 22 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter (i.e. “new matter") which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 22 does not have support in the originally filed specification. It requires “the first pillar of the second conductivity type is electrically coupled to a first well, the second pillar of the second conductivity type is electrically coupled a second well and is electrically floating, the third pillar of the second conductivity type is electrically coupled a third well, the third well is separated by a width from the second well that is greater than a width between the second well and the first well.” The originally filed specification does not discuss the limitation “the third well is separated by a width from the second well that is greater than a width between the second well and the first well”. Fig. 1 shows widths Wp and Wn, which are widths of pillars (see e.g. para 10), and Fig. 4 shows widths W1 and W2, which are distances between pillars (see para 77), but nowhere are the distances between the wells described in a way that supports the limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claim(s) 1-10 and 13-20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US 2001/0028083 A1 (“Onishi”) in view of US 2008/0001217 A1 (“Kawashima”).
Onishi teaches, for example:
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Onishi teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A semiconductor device (see e.g. Figs. 4A-4B, 10, 18, etc.), comprising:
a semiconductor substrate (e.g. 11, see para 55);
a blocking layer in an active region (e.g. region including the “drain drift region 22”, see e.g. para 55) including:
a first pillar (e.g. 22a in Fig. 4B or 22b in Fig. 10; for example, see “1st pillar of 1st type” label in annotated version of Fig. 10, above) of a first conductivity type (n-type),
a first pillar (e.g. 22b or 22bb in Fig. 4B or 22b in Fig. 10; for example, see “1st pillar of 2nd type” label in annotated version of Fig. 10, above) of a second conductivity type (p-type) electrically coupled to a source electrode 17 and extending along a vertical direction on the semiconductor substrate between the source electrode and the semiconductor substrate (see e.g. Figs. 4B and 10); and
a termination region (e.g. region including the “breakdown withstanding region” 20 or 420, see e.g. para 56 and Figs. 4A-4B and 10) including:
a second pillar (e.g. one of the regions 20ab of Fig. 4B or one of the regions 420a in Fig. 10; for example, see “2nd pillar of 2nd type” label in annotated version of Fig. 10, above) of the first conductivity type (n-type), and
a second pillar (e.g. one of the regions 20b of Fig. 4B or one of the regions 420b in Fig. 10; for example, see “2nd pillar of 1st type” label in annotated version of Fig. 10, above) of the second conductivity type (p-type),
the second pillar of the first conductivity type being disposed between the first pillar of the second conductivity type and the second pillar of the second conductivity type (see e.g. Figs. 4A-4B and annotated version of Fig. 10, above), and
a third pillar (e.g. 20aa in Fig. 4B or another 420a in Fig. 10; for example, see “3rd pillar of 1st type” label in annotated version of Fig. 10, above) of the first conductivity type (n-type), and having a width greater than a width of the second pillar of the first conductivity type (all pillars 420a have wavy sides in Fig. 10; consider one of the pillars 420a to be the third pillar of the first conductivity type, and another one of the pillars 420a to the second pillar; the maximum width of the third pillar of the first conductivity type is larger than the minimum width of the second pillar of the first conductivity type).
Onishi does not explicitly disclose: the second pillar of the first conductivity type each having a density profile uniform in a horizontal direction and varying in the vertical direction.
Regarding the “density profile uniform in a horizontal direction and varying in the vertical direction”: as discussed in the applicants' specification, see Figs. 9B-9H, these requirements of the density profile are accomplished by implanting N-type regions such as 110-N1 (Fig. 9B) in a continuous layer across the entire top of the layer that is to be doped (110-U1, see Fig. 9A), followed by implanting P-type implants into regions such as 110-P1 (Fig. 9C) that are spaced apart from each other. This process is then repeated many times vertically (see Figs. 9D-9G), with the same symmetry (e.g. the dopants in the upper layers directly overlie those in the lower layers). After annealing (which is shown as a progression from Fig. 9I-9K at various stages of the annealing), the pillars are of the form as shown in Fig. 9K. As shown in Fig. 9K, because the N-type implants are initially in layers across the entire region, they diffuse only vertically; whereas because the p-type implants are formed in localized regions that do not cover the entire region, they diffuse radially. As a result, the N-type regions grow vertically while the p-type regions grow radially, and thus the concentration of the n-type dopant will be uniform horizontally across all of the pillars while it will vary in the vertical direction.
Onishi forms the pillars in region 20 in the same way. N-type implants 33 (mislabeled as “31” in Fig. 11B, but see para 87) are formed in an entire active area in a single layer 34 (Figs. 11B). Then, P-type implants 35 are formed in spaced out, selected areas 36, in that layer (Fig. 11C). This process then repeats in multiple layers vertically (Fig. 11D). After this, the implants are diffused (Fig. 11E). Because the process is the same, it will result in the same structure with the same general properties, and would result in the same structure as in the applicants’ specification and claims (Fig. 11E) with the same uniformity of n-type implants across the N- and P- pillars and the same variation of the n-type implants vertically in the n-type pillar.
Thus, while Onishi does not explicitly disclose the density limitation by plotting impurity concentrations versus position, because the processes are the same, the results are the same, and the claimed limitations would result in the disclosure of Onishi.
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Onishi does not explicitly disclose: the first pillar of the first conductivity type and the second pillar of the first conductivity type each having a density profile uniform in a horizontal direction and varying in the vertical direction.
Kawashima teaches, for example:
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Kawashima teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Onishi, that the first pillar of the first conductivity type and the second pillar of the first conductivity type each having a density profile uniform in a horizontal direction and varying in the vertical direction (In Kawashima, pillars in the active element region and in the peripheral region are both formed in the same way, by ion implantation processes, resulting in wavy profiles similar to Onishi’s pillars in the peripheral region, thus suggesting to use Onishi’s formation of pillars in both regions the same way as Onishi forms the pillars in the peripheral region 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Kawashima to the invention of Onishi. The motivation to do so is that the combination produces the predictable results of forming the pillars having wavy sides in both the active region and in the peripheral breakdown region (see e.g. Figs. 2 and 3) in a way that improves the breakdown voltage of the device as a whole (see e.g. para 23, 26-29, 61, etc.).
Onishi and Kawashima together teach and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
2. The semiconductor device of claim 1, wherein the density profile of the second pillar of the first conductivity type varies in the vertical direction according to a predetermined period (see Onishi, Figs. 10 and 11D, wherein the equal thickness of 30 would result in the same predetermined period).
3. The semiconductor device of claim 1, wherein a high-density portion and a low-density portion in the density profile of the second pillar of the first conductivity type are repeated along the vertical direction (see Onishi, Figs. 10 and 11D).
4. The semiconductor device of claim 1, wherein
the second pillar of the first conductivity type has a side surface that contacts a side surface of the second pillar of the second conductivity type,
the side surface of the second pillar of the first conductivity type has curves opposite curves of the side surface of the second pillar of the second conductivity type (see Onishi, Fig. 10).
5. The semiconductor device of claim 1, further comprising: a first conductivity type epi-layer formed on the semiconductor substrate (e.g. Onishi, 30, Fig. 11a, para 85).
6. The semiconductor device of claim 1, wherein
the semiconductor substrate includes a high density N-type substrate 11 (n+),
the second pillar of the first conductivity type is an N-type pillar (n-type, see discussion of claim 1), and
the second pillar of the second conductivity type is a P-type pillar (p-type, see discussion of claim 1).
7. The semiconductor device of claim 1, wherein the first pillar of the first conductivity type and the first pillar of the second conductivity type have a horizontal cross-section structure including a striped structure, a circular structure, or a cellular structure (see Onishi, e.g. Figs. 4B, 10, and 11e).
8. The semiconductor device of claim 1, wherein the second pillar of the second conductivity type is disposed between the second pillar of the first conductivity type and the third pillar of the first conductivity type (see e.g. annotated version of Fig. 10).
9. The semiconductor device of claim 1, wherein the first pillar of the second conductivity type (e.g. 22a in Fig. 4B or 22b in Fig. 10) is electrically coupled to the source electrode via a well (e.g. Onishi, 13a/14 in Fig. 4, or only 13a in Fig. 4; or e.g. 13a/26/14 or a part thereof in Fig. 10).
10. The semiconductor device of claim 9, wherein the well includes a high-density impurity region (e.g. Onishi, 13a, which is highly doped p-type as denoted by p+).
13. The semiconductor device of claim 1, further comprising: a field oxide layer 23, the second pillar of the second conductivity type is coupled to the field oxide layer via a well 20c (see e.g. Onishi, Fig. 18).
Re claim 14, Onishi teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
14. A semiconductor device (see e.g. Figs. 4A-4B, 10, 18, etc.), comprising:
a semiconductor substrate 11 (para 55);
a blocking layer in an active region (e.g. region including the “drain drift region 22”, see e.g. para 55) including:
a first pillar (e.g. 22a in Fig. 4B or 22b in Fig. 10; for example, see “1st pillar of 1st type” label in annotated version of Fig. 10, above) of a first conductivity type (n-type),
a first pillar (e.g. 22b or 22bb in Fig. 4B or 22b in Fig. 10; for example, see “1st pillar of 2nd type” label in annotated version of Fig. 10, above) of a second conductivity type (p-type) electrically coupled to a source electrode 17 and extending along a vertical direction on the semiconductor substrate between the source electrode and the semiconductor substrate (see e.g. Figs. 4B and 10); and
a termination region (e.g. region including the “breakdown withstanding region” 20 or 420, see e.g. para 56 and Figs. 4A-4B and 10) including:
a second pillar (e.g. one of the regions 20ab of Fig. 4B or one of the regions 420a in Fig. 10; for example, see “2nd pillar of 2nd type” label in annotated version of Fig. 10, above) of the first conductivity type (n-type), and
a second pillar (e.g. one of the regions 20b of Fig. 4B or one of the regions 420b in Fig. 10; for example, see “2nd pillar of 1st type” label in annotated version of Fig. 10, above) of the second conductivity type (p-type),
the second pillar of the first conductivity type being disposed between the first pillar of the second conductivity type and the second pillar of the second conductivity type (see e.g. Figs. 4A-4B and 10),
the second pillar of the first conductivity type has a side surface with curves opposite curves of a side surface of the second pillar of the second conductivity type (see e.g. Figs. 4A-4B and annotated version of Fig. 10, above), and
a third pillar (e.g. 20aa in Fig. 4B or another 420a in Fig. 10; for example, see “3rd pillar of 1st type” label in annotated version of Fig. 10, above) of the first conductivity type (n-type), and having a width greater than a width of the second pillar of the first conductivity type (all pillars 420a have wavy sides in Fig. 10; consider one of the pillars 420a to be the third pillar of the first conductivity type, and another one of the pillars 420a to the second pillar; the maximum width of the third pillar of the first conductivity type is larger than the minimum width of the second pillar of the first conductivity type).
Onishi does not teach that the first pillar of the first conductivity type has a side surface with curves opposite curves of a side surface of the first pillar of the second conductivity type.
Kawashima teaches, for example:
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Kawashima teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Onishi that the first pillar of the first conductivity type (e.g. area between adjacent 106s, which is N-type, see e.g. Fig. 3) has a side surface with curves opposite curves of a side surface of the first pillar of the second conductivity type (e.g. 106, which are P-type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Kawashima to the invention of Onishi. The motivation to do so is that the combination produces the predictable results of forming the pillars having wavy sides in both the active region and in the peripheral breakdown region (see e.g. Figs. 2 and 3) in a way that improves the breakdown voltage of the device as a whole (see e.g. para 23, 26-29, 61, etc.).
Onishi and Kawashima together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
15. The semiconductor device of claim 14, wherein the first pillar of the second conductivity type is electrically coupled to a source electrode 17 and extends along a vertical direction on the semiconductor substrate between the source electrode and the semiconductor substrate (see e.g. Figs. 4, 10, 11e, and 18, etc.).
Re claim 16, Onishi and Kawashima teach the semiconductor device of claim 15 (see discussion above), but do not explicitly disclose: the second pillar of the first conductivity type has a density profile uniform in a horizontal direction orthogonal to the vertical direction, and the density profile of the first conductivity type varies in the vertical direction.
As discussed in the applicants' specification, see Figs. 9B-9H, these requirements of the density profile are accomplished by implanting N-type regions such as 110-N1 (Fig. 9B) in a continuous layer across the entire top of the layer that is to be doped (110-U1, see Fig. 9A), followed by implanting P-type implants into regions such as 110-P1 (Fig. 9C) that are spaced apart from each other. This process is then repeated many times vertically (see Figs. 9D-9G), with the same symmetry (e.g. the dopants in the upper layers directly overlie those in the lower layers). After annealing (which is shown as a progression from Fig. 9I-9K at various stages of the annealing), the pillars are of the form as shown in Fig. 9K. As shown in Fig. 9K, because the N-type implants are initially in layers across the entire region, they diffuse only vertically; whereas because the p-type implants are formed in localized regions that do not cover the entire region, they diffuse radially. As a result, the N-type regions grow vertically while the p-type regions grow radially, and thus the concentration of the n-type dopant will be uniform horizontally across all of the pillars while it will vary in the vertical direction.
Onishi forms the pillars in the same way. N-type implants 33 (mislabeled as “31” in Fig. 11B, but see para 87) are formed in an entire active area in a single layer 34 (Figs. 11B). Then, P-type implants 35 are formed in spaced out, selected areas 36, in that layer (Fig. 11C). This process then repeats in multiple layers vertically (Fig. 11D). After this, the implants are diffused (Fig. 11E). Because the process is the same, it will result in the same structure with the same general properties, and would result in the same structure as in the applicants’ specification and claims (Fig. 11E) with the same uniformity of n-type implants across the N- and P- pillars and the same variation of the n-type implants vertically in the n-type pillar.
Thus, while Onishi and Kawashima do not explicitly disclose the limitations by plotting impurity concentrations versus position, because the processes are the same, the results are the same, and the claimed limitations would result.
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
17. The semiconductor device of claim 16, wherein the density profile of the second pillar of the first conductivity type varies in the vertical direction according to a predetermined period (see Figs. 10 and 11D, wherein the equal thickness of 30 would result in the same predetermined period).
18. The semiconductor device of claim 16, wherein a high-density portion and a low-density portion in the density profile of the second pillar of the first conductivity type are repeated along the vertical direction (see Figs. 10 and 11D).
19. The semiconductor device of claim 14, wherein the second pillar of the first conductivity type has a side surface that contacts a side surface of the second pillar of the second conductivity type (see e.g. Figs. 4, 10, 11e, and 18, etc.).
20. The semiconductor device of claim 14, wherein the second pillar of the second conductivity type being disposed between the second pillar of the first conductivity type and the third pillar of the first conductivity type (see e.g. annotated version of Fig. 10),
Claim(s) 11-12 and 21 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Onishi and Kawashima, as applied to claim 10, above, and further in view of US 2009/0079002 A1 (“Lee”) (cited in parent applications, and listed on the IDS filed 2/15/23).
Onishi and Kawashima teaches and/or suggests as obvious the limitations of claim 10, as discussed above, but do not further teach:
wherein the well is a first well, the second pillar of the second conductivity type is electrically coupled to a second well and is electrically floating (claim 10),
excludes any high-density impurity region (claim 11),
the second well is floating (claim 21).
Lee teaches:
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Lee teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Onishi and Kawashima,
wherein the well is a first well 338 (Fig. 3), the second pillar 329 of the second conductivity type (p-type) is electrically coupled to a second well 342 and is electrically floating (see Fig. 3, wherein it is not connected to an electrically grounded element) (claim 10),
excludes any high-density impurity region (342 itself does not include the highly doped region of Onishi, and itself is not highly doped, designated as p+) (claim 11),
the second well is floating (see Fig. 3, wherein it is not connected to an electrically grounded element) (claim 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lee to the invention of Onishi and Kawashima. The motivation to do so is that the combination produces the predictable results of using a transition region 304 to aid in the termination by bridging pillars together in a way that reduces the breakdown voltage in region 304 as compared to in the active region 301 (para 248).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are not persuasive. Applicant argues that the new limitations of claims 1 and 14 wherein the third pillar is in the termination region is not taught (see remarks, filed 2/6/26, last paragraph of page 7). This is not persuasive. See the updated rejection, above, including the annotated Fig. 10, that includes updated element matching that explains how the limitation is met.
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896