DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 07/06/2026 has been entered. Claims 1-16 and 21 are canceled by
Applicant. Claims 37-42 are new.
Election/Restrictions
The amendment of claim 17 related to “wherein a relative permittivity of the gate dielectric
layer is equal to the relative permittivity of the lower dielectric layer and a thickness of the gate dielectric layer is greater than the thickness of the lower dielectric layer” is directed to a different Species to the Species described in previous claim 17. This amendment of claim 17 is showed in Figure 3G, paragraph [0033], while the previous claim 17 is described by Figures 3A, 18. For this reason, the limitation of “wherein a relative permittivity of the gate dielectric layer is equal to the relative permittivity of the lower dielectric layer and a thickness of the gate dielectric layer is greater than the thickness of the lower dielectric layer” is withdrawn by consideration.
Newly submitted claims 37-42 directed to an invention that is independent or distinct from the
invention originally claimed for the following reasons: Newly submitted claims 37-42 include limitations directed to a different Species to the Species disclosed in claims 17-31 (showed in Figures 3A, 18), then claims 37-42 bring restriction. Claim 37 include the limitation of “the source-follower transistor comprises a second gate dielectric structure including a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer, wherein the second gate dielectric layer is between the first gate dielectric layer and the third gate dielectric layer, wherein a thickness of the second gate dielectric layer is greater than a thickness of the first gate dielectric layer and less than a thickness of the third gate dielectric layer, wherein the thickness of the first gate dielectric layer is less than a thickness of the first gate dielectric structure”, or in claim 40 “wherein a thickness of the third gate dielectric structure is less than a thickness of the second gate dielectric structure” the limitations in claim 37-42 are disclosed in Figs. 3B,3E. However, claim 17 of the elected Invention is disclosed in Figs. 7-18.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 37-42 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Arguments
Applicant’s arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 07/06/2026, have been fully considered. Applicant’s arguments related to claims 17 and 26: “… Arimura is silent in regards to a thickness of the interfacial dielectric layer 102… … The rejection therefore relies upon impermissible hindsight reconstruction using Applicant's disclosure as a roadmap… As seen in Fig. 2 of Yamashita above, each of the transistors 13, 14, and 15 have a gate insulating film with a common thickness and a common structure. The OA of 3/5/26 does not explain why one of ordinary skill in the art would have selectively employ Arimura's multilayer gate dielectric structure for only the amplifying transistor 14 and/or the reset transistor 15 of Yamashita while simultaneously retaining a different gate dielectric structure for the transfer transistor 13 of Yamashita… …The cited art fails to teach a relative permittivity of the gate dielectric layer is equal to the relative permittivity of the lower dielectric layer and a thickness of the gate dielectric layer is greater than the thickness of the lower dielectric layer…”.
The Applicant’s arguments related to claims 17 and 26 are not persuasive because interfacial dielectric layer 102 is about 2nm from Arimura’s Fig. 3 (the image in figure 3 includes the scale). In relation to the combination of Ogino (US 20200251518 A1), Yamashita (US 20080192135 A1) and Arimura (US 20170162686 A1) is still considered proper because the incorporation of a dielectric structure (Arimura) in one of the transistors of device (such as transistor 14, Yamashita) is included based on the electrical characteristics/requirements of the device, then to provide high performance, high mobility and excellent BTI reliability (in [0009] Arimura). Arimura discloses a gate dielectric structure that can be applied to any transistor of the device, it does not suggest that all transistors of the device must be include the gate dielectric structure from Arimura. Regarding to the amendment of claim 17, this is not persuasive because is rejected by the combination of Ogino, Yamashita and Arimura, see rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 17-20 and 22-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 17, it recites the limitation “…forming a plurality of second transistors over the first substrate, wherein the second transistors…” is not explained. The limitation has an antecedent issue of “the second transistors”. Therefore, it is indefinite. For the examination purpose and according to claim 17, the limitation “…forming a plurality of second transistors over the first substrate, wherein the second transistors…” is interpreted as “…forming a plurality of second transistors over the first substrate, wherein the plurality of second transistors.
Regarding claims 17-20 and 22-25, those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 17.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 and 19-20, 22-31 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ogino et al (US 20200251518 A1, hereinafter Ogino, of the record) in view of Yamashita et al. (US 20080192135 A1, hereinafter Yamashita of the record) and further in view of Arimura (US 20170162686 A1, hereinafter Arimura of the record).
Re: Independent Claim 17, Ogino discloses a method for forming an image sensor, the method comprising:
forming a photodetector (220 photodiodes in [0082], Fig. 2) within a first substrate (200 substrate in [0082], Fig. 2);
forming a first transistor (202 transfer transistor in [0082]) on the first substrate (200) adjacent (Fig. 2-Annotated) to the photodetector (220);
forming a plurality of second transistors (pixel transistors including reset transistors amplification transistors, and selective transistors in [0084], not shown);
forming a third transistor (102 transistor having a gate dielectric made of silicon oxide in [0080]) on a second substrate (100 substrate in [0080], Fig. 2); and
bonding (Fig. 2) the second substrate (100) to the first substrate (200).
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Ogino’s Figure 2-Annotated.
Ogino does not expressly disclose wherein the first transistor comprises a gate electrode and a gate dielectric layer between the gate electrode and the first substrate; forming a plurality of second transistors (pixel transistors) over the first substrate, wherein the plurality of second transistors comprise a first readout transistor having a first readout gate dielectric structure comprising a lower dielectric layer stacked with an upper dielectric structure, wherein a relative permittivity of the upper dielectric structure is greater than a relative permittivity of the lower dielectric layer, and wherein a thickness of the upper dielectric structure is greater than a thickness of the lower dielectric layer; wherein the third transistor has a gate dielectric structure with a relative permittivity less than the relative permittivity of the upper dielectric structure.
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Yamashita’s Figure 2-Annotated.
However, in the same semiconductor device manufacturing field of endeavor, Yamashita discloses a pixel circuit wherein the first transistor (13 a transfer transistor in [0024], Fig. 2) comprises a gate dielectric layer (13B a gate insulating film in [0046], Fig. 2) between the gate electrode (13A a gate electrode in [0046], Fig. 2) and the first substrate (51 a semiconductor substrate in [0035], Fig. 2); forming a plurality of second transistors (14, 15 an amplifying transistor 14, a reset transistor 15 in [0024], Fig. 2) over the first substrate (51 a semiconductor substrate in [0035], Fig. 2), wherein the plurality of second transistors (14, 15) comprise a first readout transistor (14,15 are readout transistors in [0024], Fig. 2-Annotated, as example 14 may be a first readout transistor) having a first readout gate dielectric structure (14B-d a gate insulating film, similar to 13B, having a thickness of 5nm, in [0012,0046], Fig. 2-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yamashita’s method of the first transistor comprises a gate electrode and a gate dielectric layer between the gate electrode and the first substrate; forming a plurality of second transistors over the first substrate, wherein the plurality of second transistors comprise a first readout transistor having a first readout gate dielectric structure to Ogino’s method to reduce dark current noise for maintaining the signal-to-noise ratio in fine pixels ([0007], Yamashita).
Ogino modified by Yamashita does not expressly disclose a first readout transistor having a first readout gate dielectric structure comprising a lower dielectric layer stacked with an upper dielectric structure, wherein a relative permittivity of the upper dielectric structure is greater than a relative permittivity of the lower dielectric layer, and wherein a thickness of the upper dielectric structure is greater than a thickness of the lower dielectric layer; wherein the third transistor has a gate dielectric structure with a relative permittivity less than the relative permittivity of the upper dielectric structure.
However, in the same semiconductor device manufacturing field of endeavor, Arimura discloses a transistor (transistor in [0010], Fig. 3) having a gate dielectric structure (102,103,104 a SiO2 layer 102, a LaSiO layer 103, a HfO2 layer 104 in [0070], Fig. 3) comprising a lower dielectric layer (102 a SiO2 layer in [0070], Fig. 3) stacked with an upper dielectric structure (103,104 a LaSiO layer 103, a HfO2 layer 104 in [0070], H-102,103,104 having a height/thickness of around 6nm, Fig. 3-Annotated), wherein a relative permittivity of the upper dielectric structure (103,104) is greater (LaSiO-HfO2 have a greater relative permittivity than SiO2, [0070], Fig. 3) than a relative permittivity of the lower dielectric layer (102), and wherein a thickness of the upper dielectric structure (103,104) is greater (Fig. 3-Annotated) than a thickness of the lower dielectric layer (102).
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Arimura’s Figure 3-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Arimura’s method of a transistor having a gate dielectric structure comprising a lower dielectric layer stacked with an upper dielectric structure, wherein a relative permittivity of the upper dielectric structure is greater than a relative permittivity of the lower dielectric layer, and wherein a thickness of the upper dielectric structure is greater than a thickness of the lower dielectric layer to the combination of Ogino and Yamashita to provide transistors having high performance, high mobility and excellent BTI reliability ([0009], Arimura).
The combination of Ogino, Yamashita and Arimura results in a first readout transistor having a first readout gate dielectric structure comprising a lower dielectric layer stacked with an upper dielectric structure, wherein a relative permittivity of the upper dielectric structure is greater than a relative permittivity of the lower dielectric layer, and wherein a thickness of the upper dielectric structure is greater than a thickness of the lower dielectric layer; wherein the third transistor (102, Ogino) has a gate dielectric structure (102 having a gate dielectric made of silicon oxide in [0080], Ogino) with a relative permittivity less (SiO2 from Ogino’s 102 have a less relative permittivity than LaSiO-HfO2 from Arimura’s 103,104) than the relative permittivity of the upper dielectric structure (103,104 applied to Ogino/ Yamashita’s 14).
Re: Claim 19, Ogino modified by Yamashita and Arimura discloses the method of claim 17,
Ogino modified by Yamashita and Arimura does not expressly disclose wherein a thickness of the gate dielectric structure of the third transistor is less than the thickness of the upper dielectric structure.
However, in the same semiconductor device manufacturing field of endeavor, Yamashita discloses a transistor (13 a transistor in [0024], Fig. 2) having the gate dielectric structure (13B a gate insulating film, having a thickness of 5nm, in [0012,0046], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yamashita’s method of wherein of the gate dielectric structure of the transistor having a thickness of 5nm to the combination of Ogino, Yamashita and Arimura to reduce dark current noise for maintaining the signal-to-noise ratio in fine pixels ([0007], Yamashita).
The combination of Ogino, Yamashita and Arimura results in wherein a thickness of the gate dielectric structure of the third transistor (13B having a thickness of 5nm, Fig. 2, Yamashita applied to Ogino) is less (13B’s Yamashita having a thickness less than 103-104’s Arimura, Fig. 3) than the thickness of the upper dielectric structure (103-104 having a thickness of around 6nm, Fig. 3, Arimura).
Re: Claim 20, Ogino modified by Yamashita and Arimura discloses the method of claim 17, wherein the upper dielectric structure (103,104 Fig. 3, Arimura) comprises a first upper dielectric layer (103 Fig. 3, Arimura) stacked with a second upper dielectric layer (104 Fig. 3, Arimura), wherein a relative permittivity of the first upper dielectric layer (103 Fig. 3, Arimura) is less or higher (103-LaSiO having a relative permittivity of 20 and 104-HfO2 of 25, Fig. 3, Arimura) than a relative permittivity of the second upper dielectric layer (104 Fig. 3, Arimura).
Re: Claim 22, Ogino modified by Yamashita and Arimura discloses the method of claim 17,
Ogino modified by Yamashita and Arimura does not expressly disclose further comprising: performing a doping process to form a floating diffusion node in the first substrate adjacent to the first transistor, wherein a first readout gate electrode of the first readout transistor is directly electrically coupled to the floating diffusion node.
However, in the same semiconductor device manufacturing field of endeavor, Yamashita discloses a pixel circuit performing a doping process to form a floating diffusion node (16 a floating diffusion layer in [0024], Fig. 2) in the first substrate (51 a semiconductor substrate in [0035], Fig. 2) adjacent to the first transistor (13 a transfer transistor in [0024], Fig. 2), wherein a first readout gate electrode (14A a gate electrode in [0038], Fig. 2) of the first readout transistor (14 a amplifying in [0024], Fig. 2) is directly electrically coupled to the floating diffusion node (51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yamashita’s method of performing a doping process to form a floating diffusion node in the first substrate adjacent to the first transistor, wherein a first readout gate electrode of the first readout transistor is directly electrically coupled to the floating diffusion node to the combination of Ogino, Yamashita and Arimura to reduce dark current noise for maintaining the signal-to-noise ratio in fine pixels ([0007], Yamashita).
Re: Claim 23, Ogino modified by Yamashita and Arimura discloses the method of claim 17, wherein the plurality of second transistors comprise a second readout transistor (15 a reset transistor in [0024], Fig. 2, Yamashita) having a second readout gate dielectric structure (15B a gate insulating film similar to 13B, having a thickness of 5nm in [0012,0046], Fig. 2, Yamashita), wherein the second readout gate dielectric structure (15B Fig. 2, Yamashita) comprises a single material (15B made of one single layer Fig. 2, Yamashita) .
Ogino modified by Yamashita and Arimura does not expressly disclose wherein the second readout gate dielectric structure comprises a single material having a relative permittivity less than the relative permittivity of the upper dielectric structure.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to include the second readout gate dielectric structure comprises a single material made of silicon oxide since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297, See MPEP 2144.07.
The combination of Ogino, Yamashita and Arimura results in the second readout gate dielectric structure (15B Fig. 2, Yamashita) comprises a single material having a relative permittivity less (15B’s Yamashita made of SiO2 having a relative permittivity less than 103’s Arimura- LaSiO, 104’s Arimura -HfO2, Fig. 3) than the relative permittivity of the upper dielectric structure (103,104 Fig. 3, Arimura).
Re: Claim 24, Ogino modified by Yamashita and Arimura discloses the method of claim 23,
Ogino modified by Yamashita and Arimura does not expressly disclose wherein forming the plurality of second transistors comprises performing a doping process to form a plurality of source/drain regions of the first and second readout transistors in the first substrate, wherein the plurality of source/drain regions comprise a common source/drain region shared between the first and second readout transistors.
However, in the same semiconductor device manufacturing field of endeavor, Yamashita discloses a pixel circuit forming the plurality of second transistors (14, 15 an amplifying transistor 14, a reset transistor 15 in [0024], Fig. 2) comprises performing a doping process to form a plurality of source/drain regions (14B, 15B diffusion layers in [0037], Fig. 2) of the first and second readout transistors (14, 15 in [0024], Fig. 2) in the first substrate (51 a semiconductor substrate in [0035], Fig. 2), wherein the plurality of source/drain regions (14B, 15B) comprise a common source/drain region (15B) shared between the first and second readout transistors (14, 15 in [0024], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yamashita’s method forming the plurality of second transistors comprises performing a doping process to form a plurality of source/drain regions of the first and second readout transistors in the first substrate, wherein the plurality of source/drain regions comprise a common source/drain region shared between the first and second readout transistors to the combination of Ogino, Yamashita and Arimura to reduce dark current noise for maintaining the signal-to-noise ratio in fine pixels ([0007], Yamashita).
Re: Claim 25, Ogino modified by Yamashita and Arimura discloses the method of claim 23, wherein a height of the first readout gate dielectric structure (H-102,103,104 having a height of around 6nm, Fig. 3-Annotated, Arimura) is greater than a height of the second readout gate dielectric structure (15B a height of 5nm, Fig. 2, Yamashita).
Re: Independent Claim 26, Ogino discloses a method for forming an image sensor, the method comprising:
forming a plurality of photodetectors (220 photodiodes in [0082], Fig. 2) in a first substrate (200 substrate in [0082], Fig. 2);
forming a transfer gate structure (202 transfer transistor in [0082]) on a first surface of the first substrate (200) and adjacent (Fig. 2-Annotated) to the plurality of photodetectors (220);
forming a floating diffusion node (221 floating diffusion in [0082]) in the first substrate (200) and adjacent to the transfer gate structure (202); and
Ogino does not expressly disclose wherein the transfer gate structure (200) comprises a first gate dielectric and a first gate electrode; and forming a source-follower transistor on the first surface of the first substrate, wherein the source-follower transistor comprises a second gate dielectric and a second gate electrode, wherein a height of the first gate dielectric over the first surface of the first substrate is less than a height of the second gate dielectric, wherein an equivalent oxide thickness (EOT) of the second gate dielectric is less than an EOT of the first gate dielectric, wherein the second gate electrode is coupled to the floating diffusion node.
However, in the same semiconductor device manufacturing field of endeavor, Yamashita discloses a pixel circuit wherein the transfer gate structure (13 a transfer transistor in [0024], Fig. 2) comprises a first gate dielectric (13B a gate insulating film in [0046], Fig. 2) and a first gate electrode (13A a gate electrode in [0046], Fig. 2); and forming a source-follower transistor (14 a amplifying in [0024], Fig. 2) on the first surface of the first substrate (51 a semiconductor substrate in [0035], Fig. 2), wherein the source-follower transistor (14) comprises a second gate dielectric (14B-d a gate insulating film, similar to 13B, having a thickness of 5nm, in [0012,0046], Fig. 2-Annotated) and a second gate electrode (14A a gate electrode in [0038], Fig. 2), wherein the second gate electrode (14A) is coupled (Fig. 2) to the floating diffusion node (16 a floating diffusion layer in [0024], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yamashita’s method of wherein the transfer gate structure comprises a first gate dielectric and a first gate electrode; and forming a source-follower transistor on the first surface of the first substrate, wherein the source-follower transistor comprises a second gate dielectric and a second gate electrode, wherein the second gate electrode is coupled to the floating diffusion node to Ogino’s method to reduce dark current noise for maintaining the signal-to-noise ratio in fine pixels ([0007], Yamashita).
Ogino modified by Yamashita does not expressly disclose wherein a height of the first gate dielectric over the first surface of the first substrate is less than a height of the second gate dielectric, wherein an equivalent oxide thickness (EOT) of the second gate dielectric is less than an EOT of the first gate dielectric.
However, in the same semiconductor device manufacturing field of endeavor, Arimura discloses a transistor (transistor in [0010], Fig. 3) having a gate dielectric structure (102,103,104 a SiO2 layer 102, a LaSiO layer 103, a HfO2 layer 104 in [0070], Fig. 3) comprising a height (H-102,103,104 having a height of around 6nm, Fig. 3-Annotated) over the first surface (Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the source follower transistor of the combination of Ogino and Yamashita having a gate dielectric structure according to the Arimura’s method to provide a transistor having high performance, high mobility and excellent BTI reliability ([0009], Arimura).
The combination of Ogino, Yamashita and Arimura results in a height (13B, a height/thickness of 5nm Yamashita, Fig. 2) of the first gate dielectric (13B, made of SiO2, Yamashita, Fig. 2) over the first surface of the first substrate (51, Yamashita, Fig. 2) is less than a height (102,103,104, having a height of around 6nm, Arimura, Fig. 3) of the second gate dielectric (102,103,104, Arimura, Fig. 3 applied to Ogino and 14B-d’s Yamashita), wherein an equivalent oxide thickness (EOT) of the second gate dielectric (102,103,104 Fig. 3-Annotated, Arimura) is less (EOT(102,103,104)’s Arimura is around of 0.78nm, using the EOT formula for multiple dielectric layers, applied to Ogino and 14B-d’s Yamashita) than an EOT (EOT(13B)’s Yamashita is around of 5nm, using the EOT formula of one dielectric layer) of the first gate dielectric (13B, Yamashita, Fig. 2).
Re: Claim 27, Ogino modified by Yamashita and Arimura discloses the method of claim 26, further comprising: forming a transistor (102 transistor having a gate dielectric made of silicon oxide in [0080], Ogino) on a second substrate (100 substrate in [0080], Fig. 2, Ogino), wherein the transistor (102, Ogino) comprises a third gate dielectric (102 having a gate dielectric made of silicon oxide in [0080], Ogino) and a third gate electrode (102 having a gate electrode in [0080], Ogino); and bonding (Fig. 2, Ogino) the first substrate (200, Ogino) to the second substrate (100, Ogino).
Ogino modified by Yamashita and Arimura does not expressly disclose wherein an EOT of the third gate dielectric is greater than the EOT of the second gate dielectric.
However, in the same semiconductor device manufacturing field of endeavor, Yamashita discloses a transistor (transistor in [0012]) having a gate dielectric (gate insulating film in [0012], Fig. 2) with a thickness (thickness of 5nm, [0012]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the third gate dielectric of the combination of Ogino having a thickness of 5nm according to the Yamashita’s method to reduce dark current noise for maintaining the signal-to-noise ratio in fine pixels ([0007], Yamashita).
The combination of Ogino, Yamashita and Arimura results in wherein an EOT of the third gate dielectric (EOT’s Yamashita is around of 5nm, using the EOT formula in a SiO2 layer, applied to Ogino) is greater than the EOT (EOT (102,103,104)’s Arimura is around of 0.78nm, using the EOT formula for multiple dielectric layers, applied to Ogino and Yamashita) of the second gate dielectric (102,103,104 Fig. 3-Annotated, Arimura).
Re: Claim 28, Ogino modified by Yamashita and Arimura discloses the method of claim 26,
Ogino modified by Yamashita and Arimura does not expressly disclose further comprising: forming a reset transistor on the first surface of the first substrate and adjacent to the source-follower transistor, wherein a source/drain region of the reset transistor is coupled to the second gate electrode, wherein the reset transistor comprises a third gate dielectric and a third gate electrode, wherein an EOT of the third gate dielectric is greater than the EOT of the second gate dielectric.
However, in the same semiconductor device manufacturing field of endeavor, Yamashita discloses a pixel circuit wherein forming a reset transistor (15 a reset transistor in [0024], Fig. 2) on the first surface of the first substrate (51 a semiconductor substrate in [0035], Fig. 2) and adjacent to the source-follower transistor (14 a amplifying in [0024], Fig. 2), wherein a source/drain region (16 a floating diffusion layer in [0024], Fig. 2) of the reset transistor (15) is coupled to the second gate electrode (14A a gate electrode in [0038], Fig. 2), wherein the reset transistor (15) comprises a third gate dielectric (15B a gate insulating film similar to 13B, having a thickness of 5nm in [0012,0046], Fig. 2)and a third gate electrode (15A a gate electrode in [0038], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yamashita’s method of forming a reset transistor on the first surface of the first substrate and adjacent to the source-follower transistor, wherein a source/drain region of the reset transistor is coupled to the second gate electrode, wherein the reset transistor comprises a third gate dielectric and a third gate electrode to Ogino’s method to reduce dark current noise for maintaining the signal-to-noise ratio in fine pixels ([0007], Yamashita).
The combination of Ogino, Yamashita and Arimura results in wherein an EOT (EOT’s Yamashita is around of 5nm, using the EOT formula in a SiO2 layer, applied to Ogino) of the third gate dielectric (15B, Yamashita) is greater than the EOT (EOT (102,103,104)’s Arimura is around of 0.78nm, using the EOT formula for multiple dielectric layers, applied to Ogino and Yamashita) of the second gate dielectric (102,103,104 Fig. 3-Annotated, Arimura).
Re: Claim 29, Ogino modified by Yamashita and Arimura discloses the method of claim 26, wherein the second gate dielectric (102,103,104 Fig. 3-Annotated, Arimura) comprises a first dielectric layer (102 a SiO2 layer in [0070], Fig. 3, Arimura), a second dielectric layer (103 a LaSiO layer in [0070], Fig. 3) over the first dielectric layer (102 Fig. 3, Arimura), and a third dielectric layer (104 a HfO2 layer in [0070], Fig. 3, Arimura) over the second dielectric layer (103 Fig. 3, Arimura), wherein thicknesses of the second (103 Fig. 3, Arimura) and third (104 Fig. 3, Arimura) dielectric layers are greater (Fig. 3-Annotated, Arimura) than a thickness of the first dielectric layer (102 Fig. 3, Arimura), and wherein relative permittivities of the second (103 Fig. 3, Arimura) and third dielectric layers (104 Fig. 3, Arimura) are greater (LaSiO and HfO2 having a greater relative permittivity than SiO2 in [0070], Fig. 3, Arimura) than a relative permittivity of the first dielectric layer (102 Fig. 3, Arimura).
Re: Claim 30, Ogino modified by Yamashita and Arimura discloses the method of claim 29, wherein the first gate dielectric (13B’s Yamashita, Fig. 2 applied to Ogino) comprises a single continuous layer extending from the first surface of the first substrate (51’s Yamashita, Fig. 2 applied to Ogino) to a lower surface of the first gate electrode (51’s Yamashita, Fig. 2 applied to Ogino).
Ogino modified by Yamashita and Arimura does not expressly disclose wherein a relative permittivity of the first gate dielectric is less than the relative permittivities of the second and third dielectric layers.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to include the first gate dielectric made of silicon oxide since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297, See MPEP 2144.07.
The combination of Ogino, Yamashita and Arimura results in wherein a relative permittivity of the first gate dielectric (13B’s Yamashita, Fig. 2 applied to Ogino) is less (13B-SiO2 having a relative permittivity of 3.9, 103-LaSiO-Arimura having a relative permittivity of 20 and 104-HfO2-Arimura of 25) than the relative permittivities of the second (103’s Arimura, Fig. 3 applied to Ogino and Yamashita) and third (104’s Arimura, Fig. 3 applied to Ogino and Yamashita) dielectric layers.
Re: Claim 31, Ogino modified by Yamashita and Arimura discloses the method of claim 29, wherein the relative permittivity of the second dielectric layer (103’s Arimura, Fig. 3 applied to Ogino and Yamashita) is less (103-LaSiO having a relative permittivity of 20 and 104-HfO2 of 25, Fig. 3, Arimura) than the relative permittivity of the third dielectric layer (104’s Arimura, Fig. 3 applied to Ogino and Yamashita).
Claim(s) 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ogino in view of Yamashita et al., view of Arimura and further in view of Lin et al. (US 20200381465 A1, hereinafter Lin, of the record).
Re: Claim 18, Ogino modified by Yamashita and Arimura discloses the method of claim 17,
Ogino modified by Yamashita and Arimura does not expressly disclose wherein the first transistor and the plurality of second transistors are formed concurrently with one another.
However, in the same semiconductor device manufacturing field of endeavor, Lin discloses wherein the first transistor (116b a second gate in [0021], Fig. 9-12) and the plurality of second transistors (116a, c, d, plurality of gates in [0021], Fig. 9-12) are formed concurrently with one another (transistors 116a, b, c, d are formed at the same time in Fig. 9-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s method wherein the first transistor and the plurality of second transistors are formed concurrently with one another to the combination of Ogino, Yamashita and Arimura to simplify and reduce the cost of the manufacturing.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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