DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/170,111, application filed on 02/16/2023. Claims 1-20 are currently pending in this application.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 04/08/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim(s) 1-2 and 6-10 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Carter et al. (US Patent No. 6,077,308).
6. With respect to independent claim 1, Carter teaches:
generating a plurality of different layout blocks (see design rules for integrating polygon regions in a layout, Col 2 lines 60 through Col 3 line 5), each satisfying predetermined design rules (see complying with design rules, Col 3, lines 1-10) and comprising:
at least one of a plurality of different first block options associated with a first layout feature (see different first gate objects and second source/drain objects as layout features described in Col 5, lines 10-20), and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature (see different first gate objects and second source/drain objects as layout features described in Col 5, lines 10-20),
selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit (choosing a first plurality of objects to place, see Carter, claim 1),
combining the selected layout blocks in accordance with the floorplan into a layout of the circuit (building transistors with the gate and source/drain objects, Col 6, lines 50-60), and
storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit (storing information of built transistors and their placement data in a layout database, Col 6, lines 50-60).
7. With respect to claim 2, Carter teaches:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to: repeatedly perform said selecting and said combining to generate multiple, different layouts of the circuit, and save the multiple, different layouts of the circuit in the cell library (repetitively allowing placement regions in a layout synthesis process, Col 1, lines 35-65; building transistors with the gate and source/drain objects, Col 6, lines 50-60; storing information of built transistors and their placement data in a layout database, Col 6, lines 50-60).
8. With respect to claim 6, Carter teaches:
wherein the first layout feature is a gate region, and the second layout feature is a source/drain contact region (see different first gate objects and second source/drain objects as layout features described in Col 5, lines 10-20).
9. With respect to claim 7, Carter teaches:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to generate the plurality of first block options each of which is a gate region, or a combination of the gate region with at least one of at least one cut region configured to cut or disable a portion of the gate region, or at least one first via over the gate region (see different first gate objects and second source/drain objects as layout features described in Col 5, lines 10-20; determining whether a via cut is present at the gate and source/drain regions, Col 5, lines 1-35).
10. With respect to claim 8, Carter teaches:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to generate the plurality of second block options each of which is a source/drain contact region, or a combination of the source/drain contact region with at least one of at least one cut region configured to cut a portion of the source/drain contact region, or at least one second via over the source/drain contact region (see different first gate objects and second source/drain objects as layout features described in Col 5, lines 10-20; determining whether a via is present at the gate and source/drain regions, Col 5, lines 1-35; determining whether a via cut is present at the gate and source/drain regions, Col 5, lines 1-35).
11. With respect to claim 9, Carter teaches:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to generate the plurality of different layout blocks, each satisfying the predetermined design rules and further comprising: at least one of a plurality of different third block options associated with a third layout feature different from the first layout feature and the second layout feature (see different first gate objects and second source/drain objects as layout features described in Col 5, lines 10-20; see different first gate objects and second source/drain objects as layout features described in Col 5, lines 10-20).
12. With respect to claim 10, Carter teaches:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to generate the plurality of third block options each of which comprises at least one cut region configured to cut a portion of a conductive pattern in a metal layer (determining whether a metal via cut is present at the gate and source/drain regions, Col 5, lines 1-35).
Allowable Subject Matter
13. Claims 11-15 and 16-20 are allowed over the prior art of record.
14. With respect to independent claim 11, and dependent claims 12-15 which depend therefrom, the prior art made of record fails to teach the combination of steps recited in claim 11, including the following particular combination of steps as recited in claim 11, as follows:
a plurality of nets associated with a plurality of alternating gate blocks and source/drain blocks, said method performed at least partially by a processor and comprising:
first mapping, to each gate block in the floorplan and based on one or more nets associated with the gate block, one or more gate block options among a plurality of predetermined gate block options;
second mapping, to each source/drain block in the floorplan and based on one or more nets associated with the source/drain block, one or more source/drain block options among a plurality of predetermined source/drain block options;
selecting, from a plurality of predetermined layout blocks each satisfying predetermined design rules and including at least one of the plurality of predetermined gate block options and at least one of the plurality of predetermined source/drain block options, layout blocks which together include a set of alternating gate block options and source/drain block options correspondingly mapped, by said first mapping and second mapping, to the plurality of alternating gate blocks and source/drain blocks in the floorplan;
combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and
storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit.
15. With respect to independent claim 16, and dependent claims 17-20 which depend therefrom, the prior art made of record fails to teach the combination of steps recited in claim 16, including the following particular combination of steps as recited in claim 16, as follows:
a first region corresponding to a first portion in the floorplan, and a border region, and the second layout block including:
a second region corresponding to a second portion in the floorplan, and a border region identical to the border region of the first layout block; and
combining the first layout block and the second layout block by overlapping the border region of the first layout block with the identical border region of the second layout block, resulting in a combined layout block of the layout of the circuit,
wherein the combined layout block comprises the first region and the second region on opposite sides of the border region.
16. Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
17. With respect to claim 3, the prior art made of record fails to teach the combination of steps recited in claim 3, including the following particular combination of steps as recited in claim 3, as follows:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to: perform an exhaustive search, in which said selecting and said combining are repeatedly performed, to generate all possible layouts of the circuit, and save the all possible layouts of the circuit in the cell library.
18. With respect to claim 4, the prior art made of record fails to teach the combination of steps recited in claim 4, including the following particular combination of steps as recited in claim 4, as follows:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to: execute a Depth-First-Search (DFS) algorithm, in which said selecting and said combining are repeatedly performed, to generate multiple, different layouts of the circuit, and save the multiple, different layouts of the circuit in the cell library.
19. With respect to claim 5, the prior art made of record fails to teach the combination of steps recited in claim 5, including the following particular combination of steps as recited in claim 5, as follows:
wherein the processor is further configured to execute the instructions stored on the computer readable storage medium to combine two layout blocks among the selected layout blocks by abutting the two layout blocks, or overlapping the two layout blocks in an identical border region of the two layout blocks.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851