Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character not mentioned in the description:
“810” in FIG. 8.
This may be corrected by amending “110” in line 4 of paragraph [0054] to --810--.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12, 16-19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Carter et al. [US 6,077,308].
Taking claim 1 as exemplary of claims 1, 8 and 16 [FIG. 8], a method of automatically generating standard cells, the method comprising:
receiving, by a computer system, a definition of a circuit for a standard cell, wherein the circuit comprises one or more semiconductor devices [netlist 120];
identifying, by the computer system, a plurality of slices that implement a device in the one or more semiconductor devices, wherein each of the plurality of slices comprises a partial layout for the device [column 3, lines 16-17, 20-22, FIG. 5 elements 510-570, column 5, lines 9-35, FIG. 6 step 640, FIG. 7A-7B elements 710-770; although the term “slices” is not recited given a broadest reasonable interpretation of the broad language a slice can be interpreted as an object or a region as cited]; and
combining, by the computer system, more than one of the plurality of slices into a combined layout to implement the device when forming the standard cell [column 3, lines 12-13, FIG. 6 loop 605, loop 635, step 655, column 7, lines 29-39].
2. The method of claim 1, wherein the device comprises a functional circuit element [FIGS. 3-4].
3. The method of claim 2, wherein the partial layouts are not functional circuit elements [column 5, lines 14-35], and the combined layout forms the functional circuit element [Table 1 step 655 and FIG. 6 step 655].
4. The method of claim 2, wherein a slice in the plurality of slices includes partial layouts for more than one of the one or more semiconductor devices [FIG. 6 loop 635 repeating to step 640], and wherein the combined layout comprises additional slices that together with the more than one of the plurality of slices implement the one or more semiconductor devices for the standard cell [column 7, lines 25-39].
5. The method of claim 1, wherein: a first slice in the plurality of slices comprises a first partial layout for the device [FIG. 7A element 710]; and a second slice in the plurality of slices comprises a second partial layout for the device [FIG. 7A element 720].
6. The method of claim 5, wherein the first partial layout comprises a layout of a source region or a drain region of a transistor [column 5, lines 27-29, FIG. 7A element 790].
7. The method of claim 5, wherein the second partial layout comprises a layout of a gate region of a transistor [column 5, lines 32-35, FIG. 7A element 785].
9. The system of claim 8, wherein: the plurality of slices comprises a first set of slices that each comprises a different implementation of a first partial layout for the device [FIG. 5 objects 1-7 each depict a different implementation, FIG. 7A regions 710-770 each depict a different implementation]; and the operations further comprise selecting a first slice from the first set of slices for the device [Table 1 line 05 command “for each”, column 6, lines 10-20, FIG. 6 loop 635 repeating to step 640].
10. The system of claim 9, wherein: the first slice comprises a connection to a first intersecting track in a metal layer [FIG. 7A element 775 to FIG. 7B element 795]; and a second slice in a second set of slices for the device comprises a connection to a second intersecting track in the metal layer [FIG. 7A element 720/785 to FIG. 7B element 795; although the reference does not explicitly recite terms such as “intersecting track” and “metal layer” it is interpreted that the first and second features as claimed are depicted as cited with column 7, lines 19-20 and 26, in other words, to connect transistors for building a standard cell there are connections to intersecting tracks in metal layers].
11. The system of claim 8, wherein the operations further comprise: determining one or more device chains for generating a cell layout for the standard cell, wherein the one or more device chains represent connections between devices in the one or more semiconductor devices and inputs and/or outputs in the standard cell [column 5, lines 7-8, column 7, line 19-28 although the term “chain” is not explicitly recited it is interpreted that a cell layout for the standard cell with connections is represented, see also FIGS. 3-4 netA, netB, netC inputs and/or netY output of the gate comprising transistors for building a standard cell].
12. The system of claim 11, wherein the operations further comprise: selecting a set of candidate slices from a slice library that can be used to implement each of the connections [Table 1 line 05 command “for each”, column 6, lines 10-20, FIG. 6 loop 635 repeating to step 640; although the term “candidate” is not explicitly recited it is interpreted that processing each object/region accommodates a set of candidates for selection; FIG. 8 element 820 provides the storage from which selection is made].
17. The one or more non-transitory computer-readable media of claim 16, wherein the definition of the circuit comprises a netlist with device characteristics and connections between the one or more semiconductor devices [netlist 120, column 5, lines 14-16].
18. The one or more non-transitory computer-readable media of claim 16, wherein the operations further comprise: accessing a first slice library for the device to retrieve the plurality of slices, wherein the first slice library comprises partial layouts for different implementations of a first device type for the device [although the term “library” is not explicitly recited it is interpreted that FIG. 8 element 820 provides the storage for accessing, FIG. 5 objects 1-7 each depict a different implementation, FIG. 7A regions 710-770 each depict a different implementation].
19. The one or more non-transitory computer-readable media of claim 18, further comprising a second slice library for the device, wherein the second slice library comprises partial layouts for different implementations of a second device type for the device [although the term “library” is not explicitly recited it is interpreted that FIG. 8 element 820 provides the storage for accessing, FIG. 5 objects 1-7 each depict a different implementation, FIG. 7A regions 710-770 each depict a different implementation].
Claims 1-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chiu et al. [US 2024/0086611 A1].
Taking claim 1 as exemplary of claims 1, 8 and 16 [FIG. 9], a method of automatically generating standard cells, the method comprising:
receiving, by a computer system, a definition of a circuit for a standard cell, wherein the circuit comprises one or more semiconductor devices [0002, 0028 functional cell also referred to as a standard cell, 0077 inherent in utilizing an APR methodology, 0102 inherent in An EDA tool can receive instructions to implement functions and operations described herein];
identifying, by the computer system, a plurality of slices that implement a device in the one or more semiconductor devices, wherein each of the plurality of slices comprises a partial layout for the device [0080 The base layout cell can be selected to provide an efficient layout for an intended functional cell or combination cell, the base layout cell can include one (or more) active layer pattern, conductive gate layer pattern, the base layout cell can include one (or more) layout pattern, 0110 a portion of IC design layout diagram includes various IC features, such as an active region, a gate electrode, a source and drain]; and
combining, by the computer system, more than one of the plurality of slices into a combined layout to implement the device when forming the standard cell [0081 the selected base layout cell is placed in a layout, 0082 functional cells, logic circuits, memory arrays, processors, etc., 0120 fabrication, 0121 fabricate IC device].
2. The method of claim 1, wherein the device comprises a functional circuit element [0026 functional cells, 0028 layout of functional cell, 0030-0031 transistor].
3. The method of claim 2, wherein the partial layouts are not functional circuit elements [0080 the base layout cell can include one (or more) active layer pattern, conductive gate layer pattern, the base layout cell can include one (or more) layout pattern, 0110 a portion of IC design layout diagram includes various IC features, such as an active region, a gate electrode, a source and drain], and the combined layout forms the functional circuit element [0028, 0040 resulting functional cell manufactured based on layout patterns].
4. The method of claim 2, wherein a slice in the plurality of slices includes partial layouts for more than one of the one or more semiconductor devices, and wherein the combined layout comprises additional slices that together with the more than one of the plurality of slices implement the one or more semiconductor devices for the standard cell [0037 intended to be uniformly applied to multiple functional cells, 0076, 0079 a variety of circuits s can be schemed and implemented].
5. The method of claim 1, wherein: a first slice in the plurality of slices comprises a first partial layout for the device [0026 functional cells can be implemented utilizing two or more base layout cells interpreted as a first of the two, 0080 base layout cell can include one (or more) active area layer patterns]; and a second slice in the plurality of slices comprises a second partial layout for the device [0026 functional cells can be implemented utilizing two or more base layout cells interpreted as a second of the two, 0080 base layout cell can include one (or more) conductive gate layer patterns].
6. The method of claim 5, wherein the first partial layout comprises a layout of a source region or a drain region of a transistor [0030].
7. The method of claim 5, wherein the second partial layout comprises a layout of a gate region of a transistor [0034].
9. The system of claim 8, wherein: the plurality of slices comprises a first set of slices that each comprises a different implementation of a first partial layout for the device [0058]; and the operations further comprise selecting a first slice from the first set of slices for the device [0025, 0063].
10. The system of claim 9, wherein: the first slice comprises a connection to a first intersecting track in a metal layer [0029 first metal area layout pattern associated with a conductive pattern arranged for interconnection]; and a second slice in a second set of slices for the device comprises a connection to a second intersecting track in the metal layer [0029 second metal area layout pattern associated with a conductive pattern arranged for interconnection].
11. The system of claim 8, wherein the operations further comprise: determining one or more device chains for generating a cell layout for the standard cell, wherein the one or more device chains represent connections between devices in the one or more semiconductor devices and inputs and/or outputs in the standard cell [0026 sequence is interpreted as device chains, 0126].
12. The system of claim 11, wherein the operations further comprise: selecting a set of candidate slices from a slice library that can be used to implement each of the connections [0002 library, it is interpreted as inherent that FIG. 9 stores the data that can be used, 0092 a specific base layout cell for implementation can be selected based criteria and 0093 functional cells can be implemented based on an efficient selection of a base cell layout from a variety is interpreted as providing candidates for selection, 0025].
13. The system of claim 12, wherein the operations further comprise: assigning tracks in a metal layer to the inputs/outputs in the standard cell [0028, 0029 a conductive pattern arranged for interconnection to the functional cell, FIG. 5A elements A/Q]; optimizing the set of candidate slices by eliminating slices that can be implemented by placing two slices adjacent to each other [0039 removing at least portions, 0054 recognizing layout patterns and attributes that are common, 0055 can be defined to omit features, [0080 base cell can be selected to provide an efficient layout for an intended functional cell or combination cell is interpreted as optimizing]; and optimizing the set of candidate slices by eliminating slices that have conflicting connections to the tracks in the metal layer [0056 the physical structure of an intended functional cell can be characterized as a base layout cell, Features that are not shared are omitted. In some embodiments, conductive patterns are omitted is interpreted as conflicting connections, [0080 base cell can be selected to provide an efficient layout for an intended functional cell or combination cell is interpreted as optimizing].
14. The system of claim 13, wherein the operations further comprise: generating one or more combinations of slices from the set of candidate slices that each implement the standard cell [0026a combination cell to further enhance efficient space utilization, 0060 unique functional cells, 0076-0077 combination cell IC device].
15. The system of claim 14, wherein the operations further comprise: optimizing the one or more combinations of slices based on design rules for the metal layer [0031-0032 metal zero patterns, 0080 base cell can be selected to provide an efficient layout for an intended functional cell or combination cell is interpreted as optimizing, 0114 design rules, 0115 manufacturing rules], wherein the one or more combinations of slices comprise the plurality of slices for the device after optimization [0080 an efficient layout for an intended functional cell or combination cell].
17. The one or more non-transitory computer-readable media of claim 16, wherein the definition of the circuit comprises a netlist with device characteristics and connections between the one or more semiconductor devices [0002, 0028, a netlist is inherent for an APR methodology, EDA tool].
18. The one or more non-transitory computer-readable media of claim 16, wherein the operations further comprise: accessing a first slice library for the device to retrieve the plurality of slices [0002 library, it is interpreted as inherent that FIG. 9 stores the data that can be used], wherein the first slice library comprises partial layouts for different implementations of a first device type for the device [0025, 0058, 0063].
19. The one or more non-transitory computer-readable media of claim 18, further comprising a second slice library for the device [0002 library, it is interpreted as inherent that FIG. 9 stores the data that can be used, whether first or second is immaterial since the subject matter pertains to storing data for the device], wherein the second slice library comprises partial layouts for different implementations of a second device type for the device [0025, 0058, 0063, whether first or second is immaterial since the subject matter pertains to storing data of partial layouts for different implementations of another device type].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Carter et al. [US 6,077,308] in view of Chu et al. [US 2023/0101678 A1].
Carter et al. teach the features from which the claim depends, including wherein the device comprises a transistor [column 5, line 4 transistor creation, Table 1 steps 645 and 650, column 6, lines 45-46], the first device type comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) [column 4, line 2 p-channel or n-channel transistors, column 7, lines 17-1925-26 building a standard cell, P- and N-type transistor]. However, Carter et al. do not teach the second device type comprises a fin field-effect transistor (finFET).
Yet, a finFET is a well-known device type. Chu et al. teach a CAD tool using a standard cell library [FIG. 7] including FinFETs [0027, 0035, 0036]. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because of design choice. Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling, as the semiconductor industry moves toward the 7nm technology node and beyond [0001], providing motivation for the combination to teach MOSFET and finFET, for Carter et al. to be modified for the second device type to comprise a finFET.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. [US 2024/0086611 A1] in view of Peng et al. [US 2023/0260878 A1].
Chiu et al. teach the features from which the claim depends, including wherein the device comprises a transistor [0030 transistor], the first device type comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) [0030-0031, 0092]. However, Chiu et al. do not teach the second device type comprises a fin field-effect transistor (finFET).
Yet, a finFET is a well-known device type. PENG et al. teach standard cell layout designs for ICs [0002], with examples of transistors including finFETs [0049]. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because of design choice. Chiu et al. suggest the use of other transistor types [0168], providing motivation for the second device type to comprise a finFET.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, Maziasz [US 9,293,450 B2] at Abstract, column 1, line 14, column 2, lines 10-11, 39-40, column 3,lines 55-61, column 5, lines 21; Seningen et al. [US 2014/0075401 A1] at FIG. 10, paragraphs [0005, 0006, 0026, 0032, 0033, 0037, 0039, 0043, 0044, 0047, 0066, 0068, 0070, 0073]; deDood [US 5,764,533] at Abstract; Wang et al. [US 7,543,262 B2] at Abstract; Sherlekar et al. [US 2012/0223368 A1] at paragraphs 0002, 0008, 0026, 0027, 0041, 0055-0063]; Chen et al. [US 9,,95,791 B2] at FIG. 7 and column 6, line 11-column 7, line 10; Yang et al. [US 2022/0237358 A1] at paragraph [0104]; Guo et al. [US 2021/0224457 A1] at FIG. 9;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEIGH M GARBOWSKI/Primary Examiner, Art Unit 2851