Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Higman et al. [US 7,386,821 B2].
Taking claim 1 as exemplary of claims 1, 8 and 16, a method of automatically generating standard cells [column 8, lines 51-52 generating an integrated circuit layout], the method comprising:
receiving, by a computer system, a definition of a circuit for a standard cell, wherein the circuit comprises one or more semiconductor devices [column 2, lines 46-47, 51-53 through column 6, lines 33-36, 54-55 according to the requirements of a given application];
identifying, by the computer system, from a first slice library of pre-existing slice definitions [column 8, lines 49-50 a library of primitive cells with edge codes, column 8, lines 55-56 accessing a library of primitive cells with edge codes], a plurality of slices that implement a device in the one or more semiconductor devices [column 2, lines 23-24 primitive cells of a portion of a physical design layout, column 2, lines 41 and 57 semiconductor device of an integrated circuit, any suitable semiconductor material or materials, column 9, lines 1-2 manufacturing the integrated circuit per the integrated circuit layout implement devices in one or more semiconductor devices], wherein each of the plurality of slices comprises a partial layout for the device, and the partial layouts represent non-functional circuit elements [column 2, lines 39-41 a partial-layout feature by itself would not suffice as a functional portion of a semiconductor device of an integrated circuit];
combining, by the computer system, more than one of the partial layouts for the plurality of slices from the first slice library into a combined layout to implement the device when forming the standard cell [column 5, lines 42-43 primitive cells coupled together, column 5, lines 52-column 6, line 23 as a result of coupling together partial layout features, partial-layout features together form full layout features, column 8, lines 56-62 selecting and placing a first and subsequent primitive cells from the library in the formation of an integrated circuit layout], wherein the combined layout forms a functional circuit element implementing the device [column 8, lines 66-67 the integrated circuit layout is complete, column 9, lines 1-2 manufacturing the integrated circuit per the integrated circuit layout implements the device].
As per claim 4, the method of claim 1, wherein a slice in the plurality of slices includes partial layouts for more than one of the one or more semiconductor devices, and wherein the combined layout comprises additional slices that together with the more than one of the plurality of slices implement the one or more semiconductor devices for the standard cell [supra, column 9, 22-24 a subset is representative of a portion of a semiconductor device of the integrated circuit, column 11, line 52-column 12, line 5 primitive cells, when joined, form complete functional devices that can be pieced together to achieve the final physical design].
As per claim 5, the method of claim 1, wherein: a first slice in the plurality of slices comprises a first partial layout for the device [column 9, lines 64-67, column 10, lines 1-3]; and a second slice in the plurality of slices comprises a second partial layout for the device [column 9, lines 64-67, column 10, lines 3-6].
As per claim 6, the method of claim 5, wherein the first partial layout comprises a layout of a source region or a drain region of a transistor [column 2, lines 54-61].
As per claim 7, the method of claim 5, wherein the second partial layout comprises a layout of a gate region of a transistor [column 2, lines 42-54].
As per claim 9, the system of claim 8, wherein: the plurality of slices comprises a first set of slices that each comprises a different implementation of a first partial layout for the device; and the operations further comprise selecting a first slice from the first set of slices for the device [column 2, line 42-column 3, line 49 any suitable material(s) selected according to the requirements of a given device application, column 7, lines 3-4 primitive cells comprising one or more different sizes and partial-layout features].
As per claim 10, the system of claim 9, wherein: the first slice comprises a connection to a first intersecting track in a metal layer; and a second slice in a second set of slices for the device comprises a connection to a second intersecting track in the metal layer [to connect transistors for building a standard cell it is broadly interpreted that there are connections to intersecting tracks in metal layers in the manufactured device].
As per claim 11, the system of claim 8, wherein the operations further comprise: determining one or more device chains for generating a cell layout for the standard cell, wherein the one or more device chains represent connections between devices in the one or more semiconductor devices and inputs and/or outputs in the standard cell [it is broadly interpreted that there are device chains, inputs, outputs, etc.in the manufactured device].
As per claim 12, the system of claim 11, wherein the operations further comprise: selecting a set of candidate slices from the first slice library that can be used to implement each of the connections [column 11, line 52-column 12, line 4 ].
As per claim 17, the one or more non-transitory computer-readable media of claim 16, wherein the definition of the circuit comprises a netlist with device characteristics and connections between the one or more semiconductor devices [the Examiner takes official notice that a netlist is well known and well within the ordinary level of skill in the art].
As per claim 18, the one or more non-transitory computer-readable media of claim 16, wherein the operations further comprise: accessing the first slice library for the device to retrieve the plurality of slices, wherein the first slice library comprises partial layouts for different implementations of a first device type for the device [column 2, line 42-column 3, line 49 any suitable material(s) selected according to the requirements of a given device application, column 7, lines 3-4 primitive cells comprising one or more different sizes and partial-layout features].
As per claim 19, the one or more non-transitory computer-readable media of claim 18, further comprising a second slice library for the device, wherein the second slice library comprises partial layouts for different implementations of a second device type for the device [column 2, line 42-column 3, line 49 any suitable material(s) selected according to the requirements of a given device application, column 7, lines 3-4 primitive cells comprising one or more different sizes and partial-layout features, column 11, lines 28-30 given that non-functional primitive cells are technology independent it would have been obvious to generate a second library according to FIG. 5 for a variety of given device applications as described above].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is are rejected under 35 U.S.C. 103 as being unpatentable over Higman et al. [US 7,386,821 B2] in view of Chu et al. [US 2023/0101678 A1] or Peng et al. [US 2023/0260878 A1].
As per claim 20, it is understood, given a device application, that Higman et al. teach the one or more non-transitory computer-readable media of claim 19, wherein the device comprises a transistor, the first device type comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) [column 2, lines 46-48, 54, 57-61, 66, column 3, lines 3-6, 18-19, 37, 46-49]. However, Higman et al. do not teach and the second device type comprises a fin field-effect transistor (finFET).
Chu et al. teach a CAD tool using a standard cell library [FIG. 7] including FinFETs [0027, 0035, 0036]. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because of design choice. Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling, as the semiconductor industry moves toward the 7nm technology node and beyond [0001], providing motivation for the combination to teach MOSFET and finFET, for Higman et al. to be modified for the second device type to comprise a finFET.
As an alternative interpretation, PENG et al. teach standard cell layout designs for ICs [0002], with examples of transistors including finFETs [0049]. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because of design choice. A finFET is a well-known device type and choosing MOSFET and finFET for the device types provides design options for a given device application and given technology.
Response to Arguments
Applicant’s arguments with respect to Carter et al. and Chiu et al. have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LEIGH M GARBOWSKI/Primary Examiner, Art Unit 2851
Prosecution Insights