DETAILED ACTION
This action is responsive to the application No. 18/170,773 filed on February 17, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/06/2026 responding to the Office action mailed on 11/06/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 2020/0321432) in view of Boles (US 2019/0229114).
Regarding Claim 1, Wei (see, e.g., Fig. 3), teaches an integrated circuit 350 comprising:
a first integrated device Device-1 over a first semiconductor structure 201a/100 in a first region 001 of the integrated circuit 350 (see, e.g., pars. 0021, 0031);
a second integrated device Device-2 over a second semiconductor structure 201b/100 in a second region 002 of the integrated circuit 350 (see, e.g., pars. 0021, 0031);
wherein:
the first semiconductor structure 201a/100 and the second semiconductor structure 201b/100 comprise at least one layer of gallium nitride material 201a/201b over a base semiconductor substrate 100 (see, e.g., par. 0031); and
the third region 003 comprises an insulating material 401 that extends through the at least one layer of gallium nitride material 201a/201b (see, e.g., par. 0031).
Wei does not show a passive component over a third region of the integrated circuit, and that the insulating material extends through the base semiconductor substrate and separates the base semiconductor substrate between the first semiconductor structure and the second semiconductor structure.
Boles (see, e.g., Fig. 1), in similar devices to Wei, on the other hand, teaches a passive component 120/130 over a third region of the integrated circuit, exhibiting lower loss than they would if formed over semiconductor material, and an insulating material 170 extending through the base semiconductor substrate 105 and separating the base semiconductor substrate 105 between the first semiconductor structure 107/105 and the second semiconductor structure 151/105, providing improved electrical isolation between semiconductor devices, lower permittivity compared to semiconductor material, and structural support for RF circuitry. Also, a transparent insulating material 170 can also provide optical visibility through the wafer on which ICs are fabricated, which can facilitate backside alignment for patterning structures on a backside of the IC (see, e.g., par. 0042).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Wei’s device, a passive component over a third region of the integrated circuit and the insulating material extending through the base semiconductor substrate and separating the base semiconductor substrate between the first semiconductor structure and the second semiconductor structure, as taught by Boles, to form RF circuit elements exhibiting lower loss than they would if formed over semiconductor material, and to provide improved electrical isolation between semiconductor devices, lower permittivity compared to semiconductor material, and structural support for RF circuitry.
Regarding Claim 2, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Fig. 1), teaches that:
the passive component 120/130 comprises a network of passive components (see, e.g., par. 0043); and
the network of passive components comprises at least one capacitor 130 and at least one inductor 120 (see, e.g., par. 0043).
Regarding Claim 3, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Fig. 1), teaches that the passive component 120/130 comprises a network of passive components for impedance matching of the integrated circuit (see, e.g., par. 0035).
Regarding Claim 4, Wei and Boles teach all aspects of claim 1. Wei (see, e.g., Fig. 3), teaches that:
the first semiconductor structure 201a/100 comprises a first island of gallium nitride material 201a formed over the semiconductor substrate 100 (see, e.g., par. 0031);
the first integrated device Device-1 is over the first island of gallium nitride material 201a (see, e.g., par. 0031);
the second semiconductor structure 201b/100 comprises a second island of gallium nitride material 201b formed over the semiconductor substrate 100 (see, e.g., par. 0031); and
the second integrated device Device-2 is over second the island of gallium nitride material 201b (see, e.g., par. 0031).
Regarding Claim 5, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Figs. 1, 5), teaches a semiconductor pedestal 465 in the third region, the semiconductor pedestal 465 separated from the first semiconductor structure 107/105 and the second semiconductor structure 151/105 by the insulating material 170 (see, e.g., par. 0063).
Regarding Claim 6, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Fig. 1), teaches a ground plane 190 on a back side of integrated circuit (see, e.g., par. 0044).
Regarding Claim 7, Wei and Boles teach all aspects of claim 6. Boles (see, e.g., Fig. 1), teaches that the insulating material 170 contacts the ground plane 190 between the first semiconductor structure 107/105 and the second semiconductor structure 151/105.
Regarding Claim 8, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Fig. 1), teaches further comprising:
a ground plane 190 on a back side of the integrated circuit (see, e.g., par. 0044); and
a semiconductor pedestal 465 in the third region (see, e.g., par. 0063), wherein:
the passive component 120/130 is electrically coupled to the ground plane 190 through an interconnect 124 supported along at least one surface of the semiconductor pedestal 465 (see, e.g., par. 0043).
Regarding Claim 9, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Fig. 1), teaches that the insulating material 170 comprises glass (see, e.g., par. 0042)
Regarding Claim 10, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Fig. 1), teaches that the passive component 120/130 is over the insulating material 170.
Regarding Claim 11, Wei and Boles teach all aspects of claim 1. Wei (see, e.g., Fig. 5), teaches that the first integrated device Device-1 comprises a transistor and the second integrated device Device-2 comprises a diode (see, e.g., par. 0033).
Regarding Claim 12, Wei and Boles teach all aspects of claim 1. Wei (see, e.g., Fig. 3), teaches that the first integrated device Device-1 comprises a first transistor and the second integrated device Device-2 comprises a second transistor (see, e.g., par. 0031).
Regarding Claim 13, Wei and Boles teach all aspects of claim 1. Boles (see, e.g., Fig. 1), teaches a passivation layer 180 over the first integrated device 110, the second integrated device 150, and the passive component 120/130 (see, e.g., par. 0043).
Regarding Claim 14, Wei (see, e.g., Fig. 3), teaches an integrated circuit 350 comprising:
a first integrated device Device-1 over a first semiconductor structure 201a/100 in a first region 001 of the integrated circuit 350 (see, e.g., pars. 0021, 0031);
a second integrated device Device-2 over a second semiconductor structure 201b/100 in a second region 002 of the integrated circuit 350 (see, e.g., pars. 0021, 0031);
an insulating material 401 in a third region 003 of the integrated circuit 350 (see, e.g., par. 0031); and
a ground plane 306B on a back side of the integrated circuit 350 (see, e.g., pars. 0023-0024),
wherein:
the first semiconductor structure 201a/100 and the second semiconductor structure 201b/100 comprise gallium nitride material 201a/201b over a semiconductor substrate 100 (see, e.g., par. 0031); and
Wei does not show that the insulating material in the third region extends through the semiconductor substrate to the ground plane and separates the semiconductor substrate between the first semiconductor structure and the second semiconductor structure.
Boles (see, e.g., Fig. 1), in similar devices to Wei, on the other hand, teaches an insulating material 170 extending through the semiconductor substrate 105 to the ground plane 190 and separating the semiconductor substrate 105 between the first semiconductor structure 107/105 and the second semiconductor structure 151/105, providing improved electrical isolation between semiconductor devices, lower permittivity compared to semiconductor material, and structural support for RF circuitry. Also, a transparent insulating material 170 can also provide optical visibility through the wafer on which ICs are fabricated, which can facilitate backside alignment for patterning structures on a backside of the IC (see, e.g., par. 0042).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Wei’s device, an insulating material extending through the semiconductor substrate to the ground plane and separating the semiconductor substrate between the first semiconductor structure and the second semiconductor structure, as taught by Boles, to form RF circuit elements exhibiting lower loss than they would if formed over semiconductor material, and to provide improved electrical isolation between semiconductor devices, lower permittivity compared to semiconductor material, and structural support for RF circuitry.
Regarding Claim 15, Wei and Boles teach all aspects of claim 14. Boles (see, e.g., Fig. 1), teaches a passive component 120/130 over the insulating material 170 in the third region of the integrated circuit (see, e.g., par. 0043).
Regarding Claim 16, Wei and Boles teach all aspects of claim 14. Boles (see, e.g., Figs. 1, 5), teaches a semiconductor pedestal 465 in the third region, the semiconductor pedestal 465 being separated from the first semiconductor structure 107/105 and the second semiconductor structure 151/105 by the insulating material 170 (see, e.g., par. 0063).
Regarding Claim 17, Wei and Boles teach all aspects of claim 14. Boles (see, e.g., Fig. 1), teaches:
a passive component 120/130 over the insulating material 170 in the third region of the integrated circuit (see, e.g., par. 0043); and
a semiconductor pedestal 465 in the third region (see, e.g., par. 0063), wherein:
the passive component 120/130 is electrically coupled to the ground plane 190 through an interconnect 124 supported along at least one surface of the semiconductor pedestal 465 (see, e.g., par. 0043).
Regarding Claim 18, Wei and Boles teach all aspects of claim 14. Wei (see, e.g., Fig. 3), teaches that the first integrated device Device-1 comprises a transistor, and the second integrated device Device-2 comprises a diode (see, e.g., par. 0033).
Regarding Claim 19, Wei and Boles teach all aspects of claim 14. Wei (see, e.g., Fig. 3), teaches that the first integrated device Device-1 comprises a first transistor and the second integrated device Device-2 comprises a second transistor (see, e.g., par. 0031).
Regarding Claim 20, Wei and Boles teach all aspects of claim 14. Boles (see, e.g., Fig. 1), teaches a passivation layer 180 over the first integrated device 110 and the second integrated device 150 (see, e.g., par. 0043).
Response to Arguments
Applicant's arguments filed on 02/06/2026 with respect to the rejection of claim 1 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814