DETAILED ACTION
This Office action is in response to the Election filed on 12 March 2026. Claims 1-18, 21, and 22 are pending in the application. Claims 19-20 have been cancelled.
This application is a continuation of application Serial No. 17/343,335, filed on 09 June 2021; now US Patent 11,587,872.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, Species II in the reply filed on 12 March 2026 is acknowledged. The traversal is on the ground(s) that the Office Action fails to recognize that alleged Species 1 is also shown in FIG. 5A and FIG. 5B. Applicant has further argued that both Independent Claim 1 and Independent Claim 10 (sic) are directed to FIG. 5A and FIG. 5B, and features of both Independent Claims 1 and Independent Claim 10 (sic) are depicted in FIG. 5A and FIG. 5B.
This is not found persuasive because Species 1 requires “forming a bottommost metal layer of the interconnect structure, wherein the bottommost metal layer has metal lines connected to the memory cell, wherein the metal lines include a bit line, a first voltage line for receiving a first voltage, a voltage line landing pad, and a word line landing pad, wherein a width of the bit line is a widest width of the metal lines”. As shown in Fig. 5A, the bottommost metal layer includes a bit line 280A, a bit line bar 280B, a first a first voltage line 28C, a word line landing pad 280D, and a voltage line landing pad 280G, wherein the bit line 280A and the bit line bar 280B have the widest widths. Claim 1 does not require the bit line bar 280B to be formed from the bottommost metal layer. Rather, independent claim 1 requires “forming a bit line bar, a word line, and a second voltage line for receiving a second voltage that is different than the first voltage, wherein the second voltage line is connected to the voltage line landing pad and the word line is connected to the word line landing pad.” From the language of independent claim 1, it appears that the bit line bar is not formed from the bottommost metal layer. Accordingly, it does not appear that the method of claim 1 reads on Figs. 5A and 5B. Moreover, contrary to Applicant’s arguments, the Office action did not identify species solely by reference to Applicant's claims, rather than by reference to Applicant's figures. The restriction requirement properly identified each species by using the distinguishing characteristics of each method of each species, by using the patent application figures, and by indicating which claims each species is readable on, to facilitate Applicant’s election of the two species identified in the Office action, in accordance with the MPEP.
Applicant has argued that the Office Action fails to properly identify any species upon which an election of species requirement can properly be based, since Applicant’s specification discloses "[i]n some embodiments, the features of SRAM cell 200 are configured to provide an SRAM circuit, such as depicted in FIG. 2 and/or FIG. 3." First, the method of claim 1 is clearly drawn to the fabrication of an SRAM circuit, which is why Species I has been identified by using Fig. 2. Second, Applicant’s specification does not include any fragmentary diagrammatic views of the SRAM cell made by the method of independent claim 1. Rather, the figures of the instant application are drawn to the method of independent claim 11, wherein the first metal layer further includes a bit line bar (dependent claim 13). Independent claim 11 does not preclude the first metal layer from including a bit line bar (see dependent claim 13), nor does claim 11 require the bit line have a widest width of the metal lines of the first metal layer. All of the fragmentary diagrammatic views of Applicant’s SRAM cell show the bottommost metal layer or the first metal layer including the bit line 280A and the bit line bar 280B, wherein both the bit line and the bit line bar have the widest width of the metal lines 280C, 280D, 290E, 280F, and 280G. Therefore, the most appropriate figure to identify Species I is Fig. 2.
Newly-submitted claims 21-22 appear to be drawn to another species of Applicant’s invention, since claim 21 requires “forming a first metallization layer of a multilayer interconnect structure that includes a bit line, a bit line bar, and a first voltage line configured to receive a first voltage, wherein the bit line, the bit line bar, and the first voltage line extend along a first routing direction, the first metallization layer is a bottommost metallization layer of the multilayer interconnect structure, and a bit line width of the bit line has a widest width of metal lines of the first metallization layer”. As noted in Fig. 9A, both the bit line 280A and the bit line bar 28B have the widest width W1. Consequently, Applicant’s election of Invention I, Species II, on which claims 11-18, are readable, is acknowledged. Claims 11-18 have been examined herein.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, US 2016/0372182 in view of Fujiwara et al., US 2017/0110461.
With respect to independent claim 11, Liaw disclose a method comprising:
forming a memory cell (see the Abstract); and
forming an interconnect structure, shown in Fig. 3 and 5) electrically coupled to the memory cell,
wherein the forming the interconnect structure includes:
forming a first metal layer (502, see Fig. 5 and paragraph [0023]) electrically coupled to the memory cell, wherein the first metal layer 502 includes a bit line 212, a first voltage line 208 configured to receive a first voltage, a first voltage line landing pad 220, and a first word line landing pad 412, see Figs. 3 and 5 and paragraph [0043],
forming a second metal layer (504, see Fig. 5) over the first metal layer 502, as shown in Fig. 5, wherein the second metal layer 504 includes a first word line 210 electrically coupled to the first word line landing pad 412 and a second voltage line landing pad 505 electrically coupled to the first voltage line landing pad 220, see Figs. 3 and 5 and paragraphs [0045] and [0048],
forming a third metal layer (506, see Fig. 5) over the second metal layer 504, as shown in Fig. 5, wherein the third metal layer 506 includes a second voltage line 507 electrically coupled to the second voltage line landing pad 505 and the second voltage line is configured to receive a second voltage, see paragraph [0046],
forming a fourth metal layer (508, see Fig. 5) over the third metal layer 506, as shown in Fig. 5, wherein the fourth metal layer includes a second word line 509, see paragraph [0051], and
wherein the bit line, the first voltage line, and the second voltage line extend along a first lengthwise direction, the first word line and the second word line extend along a second lengthwise direction that is different than the first lengthwise direction, see paragraphs [0043], [0045]-[0046], and [0051].
Liaw lacks anticipation only of a first width of the bit line 212 is greater than a second width of the first voltage line 208. However, Liaw disclose that increasing the width of the bit lines reduces the resistance of these metal lines, see paragraph [0046]. Furthermore, in the same field of endeavor, Fujiwara et al. disclose a method of fabricating a SRAM in which a first width of the bit line is greater than a second width of a first voltage line, as shown in Fig. 2C of Fujiwara et al. In light of the disclosures of both Liaw and Fujiwara et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a first width of the bit line in the known method of Liaw could have been greater that a second width of the first voltage line, thereby reducing the resistance of the bit line.
With respect to claim 15, as shown in Fig. 5 of Liaw, the second word line 509 is electrically coupled to the first word line 505.
With respect to claim 16, Liaw disclose the method further comprises forming an edge cell 814, as shown in Fig. 8A. wherein the second word line is electrically coupled to the first word line by a first connection in the memory cell and a second connection in the edge cell, see paragraph [0070].
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, US 2016/0372182 in view of Fujiwara et al., US 2017/0110461, as applied to claim 11 above, further in view of Liaw, US 7,269,056, hereinafter Liaw ‘056.
Liaw and Fujiwara are applied as above. Liaw fails to teach or suggest the fourth metal layer further includes a third voltage line configured to receive the second voltage. However, in the same field of endeavor, Liaw ‘056 disclose a fourth metal layer can include voltage lines, see the Abstract. In light of this disclosure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the fourth metal layer in the known method of Liaw could include a third metal line configured to receive the second voltage. It further would have been obvious to electrically couple the third voltage line in the fourth metal layer to the second voltage line in order to provide voltage to the second and third metal layers.
Allowable Subject Matter
Claims 12, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Liaw, as applied above. However, the combination of Liaw and Fujiwara et al. fails to teach or suggest the first width of the bit line is greater than a third width of the first voltage line landing pad and a fourth width of the first word line landing pad, as required in dependent claim 12. With respect to claim 13, the combination of Liaw and Fujiwara et al. fail to teach or suggest the first metal layer further includes a bit line bar that extends along the first lengthwise direction, wherein a third width of the bit line bar is greater than the second width of the first voltage line.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various methods of fabricating SRAMs. In particular, Hirose, WO 2025/004736 discloses a bit line having a width greater than a voltage line, as shown in Fig. 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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