DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karikalan et al. (US 2013/0168854) in view of Gao et al. (US 2021/0296282, of record).
Karikalan et al. discloses, as shown in Figures 1A-1C and 3, a chip package structure comprising:
a package carrier (102), including a plurality of carrier pads (not shown but inherent between the package carrier (102) and the solder bumps (142));
a plurality of chips (110,120), arranged side by side on the package carrier, wherein each of the plurality of chips includes a plurality of first pads (not shown but inherent between the solder bumps (142)/(144) and the chips (110,120), also note [0017]) and a plurality of second pads (not shown but inherent between the solder bumps (142) and the chips (110,120));
a bridge (130), located between the plurality of chips and the package carrier, wherein the bridge has a surface, and includes a plurality of bridge pads (144, [0015] bumps may be substituted al pads, also see Figures 2-3) located at the surface, wherein a portion of the surface of the bridge located between two of the plurality of chips is exposed to an outside environment,, each of the plurality of first pads is bonded with each of the plurality of bridge pads to form the bonding pad, so that the plurality of chips is electrically connected to each other through the bridge; and
a plurality of solder balls or C4 bumps (142), located between the package carrier and the plurality of chips, wherein the plurality of second pads of each of the plurality of chips is electrically connected with the plurality of carrier pads of the package carrier through the plurality of solder balls or C4 bumps.
Karikalan et al. does not disclose the bonding pad is a hybrid bonding pad. However, Gao et al. discloses a chip package having a plurality of first pads (4b) is hybrid bonded with each of a plurality of second pads (4a) to form the hybrid bonding pad (direct bonding pad). Note Figures 1A-1B, 2D and [0032]-[0033] of Gao et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the bonding pad of Karikalan et al. being the hybrid bonding pad, such as taught by Gao et al. in order to further improve the interconnect conductivity between the pads
Regarding claim 2, Karikalan et al. and Gao et al. disclose the material of each of the plurality of first pads and the material of each of the plurality of bridge pads are respectively metal materials ([0034]).
Regarding claim 3, Karikalan et al. and Gao et al. disclose the plurality of solder balls or C4 bumps (142) is disposed on the plurality of carrier pads of the package carrier (not shown but inherent between the package carrier (102) and the solder bumps (142), [0017], Figures 1A-1C, 3).
Regarding claim 4, Karikalan et al. and Gao et al. disclose the plurality of solder balls or C4 bumps (142) is disposed on the plurality of second pads of each of the plurality of chips (not shown but inherent between the solder bumps (142) and the chips (110,120), [0017], Figures 1A-1C, 3).
Regarding claim 5, Karikalan et al. and Gao et al. does not disclose the thickness of the bridge as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 6, Karikalan et al. and Gao et al. disclose the surface of the bridge is flush with an active surface of each of the plurality of chips (Figures 1A-1B and 2C of Gao et al.)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUNG K VU/ Primary Examiner, Art Unit 2897