Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 01/21/23. Claims 1-20 are pending in this application.
Information disclosure statement
The information disclosure statement filed on 02/21/23 has been received and is being considered.
Claim Rejections under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9, and 11-20 are rejected under 35 U.S.C. §102 as being unpatentable over Parekhji (US 10684322 B2).
Regarding claim 1, Parekhji discloses a reticle (see figs 2), comprising: a body having a single-use illumination field defined therein (see fig 2, disclosing IC clusters), the single-use illumination field defining a layer including: a plurality of integrated circuit (IC) die clusters (see fig 2), each of the plurality of IC die clusters including a plurality of IC dies separated by a first scribe line having a first width (see 206, see col 4, ln 45-60 disclosing scribe line 204 is thicker than 206), wherein the plurality of IC die clusters are arranged in juxtaposition on the body (see fig 2, disclosing juxtaposition) and are separated by a second scribe line having a second width larger than the first width(see 204, see col 4, ln 45-60 disclosing scribe line 204 is thicker than 206), and wherein the plurality of IC die clusters each have a same number of IC dies and a same area (see even distribution of IC’s in fig 2).
Regarding claim 2, Parekhji discloses the reticle of claim 1, wherein the layer of the single-use illumination field includes an optical or electrical test structure in an area of the second scribe line, and wherein the first scribe line is devoid of any optical or electrical test structure therein (see testing dies are formed interstitially).
Regarding claim 3, Parekhji discloses the reticle of claim 1, wherein the second scribe line extends around each of the plurality of IC die clusters individually (see fig 2 where 206/204 surround IC’s).
Regarding claim 4, Parekhji discloses the reticle of claim 1, wherein the second scribe line extends around collectively all of the plurality of IC die clusters(see fig 2 where 206/204 surround IC’s).
Regarding claim 5, Parekhji discloses the reticle of claim 1, wherein the plurality of IC die clusters includes at least three IC die clusters in an X direction, and a different number of IC die clusters in a Y direction(see 3x2 arrangement in fig 2).
Regarding claim 6, Parekhji discloses a method, comprising: generating a plurality of reticle setups (see IC chips in fig 2), each reticle setup representing (see fig 2 disclosing representation) a single-use reticle field arrangement and addressing a given set of design rules (see col 3, ln 16-34), each reticle setup defining a layer including: a plurality of integrated circuit (IC) die clusters (see fig 2, disclosing IC die clusters), each of the plurality of IC die clusters including a plurality of IC dies separated by a first scribe line having a first width (see 206, see col 4, ln 45-60 disclosing scribe line 204 is thicker than 206), wherein the plurality of IC die clusters are arranged in juxtaposition (see fig 2, disclosing juxtaposition) to one another and are separated by a second scribe line having a second width larger than the first width(see 204, see col 4, ln 45-60 disclosing scribe line 204 is thicker than 206), and wherein the plurality of IC die clusters each have a same number of IC dies and a same area (see 3x2 arrangement in fig 2), and a different number of IC dies in an X direction than in a Y direction(see 3x2 arrangement in fig 2); and fabricating a reticle including the reticle setup of the plurality of reticle setups having a smallest effective die area (see fig 4b and col 5, ln 26-33).
Regarding claim 9, Parekhji discloses the method of claim 6, further comprising using a plurality of the reticles to form a semiconductor wafer including the plurality of IC dies (see para [0047] mentioning wafer formation).
Regarding claim 11, Parekhji discloses the method of claim 9, wherein the second scribe line extends around collectively all of the plurality of IC die clusters (see fig 2, where scribe lines are circumferential).
Regarding claim 12, Parekhji discloses the method of claim 9, wherein the plurality of IC die clusters includes at least three IC die clusters in an X direction, and a different number of IC die clusters in a Y direction(see 3x2 arrangement in fig 2).
Regarding claim 13, Parekhji discloses the method of claim 9, further comprising testing a first IC die in a first IC die cluster by comparing the first IC die to a second IC die in a second, different IC die cluster (see fig 2, disclosing cluster comparison).
Regarding claim 14, Parekhji discloses the method of claim 9, further comprising testing a first IC die in a selected IC die cluster by comparing the first IC die to a second, different IC die in the selected IC die cluster (see fig 2 and col 3, ln 16-35 disclosing cluster comparison).
Regarding claim 15, Parekhji discloses a semiconductor wafer formed using the plurality of reticles according to claim 9 (see fig 2, 4b, col 7, ln 1-4 disclosing finished wafer.)
Regarding claim 16, Parekhji discloses a semiconductor wafer, comprising: a plurality of integrated circuit (IC) die clusters (see fig 2, disclosing IC clusters), each of the plurality of IC die clusters including a plurality of IC dies separated by a first scribe line having a first width(see 204, see col 4, ln 45-60 disclosing scribe line 204 is thicker than 206), wherein the plurality of IC die clusters are arranged in juxtaposition and are separated by a second scribe line having a second width larger than the first width (see 204, see col 4, ln 45-60 disclosing scribe line 204 is thicker than 206), and wherein the plurality of IC die clusters each have a same number of IC dies and a same area, and a different number of IC dies in an X direction than in a Y direction(see 3x2 arrangement in fig 2).
Regarding claim 17, Parekhji discloses the semiconductor wafer of claim 16, wherein all optical or electrical test structures are in an area of the second scribe line (see fig 2, disclosing testing elements being located at scribe lines).
Regarding claim 18, Parekhji discloses the semiconductor wafer of claim 16, wherein the second scribe line extends around each of the plurality of IC die clusters individually (see figs 2a/2b disclosing circumferential 204 and 206).
Regarding claim 19, Parekhji discloses the semiconductor wafer of claim 16, wherein the second scribe line extends around collectively all of the plurality of IC die clusters(see figs 2a/2b disclosing circumferential 204 and 206).
Regarding claim 20, Parekhji discloses the semiconductor wafer of claim 16, wherein the plurality of IC die clusters includes at least three IC die clusters in an X direction, and a different number of IC die clusters in a Y direction(see 3x2 arrangement in fig 2).
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 8, 10 are rejected under 35 U.S.C. §103 as being unpatentable over Parekhji as applied to claim 6 and further in view of Hendrik (US 20240111221 A1).
Regarding claim 7, Parekhji discloses the method of claim 6, but does not explicitly disclose wherein generating the plurality of reticle setups includes reiteratively generating each of the plurality of reticle setups with each iteration changing a selected design rule and reducing the smallest effective die area.
However, Hendrik, at least at paras [0044] and [0045] disclosing machine learning model disclosing wherein generating the plurality of reticle setups (models) includes reiteratively generating each of the plurality of reticle setups with each iteration changing(training a model/ data) a selected design rule and reducing the smallest effective die area (see para [0039] disclosing minimizing errors and reducing die areas by eliminating faulty IC’s, see para [0032]).
Parekhji and Hendrik are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill at a time prior to the effective filing date of the present application to combine Parekhji and Hendrik. Parekhji and Hendrik may be combined by forming the device of Parekhji in accordance with Hendrik. One having ordinary skill in the art would be motivated to combine Parekhji and Hendrik in order to increase IC yield.
Regarding claim 8, Parekhji discloses the method of claim 6,and Hendrik further discloses wherein at least one of the plurality of reticle setups is based on a set of design rules that minimizes an area of the second scribe line (see para [0027]) and accommodates all optical and electrical test structures required for testing a semiconductor wafer in the second scribe line (see par a[0028] disclosing test structures).
Parekhji and Hendrik are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill at a time prior to the effective filing date of the present application to combine Parekhji and Hendrik. Parekhji and Hendrik may be combined by forming the device of Parekhji in accordance with Hendrik. One having ordinary skill in the art would be motivated to combine Parekhji and Hendrik in order to increase IC yield.
Regarding claim 10, Parekhji discloses the method of claim 9, Hendrik discloses wherein forming the semiconductor wafer includes forming at least part of an optical or electrical test structure in an area of the second scribe line (see para [0047] describing reference targets).
Parekhji and Hendrik are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill at a time prior to the effective filing date of the present application to combine Parekhji and Hendrik. Parekhji and Hendrik may be combined by forming the device of Parekhji in accordance with Hendrik. One having ordinary skill in the art would be motivated to combine Parekhji and Hendrik in order to increase IC yield.
Response to Arguments
Applicant asserts that scribe lines are distinct from interconnect lines. However the reference Parekhji at least at col 2, ln 46-47 discloses that the scribe line are used to create landing pads and interconnects. Thus, applicant’s assertions that the interconnect channels are not scribe lines is contradicted by Parekhji.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893