DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to claims 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Sambi et al. (US PGpub: 2018/061982 A1), hereinafter Sambi, in view of Iravani et al. (US Patent: 8716791 B1), hereinafter Iravani
Regarding claim 1, Sambi teaches a structure (Paragraphs [0042] - [0120]; FIG. 5-32) comprising:
a semiconductor layer (26; see also the fabrication process: starting layer 126 in Fig. 19 corresponds to layer 26 in Fig. 5; in Fig. 20 the implantation of the well 28 is shown) having a first surface and a second surface opposite the first surface; and
a device including:
a well region (Fig. 5, 28 &) within the semiconductor layer, wherein the well region extends into the semiconductor layer to a first depth from the second surface; and
at least one porous region (48; Paragraph [0057]) within the well region (28), wherein the at least one porous region extends into the semiconductor layer from the second surface ( Particular Figs. 14 and 15, showing the formation of the porous region truly from the surface of layer 126) to a second depth shallower than the first depth;
a drain region immediately adjacent to the well region (At any rate Sambi discloses, at opposing ends of an active device region, a source region 36 and a drain region 38 and wherein the drain region is within the well region, i.e. in the sense of the present application "immediately adjacent" to the well region); and
a gate (52) on the second surface partially overlaying the well region (FIG. 5) and completely offset from the at least one porous region (48, 48 is offset from 52),
Sambi does not explicitly teach wherein the at least one porous region is laterally between and separated from the drain region and the gate.
However, Iravani teaches one porous region (140C) is laterally between and separated from the drain region (102B) and the gate (108).
Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use Sambi’s structure to modify with teachings as described by Iravani such that the invention in order to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.
Auxiliary rejection:
It is noted that the subject-matter of claim 1 is taught in Schulze et al. (US 2008/0246055 A1) (Paragraphs [0052], [0085], [0086]; FIG. 5), see Fig. 5, well 7 and porous region 5. Note that the entire region 5 can be porous (cf. paragraph [0085]) and that, while in paragraph [0085] region 7 is called "body zone", in paragraph [0052] the usual term "well" is used.
Regarding claim 2, Sambi teaches the structure of claim 1, wherein the drain region (38) is within the well region shallower in depth than the at least one porous region and above the semiconductor layer (26) (It is speculated that what is meant is that the drain region is either within the well region and shallower in depth than the at least one porous region. At least the first option is also disclosed in Sambi, Fig. 5, drain region 38 within the well region 28 and shallower in depth than the porous region 48. At any rate Sambi discloses, at opposing ends of an active device region, a source region 36 and a drain region 38 and wherein the drain region is within the well region, i.e. in the sense of the present application "immediately adjacent" to the well region).
Regarding claim 3, Sambi teaches the structure of claim 1, wherein the at least one porous region includes a single porous region parallel to the drain region (While there is no top view of the layout, the regions in an LDMOS as disclosed in Sambi are generally arranged in parallel to the gate, so that it should be assumed that the drain 38 and the porous region 48 are also parallel. No shapes of the drain and the porous region are however defined in the claim. The claim thus only indirectly implies that the porous region and the drain must have shapes that permits to call their arrangement parallel. It is unclear what shapes fall under this definition. Furthermore the description and drawings disclose drain 112 and porous region 106 stripe-shaped and parallel in a channel width direction.).
Regarding claim 4, Sambi teaches the structure of claim 1, wherein the at least one porous region includes multiple porous regions (since 48 is a nano-structured region. In detail, the nanostructured region 48 is of the same semiconductor material as the one that forms the semiconductor body 30 (for example, silicon), but is porous; i.e., it has a plurality of nanocavities (not shown). In greater detail, the nanocavities of the nanostructured region 48 may be empty, or else may be filled with an inert gas, or else again may be filled in part with an inert gas and in part with a solid material (for example, oxide). Further, the nanocavities may have an approximately spherical shape, with a diameter comprised between 1 nm and 100 nm. It is, however, possible for the nanocavities to have a non-spherical shape, with an equivalent diameter comprised, for example, between 1 nm and 100 nm.).
Regarding claim 5, Sambi teaches the structure of claim 4, wherein the multiple porous regions include at least two porous regions with different dimensions (since 48 is a nano-structured region. It is mentioned here that nano-structured regions have multiple regions and none of the regions have same dimensions. So, it is assumed all regions have different dimensions).
Regarding claim 6, Sambi teaches the structure of claim 1, wherein the drain region above the semiconductor layer (the drain region is above the semiconductor layer.).
Regarding claim 7, Sambi teaches the structure of claim 1, wherein the device further includes an active device region (in the middle in FIG. 5 having 45 etc.) and, at opposing ends of the active device region, the drain region (38) and a source region (36).
Regarding claim 8, Sambi teaches the structure of claim 7, wherein the d gate (gate 52) on the semiconductor layer above the active device region (45) positioned laterally between the source region (36) and the drain region (38) and wherein the at least one porous region (48) is within the well region between the gate (52) and the drain region (38).
Sambi does not explicitly teach
wherein the device further includes:
a gate sidewall spacer above and immediately adjacent to the well region horizontally between the gate and the at least one porous region, wherein a top surface of the well region below the gate sidewall spacer and a top surface of the at least one porous region are co-planar and
a dielectric layer above and immediately adjacent to the second surface, over the at least one porous region, and having opposite ends adjacent to the drain region and the gate sidewall spacer, respectively.
However, Iravani teaches
a gate sidewall spacer above and immediately adjacent to the well region (144, 146, 148 in FIG. 2B) horizontally between the gate and the at least one porous region, wherein a top surface of the well region below the gate sidewall spacer and a top surface of the at least one porous region are co-planar (FIG. 2B) and
a dielectric layer (110) above and immediately adjacent to the second surface, over the at least one porous region (140A, 140B, 140C), and having opposite ends adjacent to the drain region and the gate sidewall spacer, respectively (opposite ends of 110 can be considered adjacent to sidewall spacer and drain region 102B)...
Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use Sambi’s structure to modify with teachings as described by Iravani such that the invention in order to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.
Regarding claim 9, Sambi teaches the structure of claim 8, wherein the gate is separated from the drain region by a first distance and from the source region by a second distance that is less than the first distance (gate 52 is separated from the drain region 38 by a first distance and from the source region 36 by a second distance that is less than the first distance (see Fig. 5).
Regarding claim 10, Sambi teaches the structure of claim 7, wherein a lower portion of the semiconductor layer has a first type conductivity, wherein the well region has a second type conductivity that is different from the first type conductivity, and wherein the drain region and the source region have the second type conductivity at a higher conductivity level than the well region (a lower portion (26) of the semiconductor layer having a first type conductivity (P), the well region (28) having a second type conductivity (N) that is different from the first type conductivity, and the drain region (38) and the source region (36) having the second type conductivity (N) at a higher conductivity level (N+) than the well region (N-).).
Regarding claim 11, Sambi teaches the structure of claim 10, wherein the device further includes an additional well region (34) positioned laterally adjacent to the well region within the semiconductor layer, wherein the additional well region (34) has the first type conductivity at a higher conductivity level than the lower portion of the semiconductor layer, and wherein the source region is immediately adjacent to the additional well region (FIG. 5, 34 has N conductivity and 28 has N-).
Regarding claim 12, Sambi teaches the structure of claim 1, wherein the semiconductor layer comprises silicon, and wherein the at least one porous region comprises a porous silicon (semiconductor layer comprises silicon and the at least one porous region comprises a porous silicon is also disclosed in Sambi, see paragraphs [0043] and [0057]. Schulze also discloses silicon and porous silicon, paragraph [0086].).
Regarding claim 13, Sambi teaches a structure comprising:
a semiconductor layer having a first surface and a second surface opposite the first surface; and
a device including:
an active device region(45) in the semiconductor layer (semiconductor layer comprises silicon and the at least one porous region comprises a porous silicon is also disclosed in Sambi, see paragraphs [0043] and [0057]. Schulze also discloses silicon and porous silicon, paragraph [0086].);
a well region (34 and 28) in the active device region, wherein the well region extends into the semiconductor layer from the second surface to a first depth (Fig. 5, first depth is bottom surface of 28);
at least one porous region (48) within the well region (34 and 28), wherein the at least one porous region extends into the semiconductor layer (semiconductor layer comprises silicon and the at least one porous region comprises a porous silicon is also disclosed in Sambi, see paragraphs [0043] and [0057]. Schulze also discloses silicon and porous silicon, paragraph [0086].) from the second surface to a second depth shallower than the first depth (48 is shallower than first depth. It is speculated that what is meant is that the drain region is either within the well region and shallower in depth than the at least one porous region, or the drain region is above the semiconductor layer. At least the first option is also disclosed in Sambi, Fig. 5, drain region 38 within the well region 28 and shallower in depth than the porous region 48); and
at opposing ends of the active device region (45 and 46) , a source region and a drain region (38), wherein the drain region is immediately adjacent to the well region (38 and 34 adjacent) and parallel to the at least one porous region (48, 48 is parallel to 45))
a drain region immediately adjacent to the well region (At any rate Sambi discloses, at opposing ends of an active device region, a source region 36 and a drain region 38 and wherein the drain region is within the well region, i.e. in the sense of the present application "immediately adjacent" to the well region); and
a gate (52) on the second surface partially overlaying the well region (FIG. 5) and completely offset from the at least one porous region (48, 48 is offset from 52),
Sambi does not explicitly teach wherein the at least one porous region is laterally between and separated from the drain region and the gate.
However, Iravani teaches one porous region (140C) is laterally between and separated from the drain region (102B) and the gate (108).
Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use Sambi’s structure to modify with teachings as described by Iravani such that the invention in order to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897