DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group II, claims 8-27 in the reply filed on December 15, 2025 is acknowledged. Claims 1-7 have been canceled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group. Newly submitted claims 21-27 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: they represent a different species not presented in the original claims , where the openings 310B, 310C may be filled with one or more dielectric plugs prior to forming the source/drain contacts 120, source/drain vias 183 and frontside power rails 280. Then, in backside processing, thinning the substrate 110 may expose the dielectric plugs. The dielectric plugs may then be removed to reopen the openings 310B, 310C, and the through vias 250, 254 may be formed in the reopened openings 310B, 310C. Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-27 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 14-16 and 18 are rejected under 35 U.S.C. 102(a)( 2 ) as being anticipated by Xie et al. (US 2023/0420359 A1; hereafter Xie). Regarding claim 14 , Xie teaches a method (see e.g., Figures 1-23) , comprising: forming a vertical stack of nanostructure channels over a substrate (see e.g., vertical stack of active semiconductor layer 208 over a substrate 202, Para [0099], Figure 18A) ; forming a source/drain region abutting the nanostructure channels (see e.g., source/drain epitaxial layers 214 abutting the active semiconductor layers 208, Para [0102], Figure 18A) ; forming a gate structure wrapping around the nanostructure channels (see e.g., metal gate 210 wraps around the active semiconductor layers 208, Para [0102], Figures 18A, 18B) ; forming a first through via adjacent the gate structure, and a second through via adjacent the gate structure, the first through via and the second through via being on opposite sides of the gate structure (see e.g., a first through via filled with conductive material to form a power bar 262 and a second through via filled with second dielectric layer 230 and, Para [0103], Figures 19A, 21B) ; forming a contact structure having an underside in contact with the source/drain region and the first through via; and (see e.g., first contacts 260 in contact with the power bar 262 and the source/drain epitaxial layer 214, Para [0105], Figures 21C, 21D) forming respective backside conductive features in contact with the first through via and the second through via (see e.g., a backside power rail VDD 272 and VSS 274 are formed into the backside ILD layer 296. VSS 274 is in contact with the first through via and VDD 272 is in contact with the second through via, Para [0107], Figure 23B) . Regarding claim 15 , Xie, as referred in claim 14, further teaches further comprising: exposing the first and second through vias by removing the substrate (see e.g., the first through via, forming a power bar 262 and the second through via filled with second dielectric 230 are exposed when the substrate 202, etch stop layer 203 and silicon layer 204 are removed, Para [0106], Figure 22B) forming a backside dielectric layer in contact with the first and second through vias (see e.g., forming backside ILD 296 in contact with the first and second through vias, Para [0107], Figure 23B) ; and exposing the first and second through vias by forming a first opening and a second opening in the backside dielectric layer (see e.g., openings are formed in the backside ILD 296 exposing the first and second through vias. These openings are to be filled with later with conductive material to form VSS 274 and VDD 272, Para [0107], Figure 23B) ; wherein the forming respective backside conductive features includes depositing a conductive material in the first opening and the second opening (see e.g., conductive material deposited in the openings to form VDD 272 and VSS 274, Para [0107], Figure 23B) . Regarding claim 1 6 , Xie, as referred in claim 15, further teaches wherein the first and second through vias have the same height (see e.g., as shown in Figure 23B both the first through via, forming the power bar 262 and the second through via filled with second dielectric material 230 are of the same height) . Regarding claim 1 8 , Xie, as referred in claim 15, further teaches wherein removing the substrate removes a fin structure underlying the vertical stack of nanostructure channels (see e.g., silicon layer 204, forming the fin structure underlying the vertical stack of active semiconductor layers 208, is also partly removed when the substrate 202 is removed, Figure 22C) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2023/0420359 A1; hereafter Xie) in view of Li et al. (US 2023/0402379 A1; hereafter Li) . Regarding claim 1 7 , Xie, as referred in claim 15, does not explicitly teach “ further comprising: forming a source/drain via on the contact structure; and forming a frontside conductive feature on the first through via ” . Xie teaches a back-end-of-line (BEOL) layer 263 which connects with the first contacts 260 and the power bars 262. It is known in the art that BEOL layer has vias and metal interconnects which would connect to the first contacts 260 and power bars 262 as shown by Li. In a similar field of endeavor Li teaches further comprising: forming a source/drain via on the contact structure; and forming a frontside conductive feature on the first through via (see e.g., forming front side vias 336 electrically connected to contact 332 and the interlevel via 330 as shown in Figure s 3D and 3E ). Therefore, it would have been obvious to one skilled int he art at the time the invention was effectively filed to implement Li’s teachings of further comprising: forming a source/drain via on the contact structure; and forming a frontside conductive feature on the first through via in the method of Xie in order to provide connections to other semiconductor devices in the integrated circuit. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2023/0420359 A1; hereafter Xie) in view of Lee et al. (US 2021/0126135 A1; hereafter Lee) . Regarding claim 1 9 , Xie, as referred in claim 14, further teaches wherein the forming the source/drain region includes epitaxially growing the source/drain region on the nanostructure channels (see e.g., the source/drain 214 is epitaxially grown, Para [0102]) , Xie does not explicitly teach “ further comprising: forming a bottom isolation layer on a fin structure underlying the nanostructure channels; and the source/drain region is isolated from the fin structure by the bottom isolation layer ” . In a similar field of endeavor Lee teaches further comprising: forming a bottom isolation layer on a fin structure underlying the nanostructure channels (see e.g., a dielectric layer 2 45’ is formed on the fin structure 112 underlying the nanochannels 108, Para [00 5 2], Figure 2 8 B) ; and the source/drain region is isolated from the fin structure by the bottom isolation layer (see e.g., the source/drain epitaxy structures 260 are isolated from the fin structure 112 by the dielectric layer 245’, Figure 28B ) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of further comprising: forming a bottom isolation layer on a fin structure underlying the nanostructure channels; and the source/drain region is isolated from the fin structure by the bottom isolation layer in the method of Xie so that the bottom isolation layer can prevent punch through effect between the source/drain epitaxial regions. Regarding claim 20 , Xie, as referred in claim 19, further teaches further comprising: exposing the first and second through vias and the fin structure by removing the substrate (see e.g., the first through via, forming the power bar 262, and the second through via filled with second dielectric layer 230 are exposed when the substrate 202 and the etch stop layer 203 are removed. The silicon layer 204, forming the fin underlying the stack of active semiconductor layers 208, is also partly removed during the substrate removal process, Figure 22C) ; Xie does not explicitly teach “ wherein height of the fin structure is in a range of about 20 nanometers to about 35 nanometers following removal of the substrate ” . "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[ i ]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). Xie teaches partial removal of the fin silicon layer 204, forming the fin structure, upon removal of the substrate 202. This partial removal of 204 reduces the fin height. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the fin height of 20-35nm as such optimization constitutes a routine variation of the structural dimensions without producing unexpected results. Claims 8- 13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2023/0420359 A1; hereafter Xie) . Regarding claim 8 , Xie teaches a method (see e.g., Figures 1-23) , comprising: forming a vertical stack of nanostructure channels over a substrate (see e.g., vertical stack of active semiconductor layer 208 over a substrate 202, Para [0099], Figure 18A ) ; forming a source/drain region abutting the nanostructure channels (see e.g., source/drain epitaxial layers 214 abutting the active semiconductor layers 208, Para [0102], Figure 18A) ; forming a gate structure that wraps around the nanostructure channels and extends past the nanostructure channels in a first direction (see e.g., metal gate 210 wraps around and extends past the active semiconductor layers 208, Para [0102], Figures 18A , 18B) ; forming a first opening that extends through the gate structure (see e.g., a late cut formed through the depth of the nanosheet stacks 281, Para [0103], Figures 19A, 19B, 19C ) ; forming a gate isolation structure in the first opening (see e.g., a first dielectric layer 228 and a second dielectric layer 230 are formed in the areas created by the late cut, Para [0103], Figures 19A, 19B, 19C) ; forming a second opening ….. in a second direction transverse the first direction (see e.g., forming openings for the power bar trench 291 , Para [0104], Figures 20B, 20C ) ; forming a first through via in the second opening ( see e.g., power bars 262 are formed in the second openings, Para [0106], Figure s 21B, 21C, 21D ) ; forming a contact structure in contact with the first through via and the source/drain region; and (see e.g., first contacts 260 in contact with the power bar 262 and the source/drain epitaxial layer 214, Para [0105], Figures 21C, 21D) forming a backside conductive trace in contact with the first through via (see e.g., backside power rail 274 formed into the backside ILD 296 in contact with the power bar 262, Para [0107], Figure 23C) . Xie does not explicitly teach “forming a second opening adjacent the gate isolation structure …. ”; There are finite number of identified, predictable solutions; (1) selectively forming the first openings , filling them with dielectric , and then forming second openings adjacent to the first openings , (2) form ing a fist opening filled with dielectric , and selectively remov ing the dielectric at locations where the second opening is t o be formed . It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.”KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E). Xie teaches the second option that is, selectively forming openings in the dielectric layer 230 for the power bar trench 291 (see e.g., Para [0104], Figures 20B, 20C) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to apply standard lithography/etching techniques to create transverse opening adjacent to the gate isolation structure by choosing either of the known techniques to achieve predictable results. Regarding claim 9 , Xie, as modified, teaches the limitations of claim 8 as mentioned above. Xie further teaches further comprising: forming a second through via offset from the first through via in the first direction (see e.g., a second power bar 262 offset from the first power bar 262 as shown in Figure 21D) ; and forming a second backside conductive trace in contact with the second through via (see e.g., a second backside power rail 274 in contact with the second power bar 262) . Regarding claim 10 , Xie as modified, teaches the limitations of claim 9 as mentioned above. Xie further teaches wherein the first through via and the second through via are formed simultaneously in a first process ( see e.g., both the first and second power bars 262 shown in Figure 21D are formed simultaneously ) . Regarding claim 11 , Xie as modified, teaches the limitations of claim 10 as mentioned above. Xie further teaches wherein the first process includes: depositing a conductive material in the second opening (see e.g., conductive material filled in the first power bar trench 291 to form the power bar 262, Figures 20D, 21D) and in a third opening offset from the second opening in the first direction (see e.g., a second power bar trench 291 formed as shown in Figure 20D offset from the first power bar trench 291 and filled with conductive material to form a second power bar 262 as shown in figure 21D) . Regarding claim 12 , Xie as modified, teaches the limitations of claim 11 as mentioned above. Xie further teaches wherein the first process includes: forming a dielectric liner layer in the second and third openings prior to the depositing the conductive material (see e.g., first dielectric layer 228 is formed in first and second power bar trench 291 prior to depositing a conductive material to form the power bar 262, Para [0105], Figures 20C, 20D, 21D) . Regarding claim 13 , Xie as modified, teaches the limitations of claim 8 as mentioned above. Xie further teaches further comprising: forming a second source/drain region during the forming the source/drain region (see e.g., the second source/drain epitaxial layer 215 is formed during the forming of the first source/drain epitaxial layer 214, Figure s 19B, 19C) ; and forming a second contact structure in contact with the first through via and the second source/drain region (see e.g., first contact 260 is in contact with the power bar 262 and the source/drain epitaxial layer 215, Figures 21C, 21D ) ; wherein the second source/drain region is on an opposite side of the first through via from the source/drain region (see e.g., the second source/drain epitaxial layer 215 is on an opposite side of the power bar 262 from the first source/drain epitaxial layer 214, Figures 21C, 21D) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAKEHA SEHAR whose telephone number is (571)272-4033. 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAKEHA SEHAR/ Examiner, Art Unit 2893 /YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893