DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I in the reply filed on 1/22/2026 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/22/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 7-9, 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20150145907 A1 (Ryu).
Re claim 1, Ryu teaches a display device comprising:
a transistor (driving transistor TR1);
a first pixel electrode connected to the transistor (main anode 124);
a second pixel electrode (auxiliary anode 128) adjacent to the first pixel electrode and connectable to the first pixel electrode by a global transistor (switching unit 116);
a connection pattern (source and drain electrodes of switching unit 116) of the global transistor, the connection pattern contacting the first pixel electrode and the second pixel electrode;
an insulation film (dielectric layers 125/122) on the first pixel electrode, the second pixel electrode and the connection pattern; and
a signal line (gate of switching unit 116) of the global transistor, on the insulation film and crossing the connection pattern, in a plan view (while a plan view is not shown the gate line would extend transverse to the source/drain electrodes Figs. 4-5).
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459
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Re claim 2, Ryu teaches wherein the signal line is spaced apart from and between the first pixel electrode and the second pixel electrode, in the plan view (while a plan view is not shown the gate line would extend transverse to the source/drain electrodes and the cross section view shows that the gate line is between the source/drain electrodes Figs. 4-5).
Re claim 4, Ryu teaches wherein the first pixel electrode and the second pixel electrode are on a same layer and include the same material (Fig. 5 shows same layer and same material given the same shading).
Re claim 7, Ryu teaches wherein the transistor includes an active layer and a gate electrode overlapping the active layer (Fig. 5).
Re claim 8, Ryu teaches wherein the signal line and the gate electrode include the same material (the gate electrode and signal line are the same, the gate is the portion that directly influences the active layer in the TFT whereas the signal line is the portion that extends to the power source).
Re claim 9, Ryu teaches further comprising:
a pixel defining layer (bank 125) on the insulation film and the signal line, the pixel defining layer defining a first opening (opening over 111) corresponding to the first pixel electrode and a second opening (openings over 112) corresponding to the second pixel electrode (Figs. 3, 5);
a first light emitting layer (light emitting material part 126 in region 111) in the first opening (Figs. 3, 5);
a second light emitting layer (light emitting material part 126 in region 112) in the second opening (Figs. 3, 5); and
a common electrode layer (cathode 127) on the first light emitting layer, the second light emitting layer and the pixel defining layer (Fig. 5).
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Re claim 12, Ryu teaches display device including:
a plurality of pixels emitting light of different colors from each other (RGB Fig. 3), and each pixel among the plurality of pixels comprising:
a transistor (driving transistor TR1) through which electrical current is provided to the each pixel (Fig. 4);
a first light emitting diode (main OLED 111 Fig. 4) connected to the transistor;
a second light emitting diode (auxiliary OLED 112 Fig. 4) adjacent to the first light emitting diode and connectable to the first light emitting diode (Fig. 4, 5 show direct electrical connection through switching unit 116); and
a global transistor (switching unit 116) which receives an electrical signal and is connected to the first light emitting diode (Figs. 3-5).
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462
505
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Re claim 13, Ryu teaches wherein the global transistor is turned on by receiving the electrical signal and is turned off by absence of the electrical signal (Fig. 4).
Re claim 14, Ryu teaches wherein the global transistor which is turned off, disconnects the second light emitting diode from the first light emitting diode, and the electrical current flows in the first light emitting diode, and the global transistor which is turned on, connects the second light emitting diode to the first light emitting diode, and the electrical current flows in both the first light emitting diode and the second light emitting diode (Fig. 4).
Allowable Subject Matter
Claims 3, 5-6, 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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