DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on December 30, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-23 and 36-42 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 16 and 36, it is not clear what the newly added limitation, “wherein the liner layer is between a gap between two adjacent first nanostructures” recited on lines 4-5 of claim 16 and lines 6-7 of claim 36 suggests, because the phrase “between a gap between” is grammatically improper and renders the spatial relationship between the liner layer and the two adjacent first nanostructure ambiguous; for example, it is unclear whether the liner layer is disposed within a gap separating the first nanostructures, or positioned between the first nanostructures without necessarily filling a gap. Furthermore, Applicants originally disclosed in Fig. 2D-2 of present application that the liner layer 160 surrounds or encircles two adjacent first nanostructures, rather than the liner layer 160 is solely placed within a gap between the first nanostructures, therefore, it remains unclear what the claimed structural relationship among the liner layer, the gap, and the first nanostructures has.
Claims 17-23 depend on claim 16 and claims 37-42 depend on claim 36, therefore, claims 17-23 and 37-42 are also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16, 18 and 21-23 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by More et al. (US 2022/0029024, Filed: Jul. 27, 2020, hereinafter More).
Regarding claim 16, More discloses for a method for forming a semiconductor structure comprising that
forming a plurality of first nanostructures (a plurality of the second semiconductor layers 25 on the left side of Fig. 8) and a plurality of second nanostructures (a plurality of second semiconductor layers 25 on the right side of Fig. 8) over a substrate (substrate 10, Fig. 8);
forming a liner layer (first dielectric layer 40, Fig. 8) on the first nanostructures (25 on the left, Fig. 8) and the second nanostructures (25 on the right, Fig. 8), because Applicants do not specifically claim that a liner layer is directly on the first and second nanostructures,
wherein the liner layer is between a gap between two adjacent first nanostructures, as the newly added limitation is discussed in 35 U.S.C. 112(b) rejections above;
forming a dielectric structure (second dielectric layer 45, Fig. 8) between the first nanostructures (25 on the left, Fig. 8) and the second nanostructures (25 on the right, Fig. 8), wherein the dielectric structure (45, Fig. 8) is in direct contact with the liner layer (40, Fig. 8);
removing a portion of the liner layer (upper portion of the first dielectric layer 40, Fig. 20C) to expose a first gap between two adjacent first nanostructures (gap between the two adjacent second nanostructures 25 on the left, Fig. 20C) and a second gap between two adjacent second nanostructures (gap between the two adjacent second nanostructures 25 on the right, Fig. 20C), wherein another portion of the liner layer (left-side or right-side portion of the first dielectric layer 40, Fig. 20C) is remaining between the first nanostructures (25 on the left, Fig. 20C) and the dielectric structure (45, Fig. 8), because Applicants do not specifically claim what specific positions of the liner layer are being removed and remain, the upper portion of the first dielectric layer 40 by More is removed to subsequently remove the first semiconductor layers 20 ([0041], Fig. 20C), and therefore, it forms gaps between the second semiconductor layers 25;
forming a first work function layer (a portion of the gate electrode layer 104, Fig. 21C) in the first gap (gap between two adjacent 25 on the left, Fig. 21C), because More further discloses that “one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer 102 and the gate electrode 104. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials.” (emphasis added, [0071]), therefore, one of the multilayers of the work function adjustment layers in a gap between two adjacent 25 on the left in Fig. 21C by More can correspond to the first work function layer in the claimed invention; and
forming a second work function layer (another portion of the gate electrode layer 104, Fig. 21C) over the first work function layer and in the second gap, because another layer of the multilayers of the work function adjustment layers in a gap between two adjacent 25 on the right in Fig. 21C by More can correspond to the second work function layer in the claimed invention ([0071], Fig. 21C). Examiner notes that Applicants originally disclosed that “the first work function layer 172 is a n-type work function layer. In some embodiments, the n-work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or a combination thereof.” (emphasis added, [0098] of the present application), “the second work function layer 174 is made of p-work function layer. In some embodiments, the p-work function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride, tungsten nitride (WN), ruthenium (Ru) or a combination thereof.” (emphasis added, [0103] of the present application), and “the gate fill layer 176 is made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof.” (emphasis added, [0105] of the present application), therefore, the claimed first and second work function layers 172/174 and gate fill layer 176 can be made of the same material; accordingly, they would be indistinguishable and may effectively constitute a single, continuous body.
Regarding claim 18, More further discloses for method for forming the semiconductor structure as claimed in claim 16 that forming a spacer layer (third dielectric layer 50, Fig. 20C) on the liner layer (40, Fig. 20C); and forming a dielectric wall material (material of the second dielectric layer 45, Fig. 20C) on and in direct contact with the spacer layer (50, Fig. 20C), because Applicants do not specifically claim what a spacer layer is made of, what it looks like and/or what it does, the second dielectric layer 45 by More is formed on and in direct contact with the third dielectric layer 50 (Fig. 20C), and it is formed on the right side of the first dielectric layer 40 (Fig. 20C), therefore, it can correspond to the spacer layer in the claimed invention,
wherein the dielectric structure (a composite layer of the second and third dielectric layers 45 and 50, Fig. 20C) is constructed by the spacer layer (50, Fig. 20C) and the dielectric wall material (45, Fig. 20C).
Regarding claim 21, More further discloses for the method for forming the semiconductor structure as claimed in claim 16 that forming the first work function layer (work function adjustment layers, [0071]) on a portion of the dielectric structure (a portion of 45/50, Fig. 20C); and forming the second work function layer (work function adjustment layers, [0071]) on another portion of the dielectric structure (a portion of 45/50, Fig. 20C), because Applicants do not specifically claim where the portion and another portion of the dielectric structure are positioned, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, therefore, an arbitrary portion of the second and third dielectric layers can be selected for each the portion and another portion of the dielectric structure in the claimed invention; since the work function adjustment layers by More can be multilayers of the listed materials in the paragraph [0071], therefore, one layer of the multilayered work function adjustment layers can be formed an arbitrary portion of the layers 45/50 and another layer of the multilayered work function adjustment layers can be formed an another arbitrary portion of the layers 45/50.
Regarding claim 22, More further discloses for the method for forming the semiconductor structure as claimed in claim 16 that forming an isolation structure (isolation insulating layer 30 or shallow trench isolation (STI), [0040], Fig. 20C) over the substrate (10, Fig. 20C); and forming the dielectric structure (45/50, Fig. 20C) over the isolation structure (30, Fig. 20C).
Regarding claim 23, More further discloses for the method for forming the semiconductor structure as claimed in claim 16 that the dielectric structure (45/50, Fig. 20C, also see Fig. 9D) is surrounded by the liner layer (40, Fig. 20C, 9D) when seen from a top-view (Fig. 9D), because Applicants do not specifically claim that the dielectric structure is completely surrounded by the liner layer, the second and third dielectric layers 45/50 by More is partially surrounded by the first dielectric layer 40 when seen from a top-view (Fig. 9D).
Allowable Subject Matter
Claims 31-35 are allowed, because the prior art cited in this Office Action does not teach the newly added limitations, “wherein the first portion of the liner layer in the first region is between two adjacent first nanostructures”, recited on lines 13-14 of claim 31 and claims 32-35 depend on claim 31.
Response to Arguments
Applicant’s arguments with respect to claim(s) 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815